feat! refactor NeBoot for NeKernel.org v1.0.0

Signed-off-by: Amlal El Mahrouss <amlal@nekernel.org>

37 files changed, 117 insertions, 113 deletions

diff --git a/Doxyfile b/Doxyfile
index 89a1faa..b56bcb7 100644
--- a/Doxyfile
+++ b/Doxyfile
@@ -42,7 +42,7 @@ DOXYFILE_ENCODING      = UTF-8
 # title of most generated pages and in a few other places.
 # The default value is: My Project.
 
-PROJECT_NAME           = "CoreBoot"
+PROJECT_NAME           = "NeBoot"
 
 # The PROJECT_NUMBER tag can be used to enter a project or revision number. This
 # could be handy for archiving the generated documentation or if some version
diff --git a/ReadMe.md b/ReadMe.md
index 9d5904f..0ac4b47 100644
--- a/ReadMe.md
+++ b/ReadMe.md
@@ -4,6 +4,10 @@
 [![License: GPL-3.0](https://img.shields.io/badge/license-GPL--3.0-blue.svg)](LICENSE)
 [![QEMU Tested](https://img.shields.io/badge/QEMU-Tested-success)](#)
 
+# Brief
+
+NeBoot is a cross-platform open implementation of a firmware written in C, designed with modularity and portability in mind.
+
 ## Notice for Doxygen:
 
 Build the documentation using Doxygen's `doxygen` CLI tool.
diff --git a/docs/tex/30pin.tex b/docs/tex/30pin.tex
index 4c4b9ae..fa0b314 100644
--- a/docs/tex/30pin.tex
+++ b/docs/tex/30pin.tex
@@ -50,8 +50,8 @@ struct _cb_tpin_recovery_packet
 {
     uint8_t mag[CP_30PIN_MAG_LEN];     // Magic number
     uint8_t kind;                      // Packet kind identifier
-    uint8_t buffer[CB_30PIN_BUFFER_LEN]; // Packet data buffer
-    uint8_t eop[CB_30PIN_EOP_LEN];     // End-of-packet data
+    uint8_t buffer[NB_30PIN_BUFFER_LEN]; // Packet data buffer
+    uint8_t eop[NB_30PIN_EOP_LEN];     // End-of-packet data
 };
 \end{lstlisting}
 
diff --git a/lib/30pin.h b/lib/30pin.h
index 68691b9..7128c3f 100644
--- a/lib/30pin.h
+++ b/lib/30pin.h
@@ -12,11 +12,11 @@
 /// @brief 30pin recovery protocol.
 /// @details This file contains the definitions and structures used for the 30pin recovery protocol.
 
-#define CB_30PIN_MAG "TP"
+#define NB_30PIN_MAG "TP"
 #define CP_30PIN_MAG_LEN (2)
 
-#define CB_30PIN_BUFFER_LEN (498)
-#define CB_30PIN_EOP_LEN (11)
+#define NB_30PIN_BUFFER_LEN (498)
+#define NB_30PIN_EOP_LEN (11)
 
 /// @brief 30pin recovery header.
 /// @param mag magic number.
@@ -26,8 +26,8 @@
 struct _cb_tpin_recovery_packet {
   uint8_t mag[CP_30PIN_MAG_LEN];
   uint8_t kind;
-  uint8_t buffer[CB_30PIN_BUFFER_LEN];
-  uint8_t eop[CB_30PIN_EOP_LEN];
+  uint8_t buffer[NB_30PIN_BUFFER_LEN];
+  uint8_t eop[NB_30PIN_EOP_LEN];
 };
 
 /// @brief 30pin recovery packet kinds.
diff --git a/lib/boot.h b/lib/boot.h
index cf90766..5aab52b 100644
--- a/lib/boot.h
+++ b/lib/boot.h
@@ -8,7 +8,7 @@
 
 ///
 /// @file boot.h
-/// @brief CoreBoot types, data structures, and standard library.
+/// @brief NeBoot types, data structures, and standard library.
 ///
 
 typedef __UINTPTR_TYPE__ uintptr_t;
@@ -66,34 +66,34 @@ typedef ptrtype_t        size_t;
 #define true yes
 #endif  //!_cplusplus
 
-#define CB_RESTART 0
-#define CB_SHUTDOWN 1
+#define NB_RESTART 0
+#define NB_SHUTDOWN 1
 
 #define __COPYRIGHT(s) /* unused */
 
 #ifdef __COMPILE_RISCV__
-#define CB_BOOT_ADDR (0x80020000)
-#define CB_BOOT_ADDR_STR "0x80020000"
-#define CB_FRAMEBUFFER_ADDR 0x40000000L
-#define CB_UART_BASE 0x10000000
-#define CB_FLASH_BASE_ADDR 0x08000000
+#define NB_BOOT_ADDR (0x80020000)
+#define NB_BOOT_ADDR_STR "0x80020000"
+#define NB_FRAMEBUFFER_ADDR 0x40000000L
+#define NB_UART_BASE 0x10000000
+#define NB_FLASH_BASE_ADDR 0x08000000
 
 #define cb_sync_synchronize() __sync_synchronize()
 #elif defined(__COMPILE_POWERPC__)
-#define CB_UART_BASE 0x10000000
-#define CB_BOOT_ADDR 0x1030000
-#define CB_BOOT_ADDR_STR "0x1030000"
-#define CB_FRAMEBUFFER_ADDR 0x40000000L
-#define CB_FLASH_BASE_ADDR 0x08000000
+#define NB_UART_BASE 0x10000000
+#define NB_BOOT_ADDR 0x1030000
+#define NB_BOOT_ADDR_STR "0x1030000"
+#define NB_FRAMEBUFFER_ADDR 0x40000000L
+#define NB_FLASH_BASE_ADDR 0x08000000
 
 #define cb_sync_synchronize() __sync_synchronize()
 #elif defined(__COMPILE_ARM64__)
 
-#define CB_UART_BASE 0x09000000
-#define CB_BOOT_ADDR 0x1030000
-#define CB_BOOT_ADDR_STR "0x1030000"
-#define CB_FRAMEBUFFER_ADDR 0x40000000L
-#define CB_FLASH_BASE_ADDR 0x60000000
+#define NB_UART_BASE 0x09000000
+#define NB_BOOT_ADDR 0x1030000
+#define NB_BOOT_ADDR_STR "0x1030000"
+#define NB_FRAMEBUFFER_ADDR 0x40000000L
+#define NB_FLASH_BASE_ADDR 0x60000000
 
 static inline void __sync_synchronize(void) {
   /// leave it as is.
@@ -102,17 +102,17 @@ static inline void __sync_synchronize(void) {
 #define cb_sync_synchronize() __sync_synchronize()
 #endif  // ifndef __COMPILE_POWERPC__
 
-#define CB_BAUDRATE_TABLE \
+#define NB_BAUDRATE_TABLE \
   { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
 
-#define CB_STRING(s) #s
+#define NB_STRING(s) #s
 
-#define CB_BOOT_MAG_0 'C'
-#define CB_BOOT_MAG_1 'B'
+#define NB_BOOT_MAG_0 'C'
+#define NB_BOOT_MAG_1 'B'
 
-#define CB_BOOT_VER 0x101
+#define NB_BOOT_VER 0x101
 
-#define CB_BOOT_CALL(struct, offset)                                       \
+#define NB_BOOT_CALL(struct, offset)                                       \
   volatile cb_proc_t proc_##offset = (volatile cb_proc_t)(struct->offset); \
   proc_##offset();
 
diff --git a/lib/fd.h b/lib/fd.h
index 23a107d..1949c48 100644
--- a/lib/fd.h
+++ b/lib/fd.h
@@ -10,7 +10,7 @@
 
 struct _cb_file_descriptor;
 
-/// @brief CoreBoot file/device descriptor.
+/// @brief NeBoot file/device descriptor.
 /// @version 1
 typedef struct _cb_file_descriptor {
   int32_t f_kind;
diff --git a/lib/mp-bit.h b/lib/mp-bit.h
index 869c7c3..924fcdf 100644
--- a/lib/mp-bit.h
+++ b/lib/mp-bit.h
@@ -7,7 +7,7 @@
 #ifndef __BITMANIP_H__
 #define __BITMANIP_H__
 
-/// Name: CoreBoot Bits API.
+/// Name: NeBoot Bits API.
 /// Purpose: Bit manip helpers.
 
 #define cb_set_bit(X, O) X = (1 << O) | X
diff --git a/lib/pci-tree.h b/lib/pci-tree.h
index 2c4ca1f..a68fd4c 100644
--- a/lib/pci-tree.h
+++ b/lib/pci-tree.h
@@ -16,16 +16,16 @@
 #define PCI_INVALID_DATA_U16 ((uint16_t) ~0)
 #define PCI_INVALID_DATA_U32 ((uint32_t) ~0)
 
-#define CB_BASE_ADDRESS (0x20008000) /* PCI base mapped in virtual memory. */
-#define CB_PCI_TREE_BASE (0x802000)  /* The PCI tree base address. */
+#define NB_BASE_ADDRESS (0x20008000) /* PCI base mapped in virtual memory. */
+#define NB_PCI_TREE_BASE (0x802000)  /* The PCI tree base address. */
 
 /* version 1.0 */
-#define CB_PCI_VERSION (0x0100)
+#define NB_PCI_VERSION (0x0100)
 
-#define CB_PCI_DEV_MAGIC (0xfeedd00d)
-#define CB_PCI_INT_SZ sizeof(cb_pci_num_t)
+#define NB_PCI_DEV_MAGIC (0xfeedd00d)
+#define NB_PCI_INT_SZ sizeof(cb_pci_num_t)
 
-#define CB_PCI_NAME_LEN (255U)
+#define NB_PCI_NAME_LEN (255U)
 
 #define PCI_CONFIG_SPACE (4096U)
 
@@ -53,7 +53,7 @@ struct hw_cb_pci_tree {
   cb_pci_num_t d_first_node;
   cb_pci_num_t d_next_sibling;
 
-  cb_pci_char_t d_name[CB_PCI_NAME_LEN];
+  cb_pci_char_t d_name[NB_PCI_NAME_LEN];
 };
 
 /// @brief Init PCI tree.
diff --git a/lib/ppc64/processor.h b/lib/ppc64/processor.h
index bbeb0c9..3e6e04d 100644
--- a/lib/ppc64/processor.h
+++ b/lib/ppc64/processor.h
@@ -1023,29 +1023,29 @@ struct pt_regs {
 /*
  * 405EX/EXr CHIP_21 Errata
  */
-#ifdef CONFIG_CB_4xx_CHIP_21_405EX_SECURITY
-#define CONFIG_CB_4xx_CHIP_21_ERRATA
+#ifdef CONFIG_NB_4xx_CHIP_21_405EX_SECURITY
+#define CONFIG_NB_4xx_CHIP_21_ERRATA
 #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX1_RC
 #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX1_RD
 #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x0
 #endif
 
-#ifdef CONFIG_CB_4xx_CHIP_21_405EX_NO_SECURITY
-#define CONFIG_CB_4xx_CHIP_21_ERRATA
+#ifdef CONFIG_NB_4xx_CHIP_21_405EX_NO_SECURITY
+#define CONFIG_NB_4xx_CHIP_21_ERRATA
 #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX2_RC
 #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX2_RD
 #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x1
 #endif
 
-#ifdef CONFIG_CB_4xx_CHIP_21_405EXr_SECURITY
-#define CONFIG_CB_4xx_CHIP_21_ERRATA
+#ifdef CONFIG_NB_4xx_CHIP_21_405EXr_SECURITY
+#define CONFIG_NB_4xx_CHIP_21_ERRATA
 #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR1_RC
 #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR1_RD
 #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x2
 #endif
 
-#ifdef CONFIG_CB_4xx_CHIP_21_405EXr_NO_SECURITY
-#define CONFIG_CB_4xx_CHIP_21_ERRATA
+#ifdef CONFIG_NB_4xx_CHIP_21_405EXr_NO_SECURITY
+#define CONFIG_NB_4xx_CHIP_21_ERRATA
 #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR2_RC
 #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR2_RD
 #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x3
diff --git a/lib/xcoff.h b/lib/xcoff.h
index abfa35a..689c570 100644
--- a/lib/xcoff.h
+++ b/lib/xcoff.h
@@ -3,7 +3,7 @@
   Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
 
   File: xcoff.h
-  Purpose: XCOFF for CoreBoot.
+  Purpose: XCOFF for NeBoot.
 
   Revision History:
 
diff --git a/libfdt/README b/libfdt/README
index a96e4e3..583cbdc 100644
--- a/libfdt/README
+++ b/libfdt/README
@@ -1,4 +1,4 @@
 Flat Device Tree
 ================
 
-A new implementation of fdt compatible with CoreBoot.
\ No newline at end of file
+A new implementation of fdt compatible with NeBoot.
\ No newline at end of file
diff --git a/libfdt/libfdt_env.h b/libfdt/libfdt_env.h
index 6c5616c..b443449 100644
--- a/libfdt/libfdt_env.h
+++ b/libfdt/libfdt_env.h
@@ -4,8 +4,8 @@
 
 ------------------------------------------- */
 
-#ifndef __CB_FDT_H__
-#define __CB_FDT_H__
+#ifndef __NB_FDT_H__
+#define __NB_FDT_H__
 
 #include <lib/boot.h>
 
@@ -60,4 +60,4 @@ static inline fdt64_t cpu_to_fdt64(uint64_t x) {
 #undef CPU_TO_FDT16
 #undef EXTRACT_BYTE
 
-#endif  //!__CB_FDT_H__
+#endif  //!__NB_FDT_H__
diff --git a/src/amd64/amd64-boot.asm b/src/amd64/amd64-boot.asm
index bcd6058..d578aa9 100644
--- a/src/amd64/amd64-boot.asm
+++ b/src/amd64/amd64-boot.asm
@@ -1,4 +1,4 @@
-;; AMD64 CoreBoot Master Boot Program.
+;; AMD64 NeBoot Master Boot Program.
 ;; Written by Amlal EL Mahrouss
 
 %define ENTRYPOINT 0x00FF
diff --git a/src/amd64/amd64-test.asm b/src/amd64/amd64-test.asm
index 2a8bef8..b89e522 100644
--- a/src/amd64/amd64-test.asm
+++ b/src/amd64/amd64-test.asm
@@ -1,4 +1,4 @@
-;; AMD64 CoreBoot Sample program.
+;; AMD64 NeBoot Sample program.
 ;; Written by Amlal EL Mahrouss
 
 [bits 16]
diff --git a/src/arm64/arm64-uart.c b/src/arm64/arm64-uart.c
index 5a7f21d..4723204 100644
--- a/src/arm64/arm64-uart.c
+++ b/src/arm64/arm64-uart.c
@@ -13,7 +13,7 @@
 
 /* this file handles the UART */
 
-static uint32_t* cb_uart_ptr = (uint32_t*) CB_UART_BASE;
+static uint32_t* cb_uart_ptr = (uint32_t*) NB_UART_BASE;
 
 /// @brief Retrieve character from cb_uart_ptr
 utf_char_t cb_get_char(void) {
diff --git a/src/arm64/ci.make b/src/arm64/ci.make
index 07f1746..2b0fed2 100644
--- a/src/arm64/ci.make
+++ b/src/arm64/ci.make
@@ -1,7 +1,7 @@
  #
  #	========================================================
  #
- #	CoreBoot
+ #	NeBoot
  # 	Date Added: 08/11/2023
  # 	Copyright 2024, Amlal El Mahrouss, all rights reserved.
  #
@@ -34,7 +34,7 @@ WAIT=sleep 1
 
 .PHONY: all
 all: firmware-link
-	@echo "[CoreBoot] build done."
+	@echo "[NeBoot] build done."
 
 .PHONY: firmware-link
 firmware-link: firmware-compile
diff --git a/src/arm64/makefile b/src/arm64/makefile
index 8d05e8b..a85553b 100644
--- a/src/arm64/makefile
+++ b/src/arm64/makefile
@@ -1,7 +1,7 @@
  #
  #	========================================================
  #
- #	CoreBoot
+ #	NeBoot
  # 	Date Added: 08/11/2023
  # 	Copyright 2024, Amlal El Mahrouss, all rights reserved.
  #
@@ -34,7 +34,7 @@ WAIT=sleep 1
 
 .PHONY: all
 all: firmware-link
-	@echo "[CoreBoot] build done."
+	@echo "[NeBoot] build done."
 
 .PHONY: firmware-link
 firmware-link: firmware-compile
diff --git a/src/hal/coreboot-ahci-driver.c b/src/hal/neboot-ahci-driver.c
index 26a8907..b9badd2 100644
--- a/src/hal/coreboot-ahci-driver.c
+++ b/src/hal/neboot-ahci-driver.c
@@ -5,7 +5,7 @@
 ------------------------------------------- */
 
 /**
- * @file coreboot-ahci-driver.cc
+ * @file neboot-ahci-driver.cc
  * @author Amlal EL Mahrouss (amlal@nekernel.org)
  * @brief SATA Disk support, via AHCI.
  * @version 0.2
@@ -18,7 +18,7 @@
 #include <lib/boot.h>
 #include <lib/pci-tree.h>
 
-#define CB_AHCI_DRIVER_NAME ("@sata")
+#define NB_AHCI_DRIVER_NAME ("@sata")
 
 /// BUGS: 0
 /// @brief AHCI support for PowerPC.
diff --git a/src/hal/coreboot-flash-driver.c b/src/hal/neboot-flash-driver.c
index d1b0907..d1b0907 100644
--- a/src/hal/coreboot-flash-driver.c
+++ b/src/hal/neboot-flash-driver.c
diff --git a/src/coreboot-bootnet.c b/src/neboot-bootnet.c
index a547b35..a547b35 100644
--- a/src/coreboot-bootnet.c
+++ b/src/neboot-bootnet.c
diff --git a/src/coreboot-cpu-api.c b/src/neboot-cpu-api.c
index 2491f15..2491f15 100644
--- a/src/coreboot-cpu-api.c
+++ b/src/neboot-cpu-api.c
diff --git a/src/coreboot-cxx-abi.cc b/src/neboot-cxx-abi.cc
index 88b2a6a..88b2a6a 100644
--- a/src/coreboot-cxx-abi.cc
+++ b/src/neboot-cxx-abi.cc
diff --git a/src/coreboot-partition-map-parse.c b/src/neboot-partition-map-parse.c
index 7d8f80f..7d8f80f 100644
--- a/src/coreboot-partition-map-parse.c
+++ b/src/neboot-partition-map-parse.c
diff --git a/src/coreboot-partition-map.c b/src/neboot-partition-map.c
index f5d937b..c13907c 100644
--- a/src/coreboot-partition-map.c
+++ b/src/neboot-partition-map.c
@@ -9,18 +9,18 @@
 
 // include this for documentation.
 
-#define CB_FILESYSTEM_COUNT 4
-#define CB_FILESYSTEM_LIST \
+#define NB_FILESYSTEM_COUNT 4
+#define NB_FILESYSTEM_LIST \
   { "NeFS", "HeFS", "FAT32", "ext4" }
 
-/// @brief check if filesystem is supported by CoreBoot.
+/// @brief check if filesystem is supported by NeBoot.
 /// @param fs the filesystem magic, as provided by EPM.
 boolean cb_filesystem_exists(caddr_t fs, size_t len) {
   if (fs == nil || *fs == 0) return no;
 
-  char* fs_list[] = CB_FILESYSTEM_LIST;
+  char* fs_list[] = NB_FILESYSTEM_LIST;
 
-  for (size_t fs_index = 0; fs_index < CB_FILESYSTEM_COUNT; fs_index++) {
+  for (size_t fs_index = 0; fs_index < NB_FILESYSTEM_COUNT; fs_index++) {
     if (strncmp(fs_list[fs_index], fs, strlen(fs_list[fs_index])) == 0) {
       return yes;
     }
diff --git a/src/coreboot-pci-tree.c b/src/neboot-pci-tree.c
index ce168fd..a506323 100644
--- a/src/coreboot-pci-tree.c
+++ b/src/neboot-pci-tree.c
@@ -5,7 +5,7 @@
 ------------------------------------------- */
 
 /**
- * @file coreboot-pci-tree.c
+ * @file neboot-pci-tree.c
  * @author Amlal EL Mahrouss (amlal@nekernel.org)
  * @brief PCI tree implementation.
  * @version 0.1
@@ -21,7 +21,7 @@
 /// BUGS: 0
 
 /// Standard Root table (Mahrouss Table)
-#define CB_PCI_ROOT_NAME "/pci-tree/@/"
+#define NB_PCI_ROOT_NAME "/pci-tree/@/"
 
 static struct hw_cb_pci_tree* cb_base_tree   = nil;
 static struct hw_cb_pci_tree* cb_latest_tree = nil;
@@ -31,25 +31,25 @@ static struct hw_cb_pci_tree* cb_last_tree   = nil;
 /// \return if it already exists -> false
 /// Otherwise true.
 boolean cb_pci_init_tree(void) {
-  cb_base_tree = (struct hw_cb_pci_tree*) (CB_PCI_TREE_BASE);
+  cb_base_tree = (struct hw_cb_pci_tree*) (NB_PCI_TREE_BASE);
 
   // huh? anyway let's ignore it then.
-  if (cb_base_tree->d_magic != CB_PCI_DEV_MAGIC) {
-    cb_base_tree->d_magic = CB_PCI_DEV_MAGIC;
+  if (cb_base_tree->d_magic != NB_PCI_DEV_MAGIC) {
+    cb_base_tree->d_magic = NB_PCI_DEV_MAGIC;
 
-    memncpy(cb_base_tree->d_name, CB_PCI_ROOT_NAME, strlen(CB_PCI_ROOT_NAME));
+    memncpy(cb_base_tree->d_name, NB_PCI_ROOT_NAME, strlen(NB_PCI_ROOT_NAME));
 
     cb_base_tree->d_next_sibling = 0;
     cb_base_tree->d_off_props    = 0;
     cb_base_tree->d_sz_struct    = 0;
     cb_base_tree->d_sz_props     = 0;
     cb_base_tree->d_off_struct   = 0;
-    cb_base_tree->d_version      = CB_PCI_VERSION;
+    cb_base_tree->d_version      = NB_PCI_VERSION;
 
     cb_base_tree->d_next_sibling = (cb_pci_num_t) (cb_base_tree + sizeof(struct hw_cb_pci_tree));
     cb_base_tree->d_first_node   = (cb_pci_num_t) cb_base_tree;
 
-    cb_put_string(">> Append root device: " CB_PCI_ROOT_NAME "\r\n");
+    cb_put_string(">> Append root device: " NB_PCI_ROOT_NAME "\r\n");
   }
 
   cb_latest_tree = cb_base_tree;
@@ -66,13 +66,13 @@ boolean cb_pci_append_tree(const caddr_t name, cb_pci_num_t struct_ptr, cb_pci_n
 
   struct hw_cb_pci_tree* cb_pci_tree = (struct hw_cb_pci_tree*) (cb_latest_tree);
 
-  while (cb_pci_tree->d_magic == CB_PCI_DEV_MAGIC) {
+  while (cb_pci_tree->d_magic == NB_PCI_DEV_MAGIC) {
     if (strcmp(cb_pci_tree->d_name, name) == 0) return no;
 
     cb_pci_tree = (struct hw_cb_pci_tree*) (cb_pci_tree + sizeof(struct hw_cb_pci_tree));
   }
 
-  cb_pci_tree->d_magic = CB_PCI_DEV_MAGIC;
+  cb_pci_tree->d_magic = NB_PCI_DEV_MAGIC;
 
   memncpy(cb_pci_tree->d_name, name, strlen(name));
 
@@ -80,7 +80,7 @@ boolean cb_pci_append_tree(const caddr_t name, cb_pci_num_t struct_ptr, cb_pci_n
   cb_pci_tree->d_sz_struct  = struct_sz;
   cb_pci_tree->d_off_props  = 0;
   cb_pci_tree->d_sz_props   = 0;
-  cb_pci_tree->d_version    = CB_PCI_VERSION;
+  cb_pci_tree->d_version    = NB_PCI_VERSION;
 
   cb_pci_tree->d_next_sibling = (cb_pci_num_t) (cb_pci_tree + sizeof(struct hw_cb_pci_tree));
   cb_pci_tree->d_first_node   = (cb_pci_num_t) cb_latest_tree;
diff --git a/src/coreboot-print-name.c b/src/neboot-print-name.c
index 6adb099..90fe104 100644
--- a/src/coreboot-print-name.c
+++ b/src/neboot-print-name.c
@@ -10,18 +10,18 @@
 /// @param
 void cb_print_name(void) {
 #ifdef __COMPILE_POWERPC__
-  cb_put_string(">> CoreBoot for POWERPC.\r\n");
+  cb_put_string(">> NeBoot for POWERPC.\r\n");
 #endif  // __COMPILE_POWERPC__
 
 #ifdef __COMPILE_ARM64__
-  cb_put_string(">> CoreBoot for ARM64.\r\n");
+  cb_put_string(">> NeBoot for ARM64.\r\n");
 #endif  // __COMPILE_POWERPC__
 
 #ifdef __COMPILE_AMD64__
-  cb_put_string(">> CoreBoot for AMD64.\r\n");
+  cb_put_string(">> NeBoot for AMD64.\r\n");
 #endif  // __COMPILE_POWERPC__
 
 #ifdef __COMPILE_RISCV__
-  cb_put_string(">> CoreBoot for RISC-V.\r\n");
+  cb_put_string(">> NeBoot for RISC-V.\r\n");
 #endif  // __COMPILE_POWERPC__
 }
diff --git a/src/coreboot-start.c b/src/neboot-start.c
index 38aa760..8384791 100644
--- a/src/coreboot-start.c
+++ b/src/neboot-start.c
@@ -45,7 +45,7 @@ void cb_start_exec(void) {
 
   // let the hart 0 init our stuff.
   if (hart == 0) {
-    cb_put_string("CB> Welcome to CoreBoot, (c) Amlal EL Mahrouss. Built the ");
+    cb_put_string("CB> Welcome to NeBoot, (c) Amlal EL Mahrouss. Built the ");
     cb_put_string(__DATE__);
     cb_put_string("\r\r\n");
 
@@ -72,7 +72,7 @@ void cb_start_exec(void) {
 
   /// @brief Boots here if LX header matches what we except.
 
-  volatile struct cb_boot_header* boot_hdr = (volatile struct cb_boot_header*) (CB_FLASH_BASE_ADDR);
+  volatile struct cb_boot_header* boot_hdr = (volatile struct cb_boot_header*) (NB_FLASH_BASE_ADDR);
 
   /**
     boot if:
@@ -80,14 +80,14 @@ void cb_start_exec(void) {
       - version matches.
   */
 
-  if (boot_hdr->h_mag[0] == CB_BOOT_MAG_0 && boot_hdr->h_mag[1] == CB_BOOT_MAG_1) {
+  if (boot_hdr->h_mag[0] == NB_BOOT_MAG_0 && boot_hdr->h_mag[1] == NB_BOOT_MAG_1) {
     uint32_t rev = boot_hdr->h_revision;
 
 #ifdef __aarch64__
     rev = __builtin_bswap32(rev);
 #endif
 
-    if (rev != CB_BOOT_VER) {
+    if (rev != NB_BOOT_VER) {
       if (hart == 0) {
         cb_put_string("CB> Can't Boot the StageTwo, LX invalid signature. (CB0003)\r\n");
       }
@@ -113,7 +113,7 @@ void cb_start_exec(void) {
   } else {
     cb_put_string("CB> Trying EPM partition...\r\n");
 
-    part_block_t* blk = cb_parse_partition_block_at((voidptr_t) CB_BOOT_ADDR, EPM_PART_BLK_SZ, 0);
+    part_block_t* blk = cb_parse_partition_block_at((voidptr_t) NB_BOOT_ADDR, EPM_PART_BLK_SZ, 0);
 
     if (blk) {
       cb_pci_append_tree("@stage2-epm", (cb_pci_num_t) blk, sizeof(part_block_t) * blk->num_blocks);
diff --git a/src/coreboot-string.c b/src/neboot-string.c
index 355e734..0c249a4 100644
--- a/src/coreboot-string.c
+++ b/src/neboot-string.c
@@ -5,7 +5,7 @@
 ------------------------------------------- */
 
 /**
- * @file coreboot-string.c
+ * @file neboot-string.c
  * @author Amlal EL Mahrouss (amlal@nekernel.org)
  * @brief string library.
  * @version 0.1
diff --git a/src/ppc64/makefile b/src/ppc64/makefile
index 8adb03f..d046098 100644
--- a/src/ppc64/makefile
+++ b/src/ppc64/makefile
@@ -1,7 +1,7 @@
  #

  #	========================================================

  #

- #	CoreBoot

+ #	NeBoot

  # 	Date Added: 08/11/2023

  # 	Copyright 2024, Amlal El Mahrouss, all rights reserved.

  #

@@ -35,7 +35,7 @@ IMG_CMD=qemu-img create -f qcow2 epm.img 256M
 

 .PHONY: all

 all: firmware-link

-	@echo "[CoreBoot] build done."

+	@echo "[NeBoot] build done."

 

 .PHONY: firmware-link

 firmware-link: firmware-compile

diff --git a/src/ppc64/ppc64-boot.S b/src/ppc64/ppc64-boot.S
index 28d1865..de366fc 100644
--- a/src/ppc64/ppc64-boot.S
+++ b/src/ppc64/ppc64-boot.S
@@ -29,11 +29,11 @@ cb_reset_vector:
 .global cb_start_context

 .global cb_boot_processor_ready

 

-.equ CB_BOOT_ADDR, 0x1030000

+.equ NB_BOOT_ADDR, 0x1030000

 

 cb_start_rom:

-	lis 3, CB_BOOT_ADDR@h

-	addi 3, 3, CB_BOOT_ADDR@l

+	lis 3, NB_BOOT_ADDR@h

+	addi 3, 3, NB_BOOT_ADDR@l

 

 	blr

 

diff --git a/src/ppc64/ppc64-hal.c b/src/ppc64/ppc64-hal.c
index 74d18c4..993e5be 100644
--- a/src/ppc64/ppc64-hal.c
+++ b/src/ppc64/ppc64-hal.c
@@ -41,7 +41,7 @@ void cb_set_tlb(uint8_t tlb, uint32_t epn, uint64_t rpn, uint8_t perms, uint8_t
 void cb_init_hw(void) {

   /// amlal:

   /// map VGA framebuffer

-  cb_set_tlb(0, CB_FRAMEBUFFER_ADDR, /* v_addr, 0x0000A0000 */

+  cb_set_tlb(0, NB_FRAMEBUFFER_ADDR, /* v_addr, 0x0000A0000 */

              0x0000A000,             /* p_addr. 0x0000A0000  */

              MAS3_SW | MAS3_SR,      /* perm  type=TLB_MAP_IO */

              MAS2_I | MAS2_G,        /* wimge type=TLB_MAP_IO */

@@ -52,7 +52,7 @@ void cb_init_hw(void) {
 

   // map ccsrbar and uart.

   // at start we execute from esel = 0, so chose something else..

-  cb_set_tlb(1, CB_UART_BASE,   /* v_addr   0xe0000000 see  qemu-ppce500.h */

+  cb_set_tlb(1, NB_UART_BASE,   /* v_addr   0xe0000000 see  qemu-ppce500.h */

              0xfe0000000,       /* p_addr. 0xfe0000000  */

              MAS3_SW | MAS3_SR, /* perm  type=TLB_MAP_IO */

              MAS2_I | MAS2_G,   /* wimge type=TLB_MAP_IO */

@@ -63,7 +63,7 @@ void cb_init_hw(void) {
 

   /// amlal:

   /// map pci base for kernel

-  cb_set_tlb(0, CB_BASE_ADDRESS, /* v_addr, 0xFE008000 */

+  cb_set_tlb(0, NB_BASE_ADDRESS, /* v_addr, 0xFE008000 */

              0xFE0008000,        /* p_addr. 0xfe0000000  */

              MAS3_SW | MAS3_SR,  /* perm  type=TLB_MAP_IO */

              MAS2_I | MAS2_G,    /* wimge type=TLB_MAP_IO */

@@ -74,10 +74,10 @@ void cb_init_hw(void) {
 

   cb_pci_init_tree();

 

-  cb_pci_append_tree("@fb", CB_FRAMEBUFFER_ADDR, 0x0);

+  cb_pci_append_tree("@fb", NB_FRAMEBUFFER_ADDR, 0x0);

   cb_pci_append_tree("@mbci", 0x0, 0x0);  // did not found a MBCI base for now...

-  cb_pci_append_tree("@serial", CB_UART_BASE, 0);

-  cb_pci_append_tree("@pci", CB_BASE_ADDRESS, 0x0);

+  cb_pci_append_tree("@serial", NB_UART_BASE, 0);

+  cb_pci_append_tree("@pci", NB_BASE_ADDRESS, 0x0);

 

   cb_flush_tlb();

 }

diff --git a/src/ppc64/ppc64-uart.c b/src/ppc64/ppc64-uart.c
index b3b5717..9830342 100644
--- a/src/ppc64/ppc64-uart.c
+++ b/src/ppc64/ppc64-uart.c
@@ -9,10 +9,10 @@
 

 /// BUGS: 0

 

-#define CB_NS16550_COM1 (CB_UART_BASE + 0x4500)

-#define CB_NS16550_COM2 (CB_UART_BASE + 0x4600)

+#define NB_NS16550_COM1 (NB_UART_BASE + 0x4500)

+#define NB_NS16550_COM2 (NB_UART_BASE + 0x4600)

 

-volatile ascii_char_t* const UART0DR = (ascii_char_t*) CB_NS16550_COM1;

+volatile ascii_char_t* const UART0DR = (ascii_char_t*) NB_NS16550_COM1;

 

 /* this file handles the UART */

 

diff --git a/src/rv64/ci.make b/src/rv64/ci.make
index 757d6c1..c9936dd 100644
--- a/src/rv64/ci.make
+++ b/src/rv64/ci.make
@@ -1,7 +1,7 @@
  #
  #	========================================================
  #
- #	CoreBoot
+ #	NeBoot
  # 	Date Added: 08/11/2023
  # 	Copyright 2024, Amlal El Mahrouss, all rights reserved.
  #
@@ -24,7 +24,7 @@ EMU=qemu-system-riscv64 -m 4G -smp 2 -machine virt -bios $(FIRMWARE) -d int -dev
 
 .PHONY: all
 all: firmware-link
-	@echo "[CoreBoot] Done."
+	@echo "[NeBoot] Done."
 
 # link (make firmware)
 .PHONY: firmware-link
diff --git a/src/rv64/makefile b/src/rv64/makefile
index 757d6c1..c9936dd 100644
--- a/src/rv64/makefile
+++ b/src/rv64/makefile
@@ -1,7 +1,7 @@
  #
  #	========================================================
  #
- #	CoreBoot
+ #	NeBoot
  # 	Date Added: 08/11/2023
  # 	Copyright 2024, Amlal El Mahrouss, all rights reserved.
  #
@@ -24,7 +24,7 @@ EMU=qemu-system-riscv64 -m 4G -smp 2 -machine virt -bios $(FIRMWARE) -d int -dev
 
 .PHONY: all
 all: firmware-link
-	@echo "[CoreBoot] Done."
+	@echo "[NeBoot] Done."
 
 # link (make firmware)
 .PHONY: firmware-link
diff --git a/src/rv64/rv64-api.s b/src/rv64/rv64-api.s
index 8fe29e1..b4a0749 100644
--- a/src/rv64/rv64-api.s
+++ b/src/rv64/rv64-api.s
@@ -1,6 +1,6 @@
 # ====================================
 #
-#   Amlal EL Mahrouss CoreBoot
+#   Amlal EL Mahrouss NeBoot
 #   (c) Amlal EL Mahrouss all rights reserved.
 #
 #   Purpose: Assembler API for RISC-V
diff --git a/src/rv64/rv64-boot.s b/src/rv64/rv64-boot.s
index fb95d55..a9afd02 100644
--- a/src/rv64/rv64-boot.s
+++ b/src/rv64/rv64-boot.s
@@ -1,7 +1,7 @@
 /*
  *	========================================================
  *
- *	CoreBoot
+ *	NeBoot
  * 	Copyright 2024, Amlal EL Mahrouss, all rights reserved.
  *
  *  	Purpose: Startup code for RISC-V.
@@ -81,10 +81,10 @@ cb_start_context:
 	add ra, zero, a1
 	mret
 
-.equ CB_BOOT_ADDR, 0x80020000
+.equ NB_BOOT_ADDR, 0x80020000
 
 cb_start_rom:
-	li x5, CB_BOOT_ADDR
+	li x5, NB_BOOT_ADDR
 	mv ra, zero
 	add ra, zero, t0
 	mret
diff --git a/src/rv64/rv64-uart.c b/src/rv64/rv64-uart.c
index 3f604fe..22b0793 100644
--- a/src/rv64/rv64-uart.c
+++ b/src/rv64/rv64-uart.c
@@ -11,10 +11,10 @@
 
 /* this file handles the UART */
 
-static uint8_t* cb_uart_ptr = (uint8_t*) CB_UART_BASE;
+static uint8_t* cb_uart_ptr = (uint8_t*) NB_UART_BASE;
 
 utf_char_t cb_get_char(void) {
-  uintptr_t ptr = CB_UART_BASE;
+  uintptr_t ptr = NB_UART_BASE;
 
   while (!(*(((volatile uint8_t*) ptr) + 0x05) & 0x01))
     ;