xcoff: import xcoff changes from nekernel to fw.

meta: alongside other important changes (such as indexing boot offset as
volatile)

Signed-off-by: Amlal El Mahrouss <amlal@nekernel.org>

12 files changed, 58 insertions, 57 deletions

diff --git a/src/arm64/arm64-30pin.c b/src/arm64/arm64-30pin.c
index 427b078..f347f0d 100644
--- a/src/arm64/arm64-30pin.c
+++ b/src/arm64/arm64-30pin.c
@@ -7,4 +7,4 @@
 #include <lib/partition-map.h>
 #include <lib/30pin.h>
 
-extern size_t cb_send_read_30pin(voidptr_t blob, size_t* size, size_t* start_lba);
+extern size_t cb_read_30pin(voidptr_t blob, size_t* size, size_t* start_lba);
diff --git a/src/arm64/arm64-err.c b/src/arm64/arm64-err.c
index 045a58e..052b302 100644
--- a/src/arm64/arm64-err.c
+++ b/src/arm64/arm64-err.c
@@ -12,7 +12,7 @@
 /// @param reason why?
 void cb_panic(const char* reason)
 {
-	cb_put_string("Error: ");
+	cb_put_string("panic: ");
 	cb_put_string(reason);
 	cb_put_char('\n');
 
diff --git a/src/arm64/arm64-uart.c b/src/arm64/arm64-uart.c
index 1fdb550..362fc24 100644
--- a/src/arm64/arm64-uart.c
+++ b/src/arm64/arm64-uart.c
@@ -13,7 +13,7 @@
 
 /* this file handles the UART */
 
-static uint32_t* cb_uart_ptr = (uint32_t*)SYS_UART_BASE;
+static uint32_t* cb_uart_ptr = (uint32_t*)CB_UART_BASE;
 
 // we need that one, to avoid sending mutliple chars to UART.
 static boolean cb_locked_put_char = no;
diff --git a/src/coreboot-ahci-driver.c b/src/coreboot-ahci-driver.c
index 1f368d4..2ef2098 100644
--- a/src/coreboot-ahci-driver.c
+++ b/src/coreboot-ahci-driver.c
@@ -18,7 +18,7 @@
 #include <lib/pci-tree.h>
 #include <lib/boot.h>
 
-#define SYS_AHCI_DRIVER_NAME ("@sata")
+#define CB_AHCI_DRIVER_NAME ("@sata")
 
 /// BUGS: 0
 /// @brief AHCI support for PowerPC.
@@ -49,7 +49,7 @@ typedef struct cb_hba_port
 
 /// @brief Check if port is active.
 /// @param port host bus address port.
-/// @return
+/// @return whether sact is active or not.
 static boolean cb_hba_port_active(volatile cb_hba_port_t* port)
 {
 	if (!port)
@@ -58,9 +58,9 @@ static boolean cb_hba_port_active(volatile cb_hba_port_t* port)
 	return port->sact;
 }
 
-/// @brief Start HBA command.
+/// @brief Start HBA command processor.
 /// @param port host bus address port.
-/// @return
+/// @return whether it was successful or not.
 static boolean cb_hba_start_cmd(volatile cb_hba_port_t* port)
 {
 	if (!port)
@@ -82,9 +82,9 @@ static boolean cb_hba_start_cmd(volatile cb_hba_port_t* port)
 	return true;
 }
 
-/// @brief Stop HBA command.
+/// @brief Stop HBA command from processing.
 /// @param port host bus address port.
-/// @return
+/// @return whether it was successful or not.
 static boolean cb_hba_stop_cmd(volatile cb_hba_port_t* port)
 {
 	if (!port)
@@ -93,7 +93,7 @@ static boolean cb_hba_stop_cmd(volatile cb_hba_port_t* port)
 	port->cmd &= ~0x0001;
 	port->cmd &= ~0x0010;
 
-	while (1)
+	while (yes)
 	{
 		if ((port->cmd & 0x8000))
 			continue;
diff --git a/src/coreboot-partition-map.c b/src/coreboot-partition-map.c
index 40c3ff0..69bcddd 100644
--- a/src/coreboot-partition-map.c
+++ b/src/coreboot-partition-map.c
@@ -9,8 +9,8 @@
 
 // include this for documentation.
 
-#define MP_FILESYSTEM_COUNT 4
-#define MP_FILESYSTEM_LIST              \
+#define CB_FILESYSTEM_COUNT 4
+#define CB_FILESYSTEM_LIST              \
 	{                                   \
 		"NeFS", "HeFS", "FAT32", "ext4" \
 	}
@@ -23,9 +23,9 @@ boolean cb_filesystem_exists(caddr_t fs, size_t len)
 		*fs == 0)
 		return no;
 
-	char* fs_list[] = MP_FILESYSTEM_LIST;
+	char* fs_list[] = CB_FILESYSTEM_LIST;
 
-	for (size_t fs_index = 0; fs_index < MP_FILESYSTEM_COUNT; fs_index++)
+	for (size_t fs_index = 0; fs_index < CB_FILESYSTEM_COUNT; fs_index++)
 	{
 		if (strncmp(fs_list[fs_index], fs, strlen(fs_list[fs_index])) == 0)
 		{
diff --git a/src/coreboot-pci-tree.c b/src/coreboot-pci-tree.c
index 65e4b77..b39c024 100644
--- a/src/coreboot-pci-tree.c
+++ b/src/coreboot-pci-tree.c
@@ -21,7 +21,7 @@
 /// BUGS: 0
 
 /// Standard Root table (Mahrouss Table)
-#define SYS_PCI_ROOT_NAME "/pci-tree/@/"
+#define CB_PCI_ROOT_NAME "/pci-tree/@/"
 
 static struct hw_cb_pci_tree* cb_base_tree	 = nil;
 static struct hw_cb_pci_tree* cb_latest_tree = nil;
@@ -32,27 +32,27 @@ static struct hw_cb_pci_tree* cb_last_tree	 = nil;
 /// Otherwise true.
 boolean cb_pci_init_tree(void)
 {
-	cb_base_tree = (struct hw_cb_pci_tree*)(SYS_PCI_TREE_BASE);
+	cb_base_tree = (struct hw_cb_pci_tree*)(CB_PCI_TREE_BASE);
 
 	// huh? anyway let's ignore it then.
-	if (cb_base_tree->d_magic != SYS_PCI_DEV_MAGIC)
+	if (cb_base_tree->d_magic != CB_PCI_DEV_MAGIC)
 	{
-		cb_base_tree->d_magic = SYS_PCI_DEV_MAGIC;
+		cb_base_tree->d_magic = CB_PCI_DEV_MAGIC;
 
-		memncpy(cb_base_tree->d_name, SYS_PCI_ROOT_NAME, strlen(SYS_PCI_ROOT_NAME));
+		memncpy(cb_base_tree->d_name, CB_PCI_ROOT_NAME, strlen(CB_PCI_ROOT_NAME));
 
 		cb_base_tree->d_next_sibling = 0;
 		cb_base_tree->d_off_props	 = 0;
 		cb_base_tree->d_sz_struct	 = 0;
 		cb_base_tree->d_sz_props	 = 0;
 		cb_base_tree->d_off_struct	 = 0;
-		cb_base_tree->d_version		 = SYS_PCI_VERSION;
+		cb_base_tree->d_version		 = CB_PCI_VERSION;
 
 		cb_base_tree->d_next_sibling =
 			(cb_pci_num_t)(cb_base_tree + sizeof(struct hw_cb_pci_tree));
 		cb_base_tree->d_first_node = (cb_pci_num_t)cb_base_tree;
 
-		cb_put_string(">> Append root device: " SYS_PCI_ROOT_NAME "\r\n");
+		cb_put_string(">> Append root device: " CB_PCI_ROOT_NAME "\r\n");
 	}
 
 	cb_latest_tree = cb_base_tree;
@@ -71,7 +71,7 @@ boolean cb_pci_append_tree(const caddr_t name, cb_pci_num_t struct_ptr, cb_pci_n
 
 	struct hw_cb_pci_tree* cb_pci_tree = (struct hw_cb_pci_tree*)(cb_latest_tree);
 
-	while (cb_pci_tree->d_magic == SYS_PCI_DEV_MAGIC)
+	while (cb_pci_tree->d_magic == CB_PCI_DEV_MAGIC)
 	{
 		if (strcmp(cb_pci_tree->d_name, name) == 0)
 			return no;
@@ -81,7 +81,7 @@ boolean cb_pci_append_tree(const caddr_t name, cb_pci_num_t struct_ptr, cb_pci_n
 									 sizeof(struct hw_cb_pci_tree));
 	}
 
-	cb_pci_tree->d_magic = SYS_PCI_DEV_MAGIC;
+	cb_pci_tree->d_magic = CB_PCI_DEV_MAGIC;
 
 	memncpy(cb_pci_tree->d_name, name, strlen(name));
 
@@ -89,7 +89,7 @@ boolean cb_pci_append_tree(const caddr_t name, cb_pci_num_t struct_ptr, cb_pci_n
 	cb_pci_tree->d_sz_struct  = struct_sz;
 	cb_pci_tree->d_off_props  = 0;
 	cb_pci_tree->d_sz_props	  = 0;
-	cb_pci_tree->d_version	  = SYS_PCI_VERSION;
+	cb_pci_tree->d_version	  = CB_PCI_VERSION;
 
 	cb_pci_tree->d_next_sibling =
 		(cb_pci_num_t)(cb_pci_tree + sizeof(struct hw_cb_pci_tree));
diff --git a/src/coreboot-start.c b/src/coreboot-start.c
index a4e1efc..21ee5b0 100644
--- a/src/coreboot-start.c
+++ b/src/coreboot-start.c
@@ -74,7 +74,7 @@ void cb_start_exec(void)
 	/// @brief Boots here if LX header matches what we except.
 
 	volatile struct cb_boot_header* boot_hdr =
-		(volatile struct cb_boot_header*)(SYS_FLASH_BASE_ADDR);
+		(volatile struct cb_boot_header*)(CB_FLASH_BASE_ADDR);
 
 	/**
 	  boot if:
@@ -82,10 +82,10 @@ void cb_start_exec(void)
 		  - version matches.
   */
 
-	if (boot_hdr->h_mag[0] == SYS_BOOT_MAG_0 &&
-		boot_hdr->h_mag[1] == SYS_BOOT_MAG_1)
+	if (boot_hdr->h_mag[0] == CB_BOOT_MAG_0 &&
+		boot_hdr->h_mag[1] == CB_BOOT_MAG_1)
 	{
-		if (boot_hdr->h_revision != SYS_BOOT_VER)
+		if (boot_hdr->h_revision != CB_BOOT_VER)
 		{
 			if (hart == 1)
 			{
diff --git a/src/ppc64/ppc64-boot.S b/src/ppc64/ppc64-boot.S
index 17d6fa5..28d1865 100644
--- a/src/ppc64/ppc64-boot.S
+++ b/src/ppc64/ppc64-boot.S
@@ -29,11 +29,11 @@ cb_reset_vector:
 .global cb_start_context

 .global cb_boot_processor_ready

 

-.equ SYS_BOOT_ADDR, 0x1030000

+.equ CB_BOOT_ADDR, 0x1030000

 

 cb_start_rom:

-	lis 3, SYS_BOOT_ADDR@h

-	addi 3, 3, SYS_BOOT_ADDR@l

+	lis 3, CB_BOOT_ADDR@h

+	addi 3, 3, CB_BOOT_ADDR@l

 

 	blr

 

diff --git a/src/ppc64/ppc64-hal.c b/src/ppc64/ppc64-hal.c
index 53e16d2..f47f0b3 100644
--- a/src/ppc64/ppc64-hal.c
+++ b/src/ppc64/ppc64-hal.c
@@ -36,6 +36,7 @@ void cb_set_tlb(uint8_t	 tlb,
 		// this mmu-version does not allow odd tsize values

 		return;

 	}

+

 	uint32_t mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);

 	uint32_t mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);

 	uint32_t mas2 = FSL_BOOKE_MAS2(epn, wimge);

@@ -52,18 +53,18 @@ void cb_init_hw(void)
 

 	/// amlal:

 	/// map VGA framebuffer

-	cb_set_tlb(0, SYS_FRAMEBUFFER_ADDR, /* v_addr, 0x0000A0000 */

-			   0x0000A000,				/* p_addr. 0x0000A0000  */

-			   MAS3_SW | MAS3_SR,		/* perm  type=TLB_MAP_IO */

-			   MAS2_I | MAS2_G,			/* wimge type=TLB_MAP_IO */

-			   0,						/* ts i.e AS=0 */

-			   1,						/* esel (a.k.a tlb_index*/

-			   BOOKE_PAGESZ_64K,		/* tsize  ie 2^10kB ie 1MB */

+	cb_set_tlb(0, CB_FRAMEBUFFER_ADDR, /* v_addr, 0x0000A0000 */

+			   0x0000A000,			   /* p_addr. 0x0000A0000  */

+			   MAS3_SW | MAS3_SR,	   /* perm  type=TLB_MAP_IO */

+			   MAS2_I | MAS2_G,		   /* wimge type=TLB_MAP_IO */

+			   0,					   /* ts i.e AS=0 */

+			   1,					   /* esel (a.k.a tlb_index*/

+			   BOOKE_PAGESZ_64K,	   /* tsize  ie 2^10kB ie 1MB */

 			   1);

 

 	// map ccsrbar and uart.

 	// at start we execute from esel = 0, so chose something else..

-	cb_set_tlb(1, SYS_UART_BASE,  /* v_addr   0xe0000000 see  qemu-ppce500.h */

+	cb_set_tlb(1, CB_UART_BASE,	  /* v_addr   0xe0000000 see  qemu-ppce500.h */

 			   0xfe0000000,		  /* p_addr. 0xfe0000000  */

 			   MAS3_SW | MAS3_SR, /* perm  type=TLB_MAP_IO */

 			   MAS2_I | MAS2_G,	  /* wimge type=TLB_MAP_IO */

@@ -74,21 +75,21 @@ void cb_init_hw(void)
 

 	/// amlal:

 	/// map pci base for kernel

-	cb_set_tlb(0, SYS_BASE_ADDRESS, /* v_addr, 0xFE008000 */

-			   0xFE0008000,			/* p_addr. 0xfe0000000  */

-			   MAS3_SW | MAS3_SR,	/* perm  type=TLB_MAP_IO */

-			   MAS2_I | MAS2_G,		/* wimge type=TLB_MAP_IO */

-			   0,					/* ts i.e AS=0 */

-			   3,					/* esel (a.k.a tlb_index*/

-			   BOOKE_PAGESZ_1M,		/* tsize  ie 2^10kB ie 1MB */

+	cb_set_tlb(0, CB_BASE_ADDRESS, /* v_addr, 0xFE008000 */

+			   0xFE0008000,		   /* p_addr. 0xfe0000000  */

+			   MAS3_SW | MAS3_SR,  /* perm  type=TLB_MAP_IO */

+			   MAS2_I | MAS2_G,	   /* wimge type=TLB_MAP_IO */

+			   0,				   /* ts i.e AS=0 */

+			   3,				   /* esel (a.k.a tlb_index*/

+			   BOOKE_PAGESZ_1M,	   /* tsize  ie 2^10kB ie 1MB */

 			   1);

 

 	cb_pci_init_tree();

 

-	cb_pci_append_tree("@fb", SYS_FRAMEBUFFER_ADDR, 0x0);

-	cb_pci_append_tree("@mbci", 0x0, 0x0);

-	cb_pci_append_tree("@serial", SYS_UART_BASE, 0);

-	cb_pci_append_tree("@pci", SYS_BASE_ADDRESS, 0x0);

+	cb_pci_append_tree("@fb", CB_FRAMEBUFFER_ADDR, 0x0);

+	cb_pci_append_tree("@mbci", 0x0, 0x0); // did not found a MBCI base for now...

+	cb_pci_append_tree("@serial", CB_UART_BASE, 0);

+	cb_pci_append_tree("@pci", CB_BASE_ADDRESS, 0x0);

 

 	cb_flush_tlb();

 }

diff --git a/src/ppc64/ppc64-uart.c b/src/ppc64/ppc64-uart.c
index 0a01857..c908eae 100644
--- a/src/ppc64/ppc64-uart.c
+++ b/src/ppc64/ppc64-uart.c
@@ -9,10 +9,10 @@
 

 /// BUGS: 0

 

-#define SYS_NS16550_COM1 (SYS_UART_BASE + 0x4500)

-#define SYS_NS16550_COM2 (SYS_UART_BASE + 0x4600)

+#define CB_NS16550_COM1 (CB_UART_BASE + 0x4500)

+#define CB_NS16550_COM2 (CB_UART_BASE + 0x4600)

 

-volatile ascii_char_t* const UART0DR = (ascii_char_t*)SYS_NS16550_COM1;

+volatile ascii_char_t* const UART0DR = (ascii_char_t*)CB_NS16550_COM1;

 

 /* this file handles the UART */

 

diff --git a/src/rv64/rv64-boot.s b/src/rv64/rv64-boot.s
index ae975da..fb95d55 100644
--- a/src/rv64/rv64-boot.s
+++ b/src/rv64/rv64-boot.s
@@ -81,10 +81,10 @@ cb_start_context:
 	add ra, zero, a1
 	mret
 
-.equ SYS_BOOT_ADDR, 0x80020000
+.equ CB_BOOT_ADDR, 0x80020000
 
 cb_start_rom:
-	li x5, SYS_BOOT_ADDR
+	li x5, CB_BOOT_ADDR
 	mv ra, zero
 	add ra, zero, t0
 	mret
diff --git a/src/rv64/rv64-uart.c b/src/rv64/rv64-uart.c
index 4c96178..73964ef 100644
--- a/src/rv64/rv64-uart.c
+++ b/src/rv64/rv64-uart.c
@@ -11,11 +11,11 @@
 
 /* this file handles the UART */
 
-static uint8_t* cb_uart_ptr = (uint8_t*)SYS_UART_BASE;
+static uint8_t* cb_uart_ptr = (uint8_t*)CB_UART_BASE;
 
 utf_char_t cb_get_char(void)
 {
-	uintptr_t ptr = SYS_UART_BASE;
+	uintptr_t ptr = CB_UART_BASE;
 	while (!(*(((volatile uint8_t*)ptr) + 0x05) & 0x01))
 		;