From f204ff88659e058d70213fc7224a2c95c6a48c9d Mon Sep 17 00:00:00 2001 From: Amlal El Mahrouss Date: Fri, 28 Mar 2025 09:09:27 +0100 Subject: coreboot: rename from NeKernel firmware, refactor symbols to `cb_`, update docs This patch completes a major renaming and cleanup of the firmware codebase: - Rename project from "NeKernel Firmware" to "CoreBoot" in README and comments. - Replace all `mp_`-prefixed symbols with `cb_` to reflect the new naming scheme. - Remove obsolete SPECIFICATION.TXT and replace with SPECIFICATION_FIRMWARE.md. - Update memory-mapped I/O helpers, TLB init, and platform-specific code to match `cb_*` naming. - Refactor low-level UART, panic, PCI-tree, partition map, and context setup to use unified `cb_` API. - Adjust linker scripts and boot vectors for ARM64, PPC64, and RV64 targets accordingly. - Add Doxygen documentation note to README. This change is part of an ongoing effort to rebrand and unify the firmware interface, improve naming clarity, and better align with platform-specific toolchains. Signed-off-by: Amlal El Mahrouss --- src/coreboot-start.c | 62 ++++++++++++++++++++++++++-------------------------- 1 file changed, 31 insertions(+), 31 deletions(-) (limited to 'src/coreboot-start.c') diff --git a/src/coreboot-start.c b/src/coreboot-start.c index 46453ca..69335ec 100644 --- a/src/coreboot-start.c +++ b/src/coreboot-start.c @@ -22,59 +22,59 @@ ///////////////////////////////////////////////////////////////////////////////////////// -extern void mp_append_scsi_tree(void); -extern void mp_append_video_tree(void); +extern void cb_append_scsi_tree(void); +extern void cb_append_video_tree(void); -extern void mp_start_context(uintptr_t); -extern void mp_start_rom(void); +extern void cb_start_context(uintptr_t); +extern void cb_start_rom(void); -extern int mp_boot_processor_ready; +extern int cb_boot_processor_ready; /// @brief hardware thread counter. -uint64_t __mp_hart_counter = 0UL; +uint64_t __cb_hart_counter = 0UL; /// @brief Start executing the firmware. /// @param -void mp_start_exec(void) +void cb_start_exec(void) { - ++__mp_hart_counter; + ++__cb_hart_counter; - uintptr_t hart = __mp_hart_counter; + uintptr_t hart = __cb_hart_counter; - mp_sync_synchronize(); + cb_sync_synchronize(); // let the hart 0 init our stuff. if (hart == 1) { - mp_put_string("CB> Welcome to CoreBoot, (c) Amlal EL Mahrouss. Built the "); - mp_put_string(__DATE__); - mp_put_string("\r\r\n"); + cb_put_string("CB> Welcome to CoreBoot, (c) Amlal EL Mahrouss. Built the "); + cb_put_string(__DATE__); + cb_put_string("\r\r\n"); #ifdef __COMPILE_POWERPC__ - mp_put_string("CB> CPU: PowerPC 64-bit Based SoC.\r\r\n"); + cb_put_string("CB> CPU: PowerPC 64-bit Based SoC.\r\r\n"); #endif // __COMPILE_POWERPC__ #ifdef __COMPILE_AMD64__ - mp_put_string("CB> CPU: x64 Based SoC.\r\r\n"); + cb_put_string("CB> CPU: x64 Based SoC.\r\r\n"); #endif // __COMPILE_AMD64__ #ifdef __COMPILE_ARM64__ - mp_put_string("CB> CPU: AArch64 Based SoC.\r\r\n"); + cb_put_string("CB> CPU: AArch64 Based SoC.\r\r\n"); #endif // __COMPILE_ARM64__ #ifdef __COMPILE_ARM32__ - mp_put_string("CB> CPU: AArch32 Based SoC.\r\r\n"); + cb_put_string("CB> CPU: AArch32 Based SoC.\r\r\n"); #endif // __COMPILE_ARM64__ #ifdef __COMPILE_RISCV__ - mp_put_string("CB> CPU: RV64 Based SoC.\r\r\n"); + cb_put_string("CB> CPU: RV64 Based SoC.\r\r\n"); #endif // __COMPILE_RISCV__ } /// @brief Boots here if LX header matches what we except. - volatile struct mp_boot_header* boot_hdr = - (volatile struct mp_boot_header*)(SYS_FLASH_BASE_ADDR); + volatile struct cb_boot_header* boot_hdr = + (volatile struct cb_boot_header*)(SYS_FLASH_BASE_ADDR); /** boot if: @@ -89,35 +89,35 @@ void mp_start_exec(void) { if (hart == 1) { - mp_put_string("CB> Can't Boot the Stage2, invalid signature. (CB0003)\r\n"); + cb_put_string("CB> Can't Boot the Stage2, invalid signature. (CB0003)\r\n"); } } else { if (hart == 1) { - mp_put_string("CB> Executing Stage2: "); - mp_put_string((const char*)boot_hdr->h_name); - mp_put_char('\r'); - mp_put_char('\n'); + cb_put_string("CB> Executing Stage2: "); + cb_put_string((const char*)boot_hdr->h_name); + cb_put_char('\r'); + cb_put_char('\n'); // printf("CB> address: %x\n", boot_hdr->h_start_address); } if (boot_hdr->h_start_address != 0) { - mp_boot_processor_ready = 1; - mp_start_context(boot_hdr->h_start_address); + cb_boot_processor_ready = 1; + cb_start_context(boot_hdr->h_start_address); } - mp_put_string("CB> Stage2 has returned? (CB0002)\r\n"); + cb_put_string("CB> Stage2 has returned? (CB0002)\r\n"); } } else { if (hart == 1) { - mp_put_string("CB> Can't boot to Stage2. (CB0001)\r\n"); + cb_put_string("CB> Can't boot to Stage2. (CB0001)\r\n"); } } @@ -127,9 +127,9 @@ void mp_start_exec(void) { while (1) { - if (__mp_hart_counter == 0) + if (__cb_hart_counter == 0) { - mp_restart_machine(); + cb_restart_machine(); } } } -- cgit v1.2.3