From 1c8414d3348c55fcf132839a04fdedec5efaacbe Mon Sep 17 00:00:00 2001
From: Amlal <amlal@nekernel.org>
Date: Fri, 25 Apr 2025 13:28:08 +0200
Subject: dev: refactor codebase.

Signed-off-by: Amlal <amlal@nekernel.org>
---
 src/arm64/arm64-30pin.c            |   4 +-
 src/arm64/arm64-err.c              |  18 ++--
 src/arm64/arm64-uart.c             |  43 ++++----
 src/coreboot-bootnet.c             |   2 +-
 src/coreboot-cpu-api.c             |  16 ++-
 src/coreboot-cxx-abi.cc            | 112 +++++++++-----------
 src/coreboot-partition-map-parse.c |  74 +++++--------
 src/coreboot-partition-map.c       |  37 +++----
 src/coreboot-pci-tree.c            |  96 ++++++++---------
 src/coreboot-print-name.c          |  21 ++--
 src/coreboot-start.c               | 208 +++++++++++++++++--------------------
 src/coreboot-string.c              | 196 +++++++++++++++-------------------
 src/hal/coreboot-ahci-driver.c     | 102 ++++++++----------
 src/hal/coreboot-flash.c           |   2 +-
 src/ppc64/ppc64-err.c              |  18 ++--
 src/ppc64/ppc64-hal.c              | 147 ++++++++++++--------------
 src/ppc64/ppc64-uart.c             |  33 +++---
 src/rv64/rv64-err.c                |  18 ++--
 src/rv64/rv64-uart.c               |  52 ++++------
 19 files changed, 523 insertions(+), 676 deletions(-)

(limited to 'src')

diff --git a/src/arm64/arm64-30pin.c b/src/arm64/arm64-30pin.c
index f347f0d..eb89c67 100644
--- a/src/arm64/arm64-30pin.c
+++ b/src/arm64/arm64-30pin.c
@@ -1,10 +1,10 @@
 /* -------------------------------------------
 
-	Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
 
 ------------------------------------------- */
 
-#include <lib/partition-map.h>
 #include <lib/30pin.h>
+#include <lib/partition-map.h>
 
 extern size_t cb_read_30pin(voidptr_t blob, size_t* size, size_t* start_lba);
diff --git a/src/arm64/arm64-err.c b/src/arm64/arm64-err.c
index 052b302..c734ada 100644
--- a/src/arm64/arm64-err.c
+++ b/src/arm64/arm64-err.c
@@ -1,6 +1,6 @@
 /* -------------------------------------------
 
-	Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
 
 ------------------------------------------- */
 
@@ -10,14 +10,12 @@
 
 /// @brief Goes into a panic state.
 /// @param reason why?
-void cb_panic(const char* reason)
-{
-	cb_put_string("panic: ");
-	cb_put_string(reason);
-	cb_put_char('\n');
+void cb_panic(const char* reason) {
+  cb_put_string("panic: ");
+  cb_put_string(reason);
+  cb_put_char('\n');
 
-	while (yes)
-	{
-		asm volatile("hlt #0");
-	}
+  while (yes) {
+    asm volatile("hlt #0");
+  }
 }
diff --git a/src/arm64/arm64-uart.c b/src/arm64/arm64-uart.c
index 7455626..d587346 100644
--- a/src/arm64/arm64-uart.c
+++ b/src/arm64/arm64-uart.c
@@ -1,6 +1,6 @@
 /* -------------------------------------------
 
-	Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
 
 ------------------------------------------- */
 
@@ -9,47 +9,40 @@
 
 /// BUGS: 0
 
-#define ARM64_MMIO_REG(addr) (*(volatile uint32_t*)(cb_uart_ptr + addr))
+#define ARM64_MMIO_REG(addr) (*(volatile uint32_t*) (cb_uart_ptr + addr))
 
 /* this file handles the UART */
 
-static uint32_t* cb_uart_ptr = (uint32_t*)CB_UART_BASE;
+static uint32_t* cb_uart_ptr = (uint32_t*) CB_UART_BASE;
 
 // we need that one, to avoid sending mutliple chars to UART.
 static boolean cb_locked_put_char = no;
 
 /// @brief Retrieve character from cb_uart_ptr
-utf_char_t cb_get_char(void)
-{
-	while ((ARM64_MMIO_REG(0x018) & (1 << 4)))
-	{
-	}
+utf_char_t cb_get_char(void) {
+  while ((ARM64_MMIO_REG(0x018) & (1 << 4))) {
+  }
 
-	return (utf_char_t)ARM64_MMIO_REG(0x0) & 0xFF;
+  return (utf_char_t) ARM64_MMIO_REG(0x0) & 0xFF;
 }
 
-void cb_put_char(utf_char_t ch)
-{
-	while ((ARM64_MMIO_REG(0x018) & (1 << 5)))
-	{
-	}
+void cb_put_char(utf_char_t ch) {
+  while ((ARM64_MMIO_REG(0x018) & (1 << 5))) {
+  }
 
-	ARM64_MMIO_REG(0x0) = ch;
+  ARM64_MMIO_REG(0x0) = ch;
 }
 
 /// @brief UART put string
 /// @param text the input text.
-size_t cb_put_string(const char* text)
-{
-	if (text == nil)
-		return 0;
+size_t cb_put_string(const char* text) {
+  if (text == nil) return 0;
 
-	size_t i = 0;
+  size_t i = 0;
 
-	for (; i < strlen(text); i++)
-	{
-		cb_put_char(text[i]);
-	}
+  for (; i < strlen(text); i++) {
+    cb_put_char(text[i]);
+  }
 
-	return i;
+  return i;
 }
diff --git a/src/coreboot-bootnet.c b/src/coreboot-bootnet.c
index 687edd9..a547b35 100644
--- a/src/coreboot-bootnet.c
+++ b/src/coreboot-bootnet.c
@@ -1,6 +1,6 @@
 /* -------------------------------------------
 
-	Copyright (C) 2025, Amlal EL Mahrouss, all rights reserved.
+  Copyright (C) 2025, Amlal EL Mahrouss, all rights reserved.
 
 ------------------------------------------- */
 
diff --git a/src/coreboot-cpu-api.c b/src/coreboot-cpu-api.c
index c118192..2491f15 100644
--- a/src/coreboot-cpu-api.c
+++ b/src/coreboot-cpu-api.c
@@ -1,6 +1,6 @@
 /* -------------------------------------------
 
-	Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
 
 ------------------------------------------- */
 
@@ -8,15 +8,13 @@
 
 /// @brief Restarts the computer.
 /// @param none.
-void cb_restart_machine(void)
-{
+void cb_restart_machine(void) {
 #ifdef __COMPILE_RISCV__
-	volatile uint32_t* brd_pwr = (volatile uint32_t*)0x100000;
-	*brd_pwr				   = 0x7777; // send reboot signal from DMA.
+  volatile uint32_t* brd_pwr = (volatile uint32_t*) 0x100000;
+  *brd_pwr                   = 0x7777;  // send reboot signal from DMA.
 
-	while (1)
-	{
-		asm volatile("wfi");
-	}
+  while (1) {
+    asm volatile("wfi");
+  }
 #endif
 }
diff --git a/src/coreboot-cxx-abi.cc b/src/coreboot-cxx-abi.cc
index 858ba5e..70d9e62 100644
--- a/src/coreboot-cxx-abi.cc
+++ b/src/coreboot-cxx-abi.cc
@@ -1,6 +1,6 @@
 /* -------------------------------------------
 
-	Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
 
 ------------------------------------------- */
 
@@ -9,83 +9,69 @@
 /// BUGS: 0
 
 extern "C" __SIZE_TYPE__ cb_put_string(const char* text);
-extern "C" void			 cb_panic(const char* reason);
+extern "C" void          cb_panic(const char* reason);
 
-extern "C" void __stack_chk_fail()
-{
-	cb_put_string("[stack-canary] Buffer overflow detected, halting...\n");
-	cb_panic("stack_canary_fail");
+extern "C" void __stack_chk_fail() {
+  cb_put_string("[stack-canary] Buffer overflow detected, halting...\n");
+  cb_panic("stack_canary_fail");
 }
 
 void* __dso_handle;
 
 extern "C" __SIZE_TYPE__ cb_put_string(const char* text);
-extern "C" void			 cb_panic(const char* reason);
+extern "C" void          cb_panic(const char* reason);
 
 atexit_func_entry_t __atexit_funcs[DSO_MAX_OBJECTS];
-uarch_t				__atexit_func_count;
+uarch_t             __atexit_func_count;
 
-extern "C" void __cxa_pure_virtual()
-{
-	cb_put_string("[__cxa_pure_virtual] Placeholder\n");
+extern "C" void __cxa_pure_virtual() {
+  cb_put_string("[__cxa_pure_virtual] Placeholder\n");
 }
 
-extern "C" int __cxa_atexit(void (*f)(void*), void* arg, void* dso)
-{
-	if (__atexit_func_count >= DSO_MAX_OBJECTS)
-		return -1;
+extern "C" int __cxa_atexit(void (*f)(void*), void* arg, void* dso) {
+  if (__atexit_func_count >= DSO_MAX_OBJECTS) return -1;
 
-	__atexit_funcs[__atexit_func_count].destructor_func = f;
-	__atexit_funcs[__atexit_func_count].obj_ptr			= arg;
-	__atexit_funcs[__atexit_func_count].dso_handle		= dso;
+  __atexit_funcs[__atexit_func_count].destructor_func = f;
+  __atexit_funcs[__atexit_func_count].obj_ptr         = arg;
+  __atexit_funcs[__atexit_func_count].dso_handle      = dso;
 
-	__atexit_func_count++;
+  __atexit_func_count++;
 
-	return 0;
+  return 0;
 }
 
-extern "C" void __cxa_finalize(void* f)
-{
-	uarch_t i = __atexit_func_count;
-	if (!f)
-	{
-		while (i--)
-		{
-			if (__atexit_funcs[i].destructor_func)
-			{
-				(*__atexit_funcs[i].destructor_func)(__atexit_funcs[i].obj_ptr);
-			};
-		}
-
-		return;
-	}
-
-	while (i--)
-	{
-		if (__atexit_funcs[i].destructor_func)
-		{
-			(*__atexit_funcs[i].destructor_func)(__atexit_funcs[i].obj_ptr);
-			__atexit_funcs[i].destructor_func = 0;
-		};
-	}
+extern "C" void __cxa_finalize(void* f) {
+  uarch_t i = __atexit_func_count;
+  if (!f) {
+    while (i--) {
+      if (__atexit_funcs[i].destructor_func) {
+        (*__atexit_funcs[i].destructor_func)(__atexit_funcs[i].obj_ptr);
+      };
+    }
+
+    return;
+  }
+
+  while (i--) {
+    if (__atexit_funcs[i].destructor_func) {
+      (*__atexit_funcs[i].destructor_func)(__atexit_funcs[i].obj_ptr);
+      __atexit_funcs[i].destructor_func = 0;
+    };
+  }
 }
 
-namespace cxxabiv1
-{
-	extern "C" int __cxa_guard_acquire(__guard* g)
-	{
-		(void)g;
-		return 0;
-	}
-
-	extern "C" int __cxa_guard_release(__guard* g)
-	{
-		*(char*)g = 1;
-		return 0;
-	}
-
-	extern "C" void __cxa_guard_abort(__guard* g)
-	{
-		(void)g;
-	}
-} // namespace cxxabiv1
+namespace cxxabiv1 {
+extern "C" int __cxa_guard_acquire(__guard* g) {
+  (void) g;
+  return 0;
+}
+
+extern "C" int __cxa_guard_release(__guard* g) {
+  *(char*) g = 1;
+  return 0;
+}
+
+extern "C" void __cxa_guard_abort(__guard* g) {
+  (void) g;
+}
+}  // namespace cxxabiv1
diff --git a/src/coreboot-partition-map-parse.c b/src/coreboot-partition-map-parse.c
index 85ccf1b..7d8f80f 100644
--- a/src/coreboot-partition-map-parse.c
+++ b/src/coreboot-partition-map-parse.c
@@ -1,60 +1,42 @@
 /* -------------------------------------------
 
-	Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
 
 ------------------------------------------- */
 
 #include <lib/partition-map.h>
 
-bool cb_parse_partition_block_data_at(voidptr_t blob, size_t blob_sz, size_t index, size_t* end_lba, size_t* start_lba, size_t* sector_sz)
-{
-	if (!start_lba ||
-		!end_lba ||
-		!blob ||
-		!blob_sz ||
-		!sector_sz ||
-		(sizeof(part_block_t) * index) > blob_sz)
-		return false;
-
-	part_block_t* block = (part_block_t*)(blob + (sizeof(part_block_t) * index));
-
-	if (block->version != EPM_REVISION ||
-		block->num_blocks < 1 ||
-		block->num_blocks > EPM_MAX_BLKS ||
-		strcmp(block->magic, EPM_MAGIC) > 0 ||
-		block->lba_end == 0 ||
-		block->lba_start == 0)
-	{
-		return false;
-	}
-
-	*end_lba   = block->lba_end;
-	*start_lba = block->lba_start;
-	*sector_sz = block->sector_sz;
-
-	return true;
+bool cb_parse_partition_block_data_at(voidptr_t blob, size_t blob_sz, size_t index, size_t* end_lba,
+                                      size_t* start_lba, size_t* sector_sz) {
+  if (!start_lba || !end_lba || !blob || !blob_sz || !sector_sz ||
+      (sizeof(part_block_t) * index) > blob_sz)
+    return false;
+
+  part_block_t* block = (part_block_t*) (blob + (sizeof(part_block_t) * index));
+
+  if (block->version != EPM_REVISION || block->num_blocks < 1 || block->num_blocks > EPM_MAX_BLKS ||
+      strcmp(block->magic, EPM_MAGIC) > 0 || block->lba_end == 0 || block->lba_start == 0) {
+    return false;
+  }
+
+  *end_lba   = block->lba_end;
+  *start_lba = block->lba_start;
+  *sector_sz = block->sector_sz;
+
+  return true;
 }
 
-part_block_t* cb_parse_partition_block_at(voidptr_t blob, size_t blob_sz, size_t index)
-{
-	if (!blob ||
-		!blob_sz ||
-		(sizeof(part_block_t) * index) > blob_sz)
-		return nil;
+part_block_t* cb_parse_partition_block_at(voidptr_t blob, size_t blob_sz, size_t index) {
+  if (!blob || !blob_sz || (sizeof(part_block_t) * index) > blob_sz) return nil;
 
-	part_block_t* block = (part_block_t*)(blob + (sizeof(part_block_t) * index));
+  part_block_t* block = (part_block_t*) (blob + (sizeof(part_block_t) * index));
 
-	cb_put_string(block->magic);
+  cb_put_string(block->magic);
 
-	if (block->version != EPM_REVISION ||
-		block->num_blocks < 1 ||
-		block->num_blocks > EPM_MAX_BLKS ||
-		strcmp(block->magic, EPM_MAGIC) > 0 ||
-		block->lba_end == 0 ||
-		block->lba_start == 0)
-	{
-		return nil;
-	}
+  if (block->version != EPM_REVISION || block->num_blocks < 1 || block->num_blocks > EPM_MAX_BLKS ||
+      strcmp(block->magic, EPM_MAGIC) > 0 || block->lba_end == 0 || block->lba_start == 0) {
+    return nil;
+  }
 
-	return block;
+  return block;
 }
\ No newline at end of file
diff --git a/src/coreboot-partition-map.c b/src/coreboot-partition-map.c
index 69bcddd..f5d937b 100644
--- a/src/coreboot-partition-map.c
+++ b/src/coreboot-partition-map.c
@@ -1,6 +1,6 @@
 /* -------------------------------------------
 
-	Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
 
 ------------------------------------------- */
 
@@ -10,28 +10,21 @@
 // include this for documentation.
 
 #define CB_FILESYSTEM_COUNT 4
-#define CB_FILESYSTEM_LIST              \
-	{                                   \
-		"NeFS", "HeFS", "FAT32", "ext4" \
-	}
+#define CB_FILESYSTEM_LIST \
+  { "NeFS", "HeFS", "FAT32", "ext4" }
 
 /// @brief check if filesystem is supported by CoreBoot.
 /// @param fs the filesystem magic, as provided by EPM.
-boolean cb_filesystem_exists(caddr_t fs, size_t len)
-{
-	if (fs == nil ||
-		*fs == 0)
-		return no;
-
-	char* fs_list[] = CB_FILESYSTEM_LIST;
-
-	for (size_t fs_index = 0; fs_index < CB_FILESYSTEM_COUNT; fs_index++)
-	{
-		if (strncmp(fs_list[fs_index], fs, strlen(fs_list[fs_index])) == 0)
-		{
-			return yes;
-		}
-	}
-
-	return no;
+boolean cb_filesystem_exists(caddr_t fs, size_t len) {
+  if (fs == nil || *fs == 0) return no;
+
+  char* fs_list[] = CB_FILESYSTEM_LIST;
+
+  for (size_t fs_index = 0; fs_index < CB_FILESYSTEM_COUNT; fs_index++) {
+    if (strncmp(fs_list[fs_index], fs, strlen(fs_list[fs_index])) == 0) {
+      return yes;
+    }
+  }
+
+  return no;
 }
diff --git a/src/coreboot-pci-tree.c b/src/coreboot-pci-tree.c
index b39c024..ce168fd 100644
--- a/src/coreboot-pci-tree.c
+++ b/src/coreboot-pci-tree.c
@@ -1,6 +1,6 @@
 /* -------------------------------------------
 
-	Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
 
 ------------------------------------------- */
 
@@ -23,84 +23,74 @@
 /// Standard Root table (Mahrouss Table)
 #define CB_PCI_ROOT_NAME "/pci-tree/@/"
 
-static struct hw_cb_pci_tree* cb_base_tree	 = nil;
+static struct hw_cb_pci_tree* cb_base_tree   = nil;
 static struct hw_cb_pci_tree* cb_latest_tree = nil;
-static struct hw_cb_pci_tree* cb_last_tree	 = nil;
+static struct hw_cb_pci_tree* cb_last_tree   = nil;
 
 /// \brief Init the PCI device tree structure.
 /// \return if it already exists -> false
 /// Otherwise true.
-boolean cb_pci_init_tree(void)
-{
-	cb_base_tree = (struct hw_cb_pci_tree*)(CB_PCI_TREE_BASE);
+boolean cb_pci_init_tree(void) {
+  cb_base_tree = (struct hw_cb_pci_tree*) (CB_PCI_TREE_BASE);
 
-	// huh? anyway let's ignore it then.
-	if (cb_base_tree->d_magic != CB_PCI_DEV_MAGIC)
-	{
-		cb_base_tree->d_magic = CB_PCI_DEV_MAGIC;
+  // huh? anyway let's ignore it then.
+  if (cb_base_tree->d_magic != CB_PCI_DEV_MAGIC) {
+    cb_base_tree->d_magic = CB_PCI_DEV_MAGIC;
 
-		memncpy(cb_base_tree->d_name, CB_PCI_ROOT_NAME, strlen(CB_PCI_ROOT_NAME));
+    memncpy(cb_base_tree->d_name, CB_PCI_ROOT_NAME, strlen(CB_PCI_ROOT_NAME));
 
-		cb_base_tree->d_next_sibling = 0;
-		cb_base_tree->d_off_props	 = 0;
-		cb_base_tree->d_sz_struct	 = 0;
-		cb_base_tree->d_sz_props	 = 0;
-		cb_base_tree->d_off_struct	 = 0;
-		cb_base_tree->d_version		 = CB_PCI_VERSION;
+    cb_base_tree->d_next_sibling = 0;
+    cb_base_tree->d_off_props    = 0;
+    cb_base_tree->d_sz_struct    = 0;
+    cb_base_tree->d_sz_props     = 0;
+    cb_base_tree->d_off_struct   = 0;
+    cb_base_tree->d_version      = CB_PCI_VERSION;
 
-		cb_base_tree->d_next_sibling =
-			(cb_pci_num_t)(cb_base_tree + sizeof(struct hw_cb_pci_tree));
-		cb_base_tree->d_first_node = (cb_pci_num_t)cb_base_tree;
+    cb_base_tree->d_next_sibling = (cb_pci_num_t) (cb_base_tree + sizeof(struct hw_cb_pci_tree));
+    cb_base_tree->d_first_node   = (cb_pci_num_t) cb_base_tree;
 
-		cb_put_string(">> Append root device: " CB_PCI_ROOT_NAME "\r\n");
-	}
+    cb_put_string(">> Append root device: " CB_PCI_ROOT_NAME "\r\n");
+  }
 
-	cb_latest_tree = cb_base_tree;
+  cb_latest_tree = cb_base_tree;
 
-	return yes;
+  return yes;
 }
 
 /// \brief Adds a new device to the tree.
 /// \param name the device name.
 /// \param struct_ptr the struct containing the device.
 /// \param struct_sz the structure size.
-boolean cb_pci_append_tree(const caddr_t name, cb_pci_num_t struct_ptr, cb_pci_num_t struct_sz)
-{
-	if (!name || *name == 0 || cb_latest_tree == nil)
-		return no;
+boolean cb_pci_append_tree(const caddr_t name, cb_pci_num_t struct_ptr, cb_pci_num_t struct_sz) {
+  if (!name || *name == 0 || cb_latest_tree == nil) return no;
 
-	struct hw_cb_pci_tree* cb_pci_tree = (struct hw_cb_pci_tree*)(cb_latest_tree);
+  struct hw_cb_pci_tree* cb_pci_tree = (struct hw_cb_pci_tree*) (cb_latest_tree);
 
-	while (cb_pci_tree->d_magic == CB_PCI_DEV_MAGIC)
-	{
-		if (strcmp(cb_pci_tree->d_name, name) == 0)
-			return no;
+  while (cb_pci_tree->d_magic == CB_PCI_DEV_MAGIC) {
+    if (strcmp(cb_pci_tree->d_name, name) == 0) return no;
 
-		cb_pci_tree =
-			(struct hw_cb_pci_tree*)(cb_pci_tree +
-									 sizeof(struct hw_cb_pci_tree));
-	}
+    cb_pci_tree = (struct hw_cb_pci_tree*) (cb_pci_tree + sizeof(struct hw_cb_pci_tree));
+  }
 
-	cb_pci_tree->d_magic = CB_PCI_DEV_MAGIC;
+  cb_pci_tree->d_magic = CB_PCI_DEV_MAGIC;
 
-	memncpy(cb_pci_tree->d_name, name, strlen(name));
+  memncpy(cb_pci_tree->d_name, name, strlen(name));
 
-	cb_pci_tree->d_off_struct = struct_ptr;
-	cb_pci_tree->d_sz_struct  = struct_sz;
-	cb_pci_tree->d_off_props  = 0;
-	cb_pci_tree->d_sz_props	  = 0;
-	cb_pci_tree->d_version	  = CB_PCI_VERSION;
+  cb_pci_tree->d_off_struct = struct_ptr;
+  cb_pci_tree->d_sz_struct  = struct_sz;
+  cb_pci_tree->d_off_props  = 0;
+  cb_pci_tree->d_sz_props   = 0;
+  cb_pci_tree->d_version    = CB_PCI_VERSION;
 
-	cb_pci_tree->d_next_sibling =
-		(cb_pci_num_t)(cb_pci_tree + sizeof(struct hw_cb_pci_tree));
-	cb_pci_tree->d_first_node = (cb_pci_num_t)cb_latest_tree;
+  cb_pci_tree->d_next_sibling = (cb_pci_num_t) (cb_pci_tree + sizeof(struct hw_cb_pci_tree));
+  cb_pci_tree->d_first_node   = (cb_pci_num_t) cb_latest_tree;
 
-	cb_latest_tree = cb_pci_tree;
-	cb_last_tree   = cb_pci_tree;
+  cb_latest_tree = cb_pci_tree;
+  cb_last_tree   = cb_pci_tree;
 
-	cb_put_string(">> Append device: ");
-	cb_put_string(name);
-	cb_put_string("\r\n");
+  cb_put_string(">> Append device: ");
+  cb_put_string(name);
+  cb_put_string("\r\n");
 
-	return yes;
+  return yes;
 }
diff --git a/src/coreboot-print-name.c b/src/coreboot-print-name.c
index e2ad8c4..6adb099 100644
--- a/src/coreboot-print-name.c
+++ b/src/coreboot-print-name.c
@@ -1,6 +1,6 @@
 /* -------------------------------------------
 
-	Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
 
 ------------------------------------------- */
 
@@ -8,21 +8,20 @@
 
 /// @brief Print firmware name.
 /// @param
-void cb_print_name(void)
-{
+void cb_print_name(void) {
 #ifdef __COMPILE_POWERPC__
-	cb_put_string(">> CoreBoot for POWERPC.\r\n");
-#endif // __COMPILE_POWERPC__
+  cb_put_string(">> CoreBoot for POWERPC.\r\n");
+#endif  // __COMPILE_POWERPC__
 
 #ifdef __COMPILE_ARM64__
-	cb_put_string(">> CoreBoot for ARM64.\r\n");
-#endif // __COMPILE_POWERPC__
+  cb_put_string(">> CoreBoot for ARM64.\r\n");
+#endif  // __COMPILE_POWERPC__
 
 #ifdef __COMPILE_AMD64__
-	cb_put_string(">> CoreBoot for AMD64.\r\n");
-#endif // __COMPILE_POWERPC__
+  cb_put_string(">> CoreBoot for AMD64.\r\n");
+#endif  // __COMPILE_POWERPC__
 
 #ifdef __COMPILE_RISCV__
-	cb_put_string(">> CoreBoot for RISC-V.\r\n");
-#endif // __COMPILE_POWERPC__
+  cb_put_string(">> CoreBoot for RISC-V.\r\n");
+#endif  // __COMPILE_POWERPC__
 }
diff --git a/src/coreboot-start.c b/src/coreboot-start.c
index cfcc668..da6da23 100644
--- a/src/coreboot-start.c
+++ b/src/coreboot-start.c
@@ -1,13 +1,13 @@
 /* -------------------------------------------
 
-	Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
 
 ------------------------------------------- */
 
+#include <lib/boot.h>
 #include <lib/mp-bit.h>
 #include <lib/partition-map.h>
 #include <lib/pci-tree.h>
-#include <lib/boot.h>
 
 /// BUGS: 0
 
@@ -34,135 +34,117 @@ uint64_t __cb_hart_counter = 0UL;
 
 /// @brief Start executing the firmware.
 /// @param
-void cb_start_exec(void)
-{
+void cb_start_exec(void) {
 #ifndef __COMPILE_RISCV__
-	static uint64_t __cb_hart_counter = 0UL;
+  static uint64_t __cb_hart_counter = 0UL;
 #endif
 
-	++__cb_hart_counter;
+  ++__cb_hart_counter;
 
-	uintptr_t hart = __cb_hart_counter;
+  uintptr_t hart = __cb_hart_counter;
 
-	// let the hart 0 init our stuff.
-	if (hart == 0)
-	{
-		cb_put_string("CB> Welcome to CoreBoot, (c) Amlal EL Mahrouss. Built the ");
-		cb_put_string(__DATE__);
-		cb_put_string("\r\r\n");
+  // let the hart 0 init our stuff.
+  if (hart == 0) {
+    cb_put_string("CB> Welcome to CoreBoot, (c) Amlal EL Mahrouss. Built the ");
+    cb_put_string(__DATE__);
+    cb_put_string("\r\r\n");
 
 #ifdef __COMPILE_POWERPC__
-		cb_put_string("CB> CPU: PowerPC 64-bit Based SoC.\r\r\n");
-#endif // __COMPILE_POWERPC__
+    cb_put_string("CB> CPU: PowerPC 64-bit Based SoC.\r\r\n");
+#endif  // __COMPILE_POWERPC__
 
 #ifdef __COMPILE_AMD64__
-		cb_put_string("CB> CPU: x64 Based SoC.\r\r\n");
-#endif // __COMPILE_AMD64__
+    cb_put_string("CB> CPU: x64 Based SoC.\r\r\n");
+#endif  // __COMPILE_AMD64__
 
 #ifdef __COMPILE_ARM64__
-		cb_put_string("CB> CPU: AArch64 Based SoC.\r\r\n");
-#endif // __COMPILE_ARM64__
+    cb_put_string("CB> CPU: AArch64 Based SoC.\r\r\n");
+#endif  // __COMPILE_ARM64__
 
 #ifdef __COMPILE_ARM32__
-		cb_put_string("CB> CPU: AArch32 Based SoC.\r\r\n");
-#endif // __COMPILE_ARM64__
+    cb_put_string("CB> CPU: AArch32 Based SoC.\r\r\n");
+#endif  // __COMPILE_ARM64__
 
 #ifdef __COMPILE_RISCV__
-		cb_put_string("CB> CPU: RV64 Based SoC.\r\r\n");
-#endif // __COMPILE_RISCV__
-	}
+    cb_put_string("CB> CPU: RV64 Based SoC.\r\r\n");
+#endif  // __COMPILE_RISCV__
+  }
 
-	/// @brief Boots here if LX header matches what we except.
+  /// @brief Boots here if LX header matches what we except.
 
-	volatile struct cb_boot_header* boot_hdr =
-		(volatile struct cb_boot_header*)(CB_FLASH_BASE_ADDR);
+  volatile struct cb_boot_header* boot_hdr = (volatile struct cb_boot_header*) (CB_FLASH_BASE_ADDR);
 
-	/**
-	  boot if:
-		  - ident matches.
-		  - version matches.
+  /**
+    boot if:
+      - ident matches.
+      - version matches.
   */
 
-	if (boot_hdr->h_mag[0] == CB_BOOT_MAG_0 &&
-		boot_hdr->h_mag[1] == CB_BOOT_MAG_1)
-	{
-		if (boot_hdr->h_revision != CB_BOOT_VER)
-		{
-			if (hart == 0)
-			{
-				cb_put_string("CB> Can't Boot the StageTwo, LX invalid signature. (CB0003)\r\n");
-			}
-		}
-		else
-		{
-			if (hart == 0)
-			{
-				cb_pci_append_tree("@stage2-lx", (cb_pci_num_t)boot_hdr, sizeof(struct cb_boot_header));
-
-				cb_put_string("CB> Executing StageTwo: ");
-				cb_put_string((const char*)boot_hdr->h_name);
-				cb_put_char('\r');
-				cb_put_char('\n');
-
-				// printf("CB> address: %x\n", boot_hdr->h_start_address);
-			}
-
-			if (boot_hdr->h_start_address != 0)
-			{
-				cb_boot_processor_ready = 1;
-				cb_start_context(boot_hdr->h_start_address);
-			}
-
-			cb_put_string("CB> StageTwo has returned? (CB0002)\r\n");
-		}
-	}
-	else
-	{
-		cb_put_string("CB> Trying EPM partition...\r\n");
-
-		part_block_t* blk = cb_parse_partition_block_at((voidptr_t)CB_FLASH_BASE_ADDR, EPM_PART_BLK_SZ, 0);
-
-		if (blk)
-		{
-			cb_pci_append_tree("@stage2-epm", (cb_pci_num_t)blk, sizeof(part_block_t) * blk->num_blocks);
-
-			size_t indx = 0;
-			size_t end_lba, start_lba, sector_sz;
-
-			while (indx < blk->num_blocks)
-			{
-				if (cb_parse_partition_block_data_at(blk, EPM_PART_BLK_SZ * blk->num_blocks, indx, &end_lba, &start_lba, &sector_sz) == no)
-				{
-					++indx;
-					continue;
-				}
-
-				cb_boot_processor_ready = 1;
-				cb_start_context((uintptr_t)(voidptr_t)blk + start_lba);
-
-				if (hart == 1)
-				{
-					cb_put_string("CB> Can't boot to StageTwo. (CB0001)\r\n");
-				}
-			}
-		}
-
-		if (hart == 1)
-		{
-			cb_put_string("CB> Can't boot to StageTwo via EPM, no bootable partition blocks found. (CB0001)\r\n");
-		}
-	}
-
-	/// end of TODO
-
-	if (hart > 1)
-	{
-		while (yes)
-		{
-			if (__cb_hart_counter == 0)
-			{
-				cb_restart_machine();
-			}
-		}
-	}
+  if (boot_hdr->h_mag[0] == CB_BOOT_MAG_0 && boot_hdr->h_mag[1] == CB_BOOT_MAG_1) {
+    if (boot_hdr->h_revision != CB_BOOT_VER) {
+      if (hart == 0) {
+        cb_put_string("CB> Can't Boot the StageTwo, LX invalid signature. (CB0003)\r\n");
+      }
+    } else {
+      if (hart == 0) {
+        cb_pci_append_tree("@stage2-lx", (cb_pci_num_t) boot_hdr, sizeof(struct cb_boot_header));
+
+        cb_put_string("CB> Executing StageTwo: ");
+        cb_put_string((const char*) boot_hdr->h_name);
+        cb_put_char('\r');
+        cb_put_char('\n');
+
+        // printf("CB> address: %x\n", boot_hdr->h_start_address);
+      }
+
+      if (boot_hdr->h_start_address != 0) {
+        cb_boot_processor_ready = 1;
+        cb_start_context(boot_hdr->h_start_address);
+      }
+
+      cb_put_string("CB> StageTwo has returned? (CB0002)\r\n");
+    }
+  } else {
+    cb_put_string("CB> Trying EPM partition...\r\n");
+
+    part_block_t* blk =
+        cb_parse_partition_block_at((voidptr_t) CB_FLASH_BASE_ADDR, EPM_PART_BLK_SZ, 0);
+
+    if (blk) {
+      cb_pci_append_tree("@stage2-epm", (cb_pci_num_t) blk, sizeof(part_block_t) * blk->num_blocks);
+
+      size_t indx = 0;
+      size_t end_lba, start_lba, sector_sz;
+
+      while (indx < blk->num_blocks) {
+        if (cb_parse_partition_block_data_at(blk, EPM_PART_BLK_SZ * blk->num_blocks, indx, &end_lba,
+                                             &start_lba, &sector_sz) == no) {
+          ++indx;
+          continue;
+        }
+
+        cb_boot_processor_ready = 1;
+        cb_start_context((uintptr_t) (voidptr_t) blk + start_lba);
+
+        if (hart == 1) {
+          cb_put_string("CB> Can't boot to StageTwo. (CB0001)\r\n");
+        }
+      }
+    }
+
+    if (hart == 1) {
+      cb_put_string(
+          "CB> Can't boot to StageTwo via EPM, no bootable partition blocks found. (CB0001)\r\n");
+    }
+  }
+
+  /// end of TODO
+
+  if (hart > 1) {
+    while (yes) {
+      if (__cb_hart_counter == 0) {
+        cb_restart_machine();
+      }
+    }
+  }
 }
diff --git a/src/coreboot-string.c b/src/coreboot-string.c
index 491095d..355e734 100644
--- a/src/coreboot-string.c
+++ b/src/coreboot-string.c
@@ -1,6 +1,6 @@
 /* -------------------------------------------
 
-	Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
 
 ------------------------------------------- */
 
@@ -19,167 +19,135 @@
 
 /// BUGS: 0
 
-size_t strncmp(const char* src, const char* cmp, size_t size)
-{
-	if (src == nil)
-		return 0;
+size_t strncmp(const char* src, const char* cmp, size_t size) {
+  if (src == nil) return 0;
 
-	int32_t counter = 0;
+  int32_t counter = 0;
 
-	for (size_t index = 0; index < size; ++index)
-	{
-		if (src[index] != cmp[index])
-			++counter;
-	}
+  for (size_t index = 0; index < size; ++index) {
+    if (src[index] != cmp[index]) ++counter;
+  }
 
-	return counter;
+  return counter;
 }
 
-void* memset(void* ptr, const char value, size_t len)
-{
-	if (ptr == nil)
-		return nil;
+void* memset(void* ptr, const char value, size_t len) {
+  if (ptr == nil) return nil;
 
-	char* start = ptr;
+  char* start = ptr;
 
-	while (len)
-	{
-		*start = value;
-		++start;
+  while (len) {
+    *start = value;
+    ++start;
 
-		--len;
-	}
+    --len;
+  }
 
-	return (void*)start;
+  return (void*) start;
 }
 
-void* memmove(void* dest, const void* src, size_t len)
-{
-	memncpy(dest, src, len);
-	return dest;
+void* memmove(void* dest, const void* src, size_t len) {
+  memncpy(dest, src, len);
+  return dest;
 }
 
-size_t memcpy(void* dst, const void* src)
-{
-	if (src == nil || dst == nil)
-		return 0;
+size_t memcpy(void* dst, const void* src) {
+  if (src == nil || dst == nil) return 0;
 
-	const char* src_chr = src;
-	char*		dst_chr = dst;
-	size_t		index	= 0;
-	size_t		len		= strlen(src);
+  const char* src_chr = src;
+  char*       dst_chr = dst;
+  size_t      index   = 0;
+  size_t      len     = strlen(src);
 
-	while (index < len)
-	{
-		dst_chr[index] = src_chr[index];
-		++index;
-	}
+  while (index < len) {
+    dst_chr[index] = src_chr[index];
+    ++index;
+  }
 
-	return 0;
+  return 0;
 }
 
 /* @brief unoptimized memcpy, TODO: use isa specific memcpy. */
-size_t memncpy(void* dst, const void* src, size_t len)
-{
+size_t memncpy(void* dst, const void* src, size_t len) {
 #if __OL == 3 && defined(__riscv)
-	riscv_memncpy(dst, src, len);
+  riscv_memncpy(dst, src, len);
 #else
 
-	if (src == nil || dst == nil)
-		return 0;
+  if (src == nil || dst == nil) return 0;
 
-	const char* src_chr = src;
-	char*		dst_chr = dst;
-	size_t		index	= 0;
+  const char* src_chr = src;
+  char*       dst_chr = dst;
+  size_t      index   = 0;
 
-	while (index < len)
-	{
-		dst_chr[index] = src_chr[index];
-		++index;
-	}
+  while (index < len) {
+    dst_chr[index] = src_chr[index];
+    ++index;
+  }
 
-	return 0;
+  return 0;
 #endif
 }
 
-size_t strlen(const char* str)
-{
-	if (*str == 0)
-		return 0;
+size_t strlen(const char* str) {
+  if (*str == 0) return 0;
 
-	size_t len = 0;
-	while (str[len] != '\0')
-		++len;
+  size_t len = 0;
+  while (str[len] != '\0') ++len;
 
-	return len;
+  return len;
 }
 
-size_t strnlen(const char* str, size_t len)
-{
-	size_t cnt = 0;
+size_t strnlen(const char* str, size_t len) {
+  size_t cnt = 0;
 
-	while (len > cnt)
-	{
-		++cnt;
+  while (len > cnt) {
+    ++cnt;
 
-		if (str[cnt] == '\0')
-			return (size_t)-1;
-	}
+    if (str[cnt] == '\0') return (size_t) -1;
+  }
 
-	return len;
+  return len;
 }
 
-void strreverse(char* s)
-{
-	if (s == nil)
-		return;
-	if (*s == '\0')
-		return;
+void strreverse(char* s) {
+  if (s == nil) return;
+  if (*s == '\0') return;
 
-	char *first, *last, temp;
+  char *first, *last, temp;
 
-	first = s;
-	last  = s + strlen(s) - 1;
+  first = s;
+  last  = s + strlen(s) - 1;
 
-	while (first != last)
-	{
-		temp	   = *first;
-		*(first++) = *last;
-		*(last--)  = temp;
-	}
+  while (first != last) {
+    temp       = *first;
+    *(first++) = *last;
+    *(last--)  = temp;
+  }
 }
 
-char* strchr(char* str, const char chr)
-{
-	while (*str != chr)
-	{
-		++str;
+char* strchr(char* str, const char chr) {
+  while (*str != chr) {
+    ++str;
 
-		if (*str == 0)
-			return nil;
-	}
+    if (*str == 0) return nil;
+  }
 
-	return str;
+  return str;
 }
 
 /// @brief Compare two strings.
 /// @param src source string
 /// @param cmp string to compare.
 /// @return
-size_t strcmp(caddr_t src, caddr_t cmp)
-{
-	if (src == null || *src == 0)
-		return 1;
-	if (cmp == null || *cmp == 0)
-		return 1;
-
-	int32_t counter = 0;
-
-	for (size_t index = 0; src[index] != 0; ++index)
-	{
-		if (cmp[index] != src[index])
-			++counter;
-	}
-
-	return counter;
+size_t strcmp(caddr_t src, caddr_t cmp) {
+  if (src == null || *src == 0) return 1;
+  if (cmp == null || *cmp == 0) return 1;
+
+  int32_t counter = 0;
+
+  for (size_t index = 0; src[index] != 0; ++index) {
+    if (cmp[index] != src[index]) ++counter;
+  }
+
+  return counter;
 }
diff --git a/src/hal/coreboot-ahci-driver.c b/src/hal/coreboot-ahci-driver.c
index 2ef2098..26a8907 100644
--- a/src/hal/coreboot-ahci-driver.c
+++ b/src/hal/coreboot-ahci-driver.c
@@ -1,6 +1,6 @@
 /* -------------------------------------------
 
-	Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
 
 ------------------------------------------- */
 
@@ -15,8 +15,8 @@
  *
  */
 
-#include <lib/pci-tree.h>
 #include <lib/boot.h>
+#include <lib/pci-tree.h>
 
 #define CB_AHCI_DRIVER_NAME ("@sata")
 
@@ -24,85 +24,73 @@
 /// @brief AHCI support for PowerPC.
 
 /// @brief AHCI HBA port.
-typedef struct cb_hba_port
-{
-	uint32_t clb;			// 0x00, command list base address, 1K-byte aligned
-	uint32_t clbu;			// 0x04, command list base address upper 32 bits
-	uint32_t fb;			// 0x08, FIS base address, 256-byte aligned
-	uint32_t fbu;			// 0x0C, FIS base address upper 32 bits
-	uint32_t is;			// 0x10, interrupt status
-	uint32_t ie;			// 0x14, interrupt enable
-	uint32_t cmd;			// 0x18, command and status
-	uint32_t reserved0;		// 0x1C, Reserved
-	uint32_t tfd;			// 0x20, task file data
-	uint32_t sig;			// 0x24, signature
-	uint32_t ssts;			// 0x28, SATA status (SCR0:SStatus)
-	uint32_t sctl;			// 0x2C, SATA control (SCR2:SControl)
-	uint32_t serr;			// 0x30, SATA error (SCR1:SError)
-	uint32_t sact;			// 0x34, SATA active (SCR3:SActive)
-	uint32_t ci;			// 0x38, command issue
-	uint32_t sntf;			// 0x20, SATA notification (SCR4:SNotification)
-	uint32_t fbs;			// 0x40, FIS-based switch control
-	uint32_t reserved1[11]; // 0x44 ~ 0x6F, Reserved
-	uint32_t vendor[4];		// 0x70 ~ 0x7F, vendor specific
+typedef struct cb_hba_port {
+  uint32_t clb;            // 0x00, command list base address, 1K-byte aligned
+  uint32_t clbu;           // 0x04, command list base address upper 32 bits
+  uint32_t fb;             // 0x08, FIS base address, 256-byte aligned
+  uint32_t fbu;            // 0x0C, FIS base address upper 32 bits
+  uint32_t is;             // 0x10, interrupt status
+  uint32_t ie;             // 0x14, interrupt enable
+  uint32_t cmd;            // 0x18, command and status
+  uint32_t reserved0;      // 0x1C, Reserved
+  uint32_t tfd;            // 0x20, task file data
+  uint32_t sig;            // 0x24, signature
+  uint32_t ssts;           // 0x28, SATA status (SCR0:SStatus)
+  uint32_t sctl;           // 0x2C, SATA control (SCR2:SControl)
+  uint32_t serr;           // 0x30, SATA error (SCR1:SError)
+  uint32_t sact;           // 0x34, SATA active (SCR3:SActive)
+  uint32_t ci;             // 0x38, command issue
+  uint32_t sntf;           // 0x20, SATA notification (SCR4:SNotification)
+  uint32_t fbs;            // 0x40, FIS-based switch control
+  uint32_t reserved1[11];  // 0x44 ~ 0x6F, Reserved
+  uint32_t vendor[4];      // 0x70 ~ 0x7F, vendor specific
 } cb_hba_port_t;
 
 /// @brief Check if port is active.
 /// @param port host bus address port.
 /// @return whether sact is active or not.
-static boolean cb_hba_port_active(volatile cb_hba_port_t* port)
-{
-	if (!port)
-		return false;
+static boolean cb_hba_port_active(volatile cb_hba_port_t* port) {
+  if (!port) return false;
 
-	return port->sact;
+  return port->sact;
 }
 
 /// @brief Start HBA command processor.
 /// @param port host bus address port.
 /// @return whether it was successful or not.
-static boolean cb_hba_start_cmd(volatile cb_hba_port_t* port)
-{
-	if (!port)
-		return false;
+static boolean cb_hba_start_cmd(volatile cb_hba_port_t* port) {
+  if (!port) return false;
 
-	size_t timeout = 1000000;
+  size_t timeout = 1000000;
 
-	while ((port->cmd & 0x8000))
-	{
-		if (!timeout)
-			return false;
+  while ((port->cmd & 0x8000)) {
+    if (!timeout) return false;
 
-		--timeout;
-	}
+    --timeout;
+  }
 
-	port->cmd |= 0x0001;
-	port->cmd |= 0x0010;
+  port->cmd |= 0x0001;
+  port->cmd |= 0x0010;
 
-	return true;
+  return true;
 }
 
 /// @brief Stop HBA command from processing.
 /// @param port host bus address port.
 /// @return whether it was successful or not.
-static boolean cb_hba_stop_cmd(volatile cb_hba_port_t* port)
-{
-	if (!port)
-		return false;
+static boolean cb_hba_stop_cmd(volatile cb_hba_port_t* port) {
+  if (!port) return false;
 
-	port->cmd &= ~0x0001;
-	port->cmd &= ~0x0010;
+  port->cmd &= ~0x0001;
+  port->cmd &= ~0x0010;
 
-	while (yes)
-	{
-		if ((port->cmd & 0x8000))
-			continue;
+  while (yes) {
+    if ((port->cmd & 0x8000)) continue;
 
-		if ((port->cmd & 0x4000))
-			continue;
+    if ((port->cmd & 0x4000)) continue;
 
-		break;
-	}
+    break;
+  }
 
-	return true;
+  return true;
 }
diff --git a/src/hal/coreboot-flash.c b/src/hal/coreboot-flash.c
index 1416bc3..d1b0907 100644
--- a/src/hal/coreboot-flash.c
+++ b/src/hal/coreboot-flash.c
@@ -4,7 +4,7 @@ Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
 
 ------------------------------------------- */
 
+#include <lib/boot.h>
 #include <lib/mp-bit.h>
 #include <lib/partition-map.h>
 #include <lib/pci-tree.h>
-#include <lib/boot.h>
diff --git a/src/ppc64/ppc64-err.c b/src/ppc64/ppc64-err.c
index 13d944c..1ef0089 100644
--- a/src/ppc64/ppc64-err.c
+++ b/src/ppc64/ppc64-err.c
@@ -1,6 +1,6 @@
 /* -------------------------------------------
 
-	Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
 
 ------------------------------------------- */
 
@@ -10,14 +10,12 @@
 
 /// @brief Goes into a panic state.
 /// @param reason why?
-void cb_panic(const char* reason)
-{
-	cb_put_string("Error: ");
-	cb_put_string(reason);
-	cb_put_char('\n');
+void cb_panic(const char* reason) {
+  cb_put_string("Error: ");
+  cb_put_string(reason);
+  cb_put_char('\n');
 
-	while (yes)
-	{
-		(void)0;
-	}
+  while (yes) {
+    (void) 0;
+  }
 }
diff --git a/src/ppc64/ppc64-hal.c b/src/ppc64/ppc64-hal.c
index f47f0b3..74d18c4 100644
--- a/src/ppc64/ppc64-hal.c
+++ b/src/ppc64/ppc64-hal.c
@@ -1,100 +1,87 @@
 /* -------------------------------------------
 
-	Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
 
 ------------------------------------------- */
 
 #include <lib/ppc64/mmu.h>
 #include <lib/ppc64/processor.h>
 
-#include <lib/pci-tree.h>
 #include <lib/boot.h>
+#include <lib/pci-tree.h>
 
-void cb_write_tlb(uint32_t mas0, uint32_t mas1, uint32_t mas2, uint32_t mas3, uint32_t mas7)
-{
-	mtspr(MAS0, mas0);
-	mtspr(MAS1, mas1);
-	mtspr(MAS2, mas2);
-	mtspr(MAS3, mas3);
-	mtspr(MAS7, mas7);
+void cb_write_tlb(uint32_t mas0, uint32_t mas1, uint32_t mas2, uint32_t mas3, uint32_t mas7) {
+  mtspr(MAS0, mas0);
+  mtspr(MAS1, mas1);
+  mtspr(MAS2, mas2);
+  mtspr(MAS3, mas3);
+  mtspr(MAS7, mas7);
 
-	cb_flush_tlb();
+  cb_flush_tlb();
 }
 
-void cb_set_tlb(uint8_t	 tlb,
-				uint32_t epn,
-				uint64_t rpn,
-				uint8_t	 perms,
-				uint8_t	 wimge,
-				uint8_t	 ts,
-				uint8_t	 esel,
-				uint8_t	 tsize,
-				uint8_t	 iprot)
-{
-	if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1 && (tsize & 1))
-	{
-		// this mmu-version does not allow odd tsize values
-		return;
-	}
-
-	uint32_t mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
-	uint32_t mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
-	uint32_t mas2 = FSL_BOOKE_MAS2(epn, wimge);
-	uint32_t mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
-	uint32_t mas7 = FSL_BOOKE_MAS7(rpn);
-
-	cb_write_tlb(mas0, mas1, mas2, mas3, mas7);
+void cb_set_tlb(uint8_t tlb, uint32_t epn, uint64_t rpn, uint8_t perms, uint8_t wimge, uint8_t ts,
+                uint8_t esel, uint8_t tsize, uint8_t iprot) {
+  if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1 && (tsize & 1)) {
+    // this mmu-version does not allow odd tsize values
+    return;
+  }
+
+  uint32_t mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
+  uint32_t mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
+  uint32_t mas2 = FSL_BOOKE_MAS2(epn, wimge);
+  uint32_t mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
+  uint32_t mas7 = FSL_BOOKE_MAS7(rpn);
+
+  cb_write_tlb(mas0, mas1, mas2, mas3, mas7);
 }
 
 /// @brief Init hardware before jumping to kernel.
 /// @param
-void cb_init_hw(void)
-{
-
-	/// amlal:
-	/// map VGA framebuffer
-	cb_set_tlb(0, CB_FRAMEBUFFER_ADDR, /* v_addr, 0x0000A0000 */
-			   0x0000A000,			   /* p_addr. 0x0000A0000  */
-			   MAS3_SW | MAS3_SR,	   /* perm  type=TLB_MAP_IO */
-			   MAS2_I | MAS2_G,		   /* wimge type=TLB_MAP_IO */
-			   0,					   /* ts i.e AS=0 */
-			   1,					   /* esel (a.k.a tlb_index*/
-			   BOOKE_PAGESZ_64K,	   /* tsize  ie 2^10kB ie 1MB */
-			   1);
-
-	// map ccsrbar and uart.
-	// at start we execute from esel = 0, so chose something else..
-	cb_set_tlb(1, CB_UART_BASE,	  /* v_addr   0xe0000000 see  qemu-ppce500.h */
-			   0xfe0000000,		  /* p_addr. 0xfe0000000  */
-			   MAS3_SW | MAS3_SR, /* perm  type=TLB_MAP_IO */
-			   MAS2_I | MAS2_G,	  /* wimge type=TLB_MAP_IO */
-			   0,				  /* ts i.e AS=0 */
-			   2,				  /* esel (a.k.a tlb_index*/
-			   BOOKE_PAGESZ_1M,	  /* tsize  ie 2^10kB ie 1MB */
-			   1);
-
-	/// amlal:
-	/// map pci base for kernel
-	cb_set_tlb(0, CB_BASE_ADDRESS, /* v_addr, 0xFE008000 */
-			   0xFE0008000,		   /* p_addr. 0xfe0000000  */
-			   MAS3_SW | MAS3_SR,  /* perm  type=TLB_MAP_IO */
-			   MAS2_I | MAS2_G,	   /* wimge type=TLB_MAP_IO */
-			   0,				   /* ts i.e AS=0 */
-			   3,				   /* esel (a.k.a tlb_index*/
-			   BOOKE_PAGESZ_1M,	   /* tsize  ie 2^10kB ie 1MB */
-			   1);
-
-	cb_pci_init_tree();
-
-	cb_pci_append_tree("@fb", CB_FRAMEBUFFER_ADDR, 0x0);
-	cb_pci_append_tree("@mbci", 0x0, 0x0); // did not found a MBCI base for now...
-	cb_pci_append_tree("@serial", CB_UART_BASE, 0);
-	cb_pci_append_tree("@pci", CB_BASE_ADDRESS, 0x0);
-
-	cb_flush_tlb();
+void cb_init_hw(void) {
+  /// amlal:
+  /// map VGA framebuffer
+  cb_set_tlb(0, CB_FRAMEBUFFER_ADDR, /* v_addr, 0x0000A0000 */
+             0x0000A000,             /* p_addr. 0x0000A0000  */
+             MAS3_SW | MAS3_SR,      /* perm  type=TLB_MAP_IO */
+             MAS2_I | MAS2_G,        /* wimge type=TLB_MAP_IO */
+             0,                      /* ts i.e AS=0 */
+             1,                      /* esel (a.k.a tlb_index*/
+             BOOKE_PAGESZ_64K,       /* tsize  ie 2^10kB ie 1MB */
+             1);
+
+  // map ccsrbar and uart.
+  // at start we execute from esel = 0, so chose something else..
+  cb_set_tlb(1, CB_UART_BASE,   /* v_addr   0xe0000000 see  qemu-ppce500.h */
+             0xfe0000000,       /* p_addr. 0xfe0000000  */
+             MAS3_SW | MAS3_SR, /* perm  type=TLB_MAP_IO */
+             MAS2_I | MAS2_G,   /* wimge type=TLB_MAP_IO */
+             0,                 /* ts i.e AS=0 */
+             2,                 /* esel (a.k.a tlb_index*/
+             BOOKE_PAGESZ_1M,   /* tsize  ie 2^10kB ie 1MB */
+             1);
+
+  /// amlal:
+  /// map pci base for kernel
+  cb_set_tlb(0, CB_BASE_ADDRESS, /* v_addr, 0xFE008000 */
+             0xFE0008000,        /* p_addr. 0xfe0000000  */
+             MAS3_SW | MAS3_SR,  /* perm  type=TLB_MAP_IO */
+             MAS2_I | MAS2_G,    /* wimge type=TLB_MAP_IO */
+             0,                  /* ts i.e AS=0 */
+             3,                  /* esel (a.k.a tlb_index*/
+             BOOKE_PAGESZ_1M,    /* tsize  ie 2^10kB ie 1MB */
+             1);
+
+  cb_pci_init_tree();
+
+  cb_pci_append_tree("@fb", CB_FRAMEBUFFER_ADDR, 0x0);
+  cb_pci_append_tree("@mbci", 0x0, 0x0);  // did not found a MBCI base for now...
+  cb_pci_append_tree("@serial", CB_UART_BASE, 0);
+  cb_pci_append_tree("@pci", CB_BASE_ADDRESS, 0x0);
+
+  cb_flush_tlb();
 }
 
-void cb_flush_tlb(void)
-{
-	asm volatile("isync;tlbwe;msync;isync");
+void cb_flush_tlb(void) {
+  asm volatile("isync;tlbwe;msync;isync");
 };
diff --git a/src/ppc64/ppc64-uart.c b/src/ppc64/ppc64-uart.c
index c908eae..c16657d 100644
--- a/src/ppc64/ppc64-uart.c
+++ b/src/ppc64/ppc64-uart.c
@@ -1,48 +1,43 @@
 /* -------------------------------------------
 
-	Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
 
 ------------------------------------------- */
 
-#include <lib/string.h>
 #include <lib/boot.h>
+#include <lib/string.h>
 
 /// BUGS: 0
 
 #define CB_NS16550_COM1 (CB_UART_BASE + 0x4500)
 #define CB_NS16550_COM2 (CB_UART_BASE + 0x4600)
 
-volatile ascii_char_t* const UART0DR = (ascii_char_t*)CB_NS16550_COM1;
+volatile ascii_char_t* const UART0DR = (ascii_char_t*) CB_NS16550_COM1;
 
 /* this file handles the UART */
 
 /// @brief Get character from UART.
 /// @param
 /// @return
-utf_char_t cb_get_char(void)
-{
-	while (!(*(((volatile uint8_t*)UART0DR) + 0x05) & 0x01))
-		;
-	return (utf_char_t)*UART0DR;
+utf_char_t cb_get_char(void) {
+  while (!(*(((volatile uint8_t*) UART0DR) + 0x05) & 0x01));
+  return (utf_char_t) *UART0DR;
 }
 
 /// @brief Put character into UART.
 /// @param ch
-void cb_put_char(utf_char_t ch)
-{
-	*UART0DR = (ascii_char_t)(ch);
+void cb_put_char(utf_char_t ch) {
+  *UART0DR = (ascii_char_t) (ch);
 }
 
 /// @brief Put string in UART.
 /// @param text the input text.
-size_t cb_put_string(const char* text)
-{
-	while (*text != '\0')
-	{ /* Loop until end of string */
+size_t cb_put_string(const char* text) {
+  while (*text != '\0') { /* Loop until end of string */
 
-		cb_put_char(*text); /* Transmit char */
+    cb_put_char(*text); /* Transmit char */
 
-		text++; /* Next char */
-	}
-	return 0;
+    text++; /* Next char */
+  }
+  return 0;
 }
diff --git a/src/rv64/rv64-err.c b/src/rv64/rv64-err.c
index 19d0f3c..a616d83 100644
--- a/src/rv64/rv64-err.c
+++ b/src/rv64/rv64-err.c
@@ -1,6 +1,6 @@
 /* -------------------------------------------
 
-	Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
 
 ------------------------------------------- */
 
@@ -10,14 +10,12 @@
 
 /// @brief Goes into a panic state.
 /// @param reason why?
-void cb_panic(const char* reason)
-{
-	cb_put_string("Error: ");
-	cb_put_string(reason);
-	cb_put_char('\n');
+void cb_panic(const char* reason) {
+  cb_put_string("Error: ");
+  cb_put_string(reason);
+  cb_put_char('\n');
 
-	while (yes)
-	{
-		asm volatile("wfi");
-	}
+  while (yes) {
+    asm volatile("wfi");
+  }
 }
diff --git a/src/rv64/rv64-uart.c b/src/rv64/rv64-uart.c
index 0bc6517..a859add 100644
--- a/src/rv64/rv64-uart.c
+++ b/src/rv64/rv64-uart.c
@@ -1,6 +1,6 @@
 /* -------------------------------------------
 
-	Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
 
 ------------------------------------------- */
 
@@ -11,51 +11,43 @@
 
 /* this file handles the UART */
 
-static uint8_t* cb_uart_ptr = (uint8_t*)CB_UART_BASE;
+static uint8_t* cb_uart_ptr = (uint8_t*) CB_UART_BASE;
 
-utf_char_t cb_get_char(void)
-{
-	uintptr_t ptr = CB_UART_BASE;
+utf_char_t cb_get_char(void) {
+  uintptr_t ptr = CB_UART_BASE;
 
-	while (!(*(((volatile uint8_t*)ptr) + 0x05) & 0x01))
-		;
+  while (!(*(((volatile uint8_t*) ptr) + 0x05) & 0x01));
 
-	return (utf_char_t)*cb_uart_ptr;
+  return (utf_char_t) *cb_uart_ptr;
 }
 
 // we need that one, to avoid sending mutliple chars to UART.
 static boolean cb_locked_put_char = no;
 
-void cb_put_char(utf_char_t ch)
-{
-	int32_t timeout = 0;
+void cb_put_char(utf_char_t ch) {
+  int32_t timeout = 0;
 
-	while (cb_locked_put_char)
-	{
-		++timeout;
+  while (cb_locked_put_char) {
+    ++timeout;
 
-		if (timeout > 1000000)
-			break;
-	}
+    if (timeout > 1000000) break;
+  }
 
-	cb_locked_put_char = yes;
-	*cb_uart_ptr	   = ch;
-	cb_locked_put_char = no;
+  cb_locked_put_char = yes;
+  *cb_uart_ptr       = ch;
+  cb_locked_put_char = no;
 }
 
 /// @brief UART put string
 /// @param text the input text.
-size_t cb_put_string(const char* text)
-{
-	if (text == nil)
-		return 0;
+size_t cb_put_string(const char* text) {
+  if (text == nil) return 0;
 
-	size_t i = 0;
+  size_t i = 0;
 
-	for (; i < strlen(text); i++)
-	{
-		cb_put_char(text[i]);
-	}
+  for (; i < strlen(text); i++) {
+    cb_put_char(text[i]);
+  }
 
-	return i;
+  return i;
 }
-- 
cgit v1.2.3


From d48a66377317771bb22c7b5e97661a91535be97f Mon Sep 17 00:00:00 2001
From: Amlal El Mahrouss <amlal@nekernel.org>
Date: Fri, 6 Jun 2025 06:03:27 +0200
Subject: fix: Fix unused variable `cb_locked_put_char` on ARM64's UART.

Signed-off-by: Amlal El Mahrouss <amlal@nekernel.org>
---
 src/arm64/arm64-uart.c | 3 ---
 1 file changed, 3 deletions(-)

(limited to 'src')

diff --git a/src/arm64/arm64-uart.c b/src/arm64/arm64-uart.c
index d587346..5a7f21d 100644
--- a/src/arm64/arm64-uart.c
+++ b/src/arm64/arm64-uart.c
@@ -15,9 +15,6 @@
 
 static uint32_t* cb_uart_ptr = (uint32_t*) CB_UART_BASE;
 
-// we need that one, to avoid sending mutliple chars to UART.
-static boolean cb_locked_put_char = no;
-
 /// @brief Retrieve character from cb_uart_ptr
 utf_char_t cb_get_char(void) {
   while ((ARM64_MMIO_REG(0x018) & (1 << 4))) {
-- 
cgit v1.2.3


From 19ffdc8218284937b1ac4fc8ef9a19a536b4a887 Mon Sep 17 00:00:00 2001
From: Amlal El Mahrouss <amlal@nekernel.org>
Date: Tue, 17 Jun 2025 23:56:50 +0200
Subject: fix: see below.

fix:
- match flash base address according to qemu `virt`.
- make use of correct offsets in the firmware's entrypoint.

refactor:
- rename flash.c to flash-driver.c

Signed-off-by: Amlal El Mahrouss <amlal@nekernel.org>
---
 lib/boot.h                      |  2 +-
 lib/pci-tree.h                  | 14 +++++++-------
 src/coreboot-start.c            |  2 +-
 src/hal/coreboot-flash-driver.c | 10 ++++++++++
 src/hal/coreboot-flash.c        | 10 ----------
 5 files changed, 19 insertions(+), 19 deletions(-)
 create mode 100644 src/hal/coreboot-flash-driver.c
 delete mode 100644 src/hal/coreboot-flash.c

(limited to 'src')

diff --git a/lib/boot.h b/lib/boot.h
index a792a82..cf90766 100644
--- a/lib/boot.h
+++ b/lib/boot.h
@@ -93,7 +93,7 @@ typedef ptrtype_t        size_t;
 #define CB_BOOT_ADDR 0x1030000
 #define CB_BOOT_ADDR_STR "0x1030000"
 #define CB_FRAMEBUFFER_ADDR 0x40000000L
-#define CB_FLASH_BASE_ADDR 0x08000000
+#define CB_FLASH_BASE_ADDR 0x60000000
 
 static inline void __sync_synchronize(void) {
   /// leave it as is.
diff --git a/lib/pci-tree.h b/lib/pci-tree.h
index 460b185..2c4ca1f 100644
--- a/lib/pci-tree.h
+++ b/lib/pci-tree.h
@@ -1,6 +1,6 @@
 /* -------------------------------------------
 
-  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+  Copyright (C) 2024-2025, Amlal EL Mahrouss, all rights reserved.
 
 ------------------------------------------- */
 
@@ -19,12 +19,6 @@
 #define CB_BASE_ADDRESS (0x20008000) /* PCI base mapped in virtual memory. */
 #define CB_PCI_TREE_BASE (0x802000)  /* The PCI tree base address. */
 
-#define PCI_CONFIG_SPACE (4096U)
-
-#define PCI_BUS_MAX (256U)
-#define PCI_DEV_MAX (32U)
-#define PCI_FN_MAX (8U)
-
 /* version 1.0 */
 #define CB_PCI_VERSION (0x0100)
 
@@ -33,6 +27,12 @@
 
 #define CB_PCI_NAME_LEN (255U)
 
+#define PCI_CONFIG_SPACE (4096U)
+
+#define PCI_BUS_MAX (256U)
+#define PCI_DEV_MAX (32U)
+#define PCI_FN_MAX (8U
+
 typedef char      cb_pci_char_t;
 typedef uintptr_t cb_pci_num_t;
 
diff --git a/src/coreboot-start.c b/src/coreboot-start.c
index da6da23..7a93744 100644
--- a/src/coreboot-start.c
+++ b/src/coreboot-start.c
@@ -108,7 +108,7 @@ void cb_start_exec(void) {
     cb_put_string("CB> Trying EPM partition...\r\n");
 
     part_block_t* blk =
-        cb_parse_partition_block_at((voidptr_t) CB_FLASH_BASE_ADDR, EPM_PART_BLK_SZ, 0);
+        cb_parse_partition_block_at((voidptr_t) CB_BOOT_ADDR, EPM_PART_BLK_SZ, 0);
 
     if (blk) {
       cb_pci_append_tree("@stage2-epm", (cb_pci_num_t) blk, sizeof(part_block_t) * blk->num_blocks);
diff --git a/src/hal/coreboot-flash-driver.c b/src/hal/coreboot-flash-driver.c
new file mode 100644
index 0000000..d1b0907
--- /dev/null
+++ b/src/hal/coreboot-flash-driver.c
@@ -0,0 +1,10 @@
+/* -------------------------------------------
+
+Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+
+------------------------------------------- */
+
+#include <lib/boot.h>
+#include <lib/mp-bit.h>
+#include <lib/partition-map.h>
+#include <lib/pci-tree.h>
diff --git a/src/hal/coreboot-flash.c b/src/hal/coreboot-flash.c
deleted file mode 100644
index d1b0907..0000000
--- a/src/hal/coreboot-flash.c
+++ /dev/null
@@ -1,10 +0,0 @@
-/* -------------------------------------------
-
-Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
-
-------------------------------------------- */
-
-#include <lib/boot.h>
-#include <lib/mp-bit.h>
-#include <lib/partition-map.h>
-#include <lib/pci-tree.h>
-- 
cgit v1.2.3


From a16989ecbf4b1c4b3e471e706222c922b62e49bf Mon Sep 17 00:00:00 2001
From: Amlal El Mahrouss <amlal@nekernel.org>
Date: Sun, 29 Jun 2025 18:11:56 +0200
Subject: fix: BSwap reivision on AArch64.

Signed-off-by: Amlal El Mahrouss <amlal@nekernel.org>
---
 src/coreboot-start.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/coreboot-start.c b/src/coreboot-start.c
index 7a93744..eeeaabc 100644
--- a/src/coreboot-start.c
+++ b/src/coreboot-start.c
@@ -81,7 +81,13 @@ void cb_start_exec(void) {
   */
 
   if (boot_hdr->h_mag[0] == CB_BOOT_MAG_0 && boot_hdr->h_mag[1] == CB_BOOT_MAG_1) {
-    if (boot_hdr->h_revision != CB_BOOT_VER) {
+    uint32_t rev = boot_hdr->h_revision;
+
+#ifdef __aarch64__
+    rev = __builtin_bswap32(rev);
+#endif
+
+    if (rev != CB_BOOT_VER) {
       if (hart == 0) {
         cb_put_string("CB> Can't Boot the StageTwo, LX invalid signature. (CB0003)\r\n");
       }
-- 
cgit v1.2.3


From e49b26f4f6a38139f78c7085b922ba7c01b03524 Mon Sep 17 00:00:00 2001
From: Amlal El Mahrouss <amlal@nekernel.org>
Date: Thu, 10 Jul 2025 14:05:58 +0200
Subject: feat: Extend Explicit Partition Map specs and reference header to
 allocate a new ID for SNU.

Signed-off-by: Amlal El Mahrouss <amlal@nekernel.org>
---
 docs/tex/epm.tex       |   1 +
 lib/partition-map.h    |   1 +
 lib/ppc64/mmu.h        |  12 ++---
 lib/ppc64/processor.h  | 128 ++++++++++++++++++++++++-------------------------
 src/coreboot-start.c   |   3 +-
 src/ppc64/ppc64-uart.c |   3 +-
 src/rv64/rv64-uart.c   |   3 +-
 7 files changed, 77 insertions(+), 74 deletions(-)

(limited to 'src')

diff --git a/docs/tex/epm.tex b/docs/tex/epm.tex
index f139c2c..399d016 100644
--- a/docs/tex/epm.tex
+++ b/docs/tex/epm.tex
@@ -106,6 +106,7 @@ struct __attribute__((packed)) part_block {
 \texttt{EPM\_LINUX} & \texttt{0x8f} - Linux partition \\
 \texttt{EPM\_BSD} & \texttt{0x9f} - BSD partition \\
 \texttt{EPM\_NEKERNEL\_OS} & \texttt{0x1f} - NeKernel-specific \\
+\texttt{EPM\_SNU\_OS} & \texttt{0x1f} - SNU-specific \\
 \hline
 \end{longtable}
 
diff --git a/lib/partition-map.h b/lib/partition-map.h
index 28d480a..f034335 100644
--- a/lib/partition-map.h
+++ b/lib/partition-map.h
@@ -87,6 +87,7 @@ enum {
   EPM_LINUX       = 0x8f,
   EPM_BSD         = 0x9f,
   EPM_NEKERNEL_OS = 0x1f,
+  EPM_SNU_OS      = 0x2f,
 };
 
 /// @brief check for supported filesystem.
diff --git a/lib/ppc64/mmu.h b/lib/ppc64/mmu.h
index 1953ab5..cbfbf47 100644
--- a/lib/ppc64/mmu.h
+++ b/lib/ppc64/mmu.h
@@ -402,7 +402,7 @@ extern void print_bats(void);
 #define MAS0_TLBSEL(x) (((x) << 28) & MAS0_TLBSEL_MSK)
 #define MAS0_ESEL_MSK 0x0FFF0000
 #define MAS0_ESEL(x) (((x) << 16) & MAS0_ESEL_MSK)
-#define MAS0_NV(x) ((x) & 0x00000FFF)
+#define MAS0_NV(x) ((x) &0x00000FFF)
 
 #define MAS1_VALID 0x80000000
 #define MAS1_IPROT 0x40000000
@@ -454,8 +454,8 @@ extern void print_bats(void);
 #define FSL_BOOKE_MAS1(v, iprot, tid, ts, tsize)                                   \
   ((((v) << 31) & MAS1_VALID) | (((iprot) << 30) & MAS1_IPROT) | (MAS1_TID(tid)) | \
    (((ts) << 12) & MAS1_TS) | (MAS1_TSIZE(tsize)))
-#define FSL_BOOKE_MAS2(epn, wimge) (((epn) & MAS3_RPN) | (wimge))
-#define FSL_BOOKE_MAS3(rpn, user, perms) (((rpn) & MAS3_RPN) | (user) | (perms))
+#define FSL_BOOKE_MAS2(epn, wimge) (((epn) &MAS3_RPN) | (wimge))
+#define FSL_BOOKE_MAS3(rpn, user, perms) (((rpn) &MAS3_RPN) | (user) | (perms))
 #define FSL_BOOKE_MAS7(rpn) (((uint64_t) (rpn)) >> 32)
 
 #define BOOKE_PAGESZ_1K 0
@@ -621,10 +621,10 @@ extern int                    num_tlb_entries;
 
 /* Some handy macros */
 
-#define EPN(e) ((e) & 0xfffffc00)
+#define EPN(e) ((e) &0xfffffc00)
 #define TLB0(epn, sz) ((EPN((epn)) | (sz) | TLB_VALID))
-#define TLB1(rpn, erpn) (((rpn) & 0xfffffc00) | (erpn))
-#define TLB2(a) ((a) & 0x00000fbf)
+#define TLB1(rpn, erpn) (((rpn) &0xfffffc00) | (erpn))
+#define TLB2(a) ((a) &0x00000fbf)
 
 #define tlbtab_start \
   mflr r1;           \
diff --git a/lib/ppc64/processor.h b/lib/ppc64/processor.h
index 4c40886..bbeb0c9 100644
--- a/lib/ppc64/processor.h
+++ b/lib/ppc64/processor.h
@@ -143,36 +143,36 @@ struct pt_regs {
 #define SPRN_DBCR 0x3F2   /* Debug Control Regsiter */
 #define DBCR_EDM 0x80000000
 #define DBCR_IDM 0x40000000
-#define DBCR_RST(x) (((x) & 0x3) << 28)
+#define DBCR_RST(x) (((x) &0x3) << 28)
 #define DBCR_RST_NONE 0
 #define DBCR_RST_CORE 1
 #define DBCR_RST_CHIP 2
 #define DBCR_RST_SYSTEM 3
-#define DBCR_IC 0x08000000              /* Instruction Completion Debug Evnt */
-#define DBCR_BT 0x04000000              /* Branch Taken Debug Event */
-#define DBCR_EDE 0x02000000             /* Exception Debug Event */
-#define DBCR_TDE 0x01000000             /* TRAP Debug Event */
-#define DBCR_FER 0x00F80000             /* First Events Remaining Mask */
-#define DBCR_FT 0x00040000              /* Freeze Timers on Debug Event */
-#define DBCR_IA1 0x00020000             /* Instr. Addr. Compare 1 Enable */
-#define DBCR_IA2 0x00010000             /* Instr. Addr. Compare 2 Enable */
-#define DBCR_D1R 0x00008000             /* Data Addr. Compare 1 Read Enable */
-#define DBCR_D1W 0x00004000             /* Data Addr. Compare 1 Write Enable */
-#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
+#define DBCR_IC 0x08000000             /* Instruction Completion Debug Evnt */
+#define DBCR_BT 0x04000000             /* Branch Taken Debug Event */
+#define DBCR_EDE 0x02000000            /* Exception Debug Event */
+#define DBCR_TDE 0x01000000            /* TRAP Debug Event */
+#define DBCR_FER 0x00F80000            /* First Events Remaining Mask */
+#define DBCR_FT 0x00040000             /* Freeze Timers on Debug Event */
+#define DBCR_IA1 0x00020000            /* Instr. Addr. Compare 1 Enable */
+#define DBCR_IA2 0x00010000            /* Instr. Addr. Compare 2 Enable */
+#define DBCR_D1R 0x00008000            /* Data Addr. Compare 1 Read Enable */
+#define DBCR_D1W 0x00004000            /* Data Addr. Compare 1 Write Enable */
+#define DBCR_D1S(x) (((x) &0x3) << 12) /* Data Adrr. Compare 1 Size */
 #define DAC_BYTE 0
 #define DAC_HALF 1
 #define DAC_WORD 2
 #define DAC_QUAD 3
-#define DBCR_D2R 0x00000800            /* Data Addr. Compare 2 Read Enable */
-#define DBCR_D2W 0x00000400            /* Data Addr. Compare 2 Write Enable */
-#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
-#define DBCR_SBT 0x00000040            /* Second Branch Taken Debug Event */
-#define DBCR_SED 0x00000020            /* Second Exception Debug Event */
-#define DBCR_STD 0x00000010            /* Second Trap Debug Event */
-#define DBCR_SIA 0x00000008            /* Second IAC Enable */
-#define DBCR_SDA 0x00000004            /* Second DAC Enable */
-#define DBCR_JOI 0x00000002            /* JTAG Serial Outbound Int. Enable */
-#define DBCR_JII 0x00000001            /* JTAG Serial Inbound Int. Enable */
+#define DBCR_D2R 0x00000800           /* Data Addr. Compare 2 Read Enable */
+#define DBCR_D2W 0x00000400           /* Data Addr. Compare 2 Write Enable */
+#define DBCR_D2S(x) (((x) &0x3) << 8) /* Data Addr. Compare 2 Size */
+#define DBCR_SBT 0x00000040           /* Second Branch Taken Debug Event */
+#define DBCR_SED 0x00000020           /* Second Exception Debug Event */
+#define DBCR_STD 0x00000010           /* Second Trap Debug Event */
+#define DBCR_SIA 0x00000008           /* Second IAC Enable */
+#define DBCR_SDA 0x00000004           /* Second DAC Enable */
+#define DBCR_JOI 0x00000002           /* JTAG Serial Outbound Int. Enable */
+#define DBCR_JII 0x00000001           /* JTAG Serial Inbound Int. Enable */
 #ifndef CONFIG_BOOKE
 #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
 #else
@@ -396,27 +396,27 @@ struct pt_regs {
 #ifdef CONFIG_E500MC
 #define TCR_WP(x) (((64 - x) & 0x3) << 30) | (((64 - x) & 0x3c) << 15) /* WDT Period 2^x clocks*/
 #else
-#define TCR_WP(x) (((x) & 0x3) << 30)  /* WDT Period */
-#define WP_2_17 0                      /* 2^17 clocks */
-#define WP_2_21 1                      /* 2^21 clocks */
-#define WP_2_25 2                      /* 2^25 clocks */
-#define WP_2_29 3                      /* 2^29 clocks */
-#endif                                 /* CONFIG_E500 */
-#define TCR_WRC(x) (((x) & 0x3) << 28) /* WDT Reset Control */
-#define WRC_NONE 0                     /* No reset will occur */
-#define WRC_CORE 1                     /* Core reset will occur */
-#define WRC_CHIP 2                     /* Chip reset will occur */
-#define WRC_SYSTEM 3                   /* System reset will occur */
-#define TCR_WIE 0x08000000             /* WDT Interrupt Enable */
-#define TCR_PIE 0x04000000             /* PIT Interrupt Enable */
-#define TCR_FP(x) (((x) & 0x3) << 24)  /* FIT Period */
-#define FP_2_9 0                       /* 2^9 clocks */
-#define FP_2_13 1                      /* 2^13 clocks */
-#define FP_2_17 2                      /* 2^17 clocks */
-#define FP_2_21 3                      /* 2^21 clocks */
-#define TCR_FIE 0x00800000             /* FIT Interrupt Enable */
-#define TCR_ARE 0x00400000             /* Auto Reload Enable */
-#define SPRN_THRM1 0x3FC               /* Thermal Management Register 1 */
+#define TCR_WP(x) (((x) &0x3) << 30)  /* WDT Period */
+#define WP_2_17 0                     /* 2^17 clocks */
+#define WP_2_21 1                     /* 2^21 clocks */
+#define WP_2_25 2                     /* 2^25 clocks */
+#define WP_2_29 3                     /* 2^29 clocks */
+#endif                                /* CONFIG_E500 */
+#define TCR_WRC(x) (((x) &0x3) << 28) /* WDT Reset Control */
+#define WRC_NONE 0                    /* No reset will occur */
+#define WRC_CORE 1                    /* Core reset will occur */
+#define WRC_CHIP 2                    /* Chip reset will occur */
+#define WRC_SYSTEM 3                  /* System reset will occur */
+#define TCR_WIE 0x08000000            /* WDT Interrupt Enable */
+#define TCR_PIE 0x04000000            /* PIT Interrupt Enable */
+#define TCR_FP(x) (((x) &0x3) << 24)  /* FIT Period */
+#define FP_2_9 0                      /* 2^9 clocks */
+#define FP_2_13 1                     /* 2^13 clocks */
+#define FP_2_17 2                     /* 2^17 clocks */
+#define FP_2_21 3                     /* 2^21 clocks */
+#define TCR_FIE 0x00800000            /* FIT Interrupt Enable */
+#define TCR_ARE 0x00400000            /* Auto Reload Enable */
+#define SPRN_THRM1 0x3FC              /* Thermal Management Register 1 */
 #define THRM1_TIN (1 << 0)
 #define THRM1_TIV (1 << 1)
 #define THRM1_THRES (0x7f << 2)
@@ -430,26 +430,26 @@ struct pt_regs {
 #ifndef CONFIG_BOOKE
 #define SPRN_TSR 0x3D8 /* Timer Status Register */
 #else
-#define SPRN_TSR 0x150                 /* Book E Timer Status Register */
-#endif                                 /* CONFIG_BOOKE */
-#define TSR_ENW 0x80000000             /* Enable Next Watchdog */
-#define TSR_WIS 0x40000000             /* WDT Interrupt Status */
-#define TSR_WRS(x) (((x) & 0x3) << 28) /* WDT Reset Status */
-#define WRS_NONE 0                     /* No WDT reset occurred */
-#define WRS_CORE 1                     /* WDT forced core reset */
-#define WRS_CHIP 2                     /* WDT forced chip reset */
-#define WRS_SYSTEM 3                   /* WDT forced system reset */
-#define TSR_PIS 0x08000000             /* PIT Interrupt Status */
-#define TSR_FIS 0x04000000             /* FIT Interrupt Status */
-#define SPRN_UMMCR0 0x3A8              /* User Monitor Mode Control Register 0 */
-#define SPRN_UMMCR1 0x3AC              /* User Monitor Mode Control Register 0 */
-#define SPRN_UPMC1 0x3A9               /* User Performance Counter Register 1 */
-#define SPRN_UPMC2 0x3AA               /* User Performance Counter Register 2 */
-#define SPRN_UPMC3 0x3AD               /* User Performance Counter Register 3 */
-#define SPRN_UPMC4 0x3AE               /* User Performance Counter Register 4 */
-#define SPRN_USIA 0x3AB                /* User Sampled Instruction Address Register */
-#define SPRN_XER 0x001                 /* Fixed Point Exception Register */
-#define SPRN_ZPR 0x3B0                 /* Zone Protection Register */
+#define SPRN_TSR 0x150                /* Book E Timer Status Register */
+#endif                                /* CONFIG_BOOKE */
+#define TSR_ENW 0x80000000            /* Enable Next Watchdog */
+#define TSR_WIS 0x40000000            /* WDT Interrupt Status */
+#define TSR_WRS(x) (((x) &0x3) << 28) /* WDT Reset Status */
+#define WRS_NONE 0                    /* No WDT reset occurred */
+#define WRS_CORE 1                    /* WDT forced core reset */
+#define WRS_CHIP 2                    /* WDT forced chip reset */
+#define WRS_SYSTEM 3                  /* WDT forced system reset */
+#define TSR_PIS 0x08000000            /* PIT Interrupt Status */
+#define TSR_FIS 0x04000000            /* FIT Interrupt Status */
+#define SPRN_UMMCR0 0x3A8             /* User Monitor Mode Control Register 0 */
+#define SPRN_UMMCR1 0x3AC             /* User Monitor Mode Control Register 0 */
+#define SPRN_UPMC1 0x3A9              /* User Performance Counter Register 1 */
+#define SPRN_UPMC2 0x3AA              /* User Performance Counter Register 2 */
+#define SPRN_UPMC3 0x3AD              /* User Performance Counter Register 3 */
+#define SPRN_UPMC4 0x3AE              /* User Performance Counter Register 4 */
+#define SPRN_USIA 0x3AB               /* User Sampled Instruction Address Register */
+#define SPRN_XER 0x001                /* Fixed Point Exception Register */
+#define SPRN_ZPR 0x3B0                /* Zone Protection Register */
 
 /* Book E definitions */
 #define SPRN_DECAR 0x036   /* Decrementer Auto Reload Register */
@@ -854,7 +854,7 @@ struct pt_regs {
 #define IOCR_PTD 0x00000400
 #define IOCR_ARE 0x00000080
 #define IOCR_DRC 0x00000020
-#define IOCR_RDM(x) (((x) & 0x3) << 3)
+#define IOCR_RDM(x) (((x) &0x3) << 3)
 #define IOCR_TCS 0x00000004
 #define IOCR_SCS 0x00000002
 #define IOCR_SPC 0x00000001
diff --git a/src/coreboot-start.c b/src/coreboot-start.c
index eeeaabc..38aa760 100644
--- a/src/coreboot-start.c
+++ b/src/coreboot-start.c
@@ -113,8 +113,7 @@ void cb_start_exec(void) {
   } else {
     cb_put_string("CB> Trying EPM partition...\r\n");
 
-    part_block_t* blk =
-        cb_parse_partition_block_at((voidptr_t) CB_BOOT_ADDR, EPM_PART_BLK_SZ, 0);
+    part_block_t* blk = cb_parse_partition_block_at((voidptr_t) CB_BOOT_ADDR, EPM_PART_BLK_SZ, 0);
 
     if (blk) {
       cb_pci_append_tree("@stage2-epm", (cb_pci_num_t) blk, sizeof(part_block_t) * blk->num_blocks);
diff --git a/src/ppc64/ppc64-uart.c b/src/ppc64/ppc64-uart.c
index c16657d..b3b5717 100644
--- a/src/ppc64/ppc64-uart.c
+++ b/src/ppc64/ppc64-uart.c
@@ -20,7 +20,8 @@ volatile ascii_char_t* const UART0DR = (ascii_char_t*) CB_NS16550_COM1;
 /// @param
 /// @return
 utf_char_t cb_get_char(void) {
-  while (!(*(((volatile uint8_t*) UART0DR) + 0x05) & 0x01));
+  while (!(*(((volatile uint8_t*) UART0DR) + 0x05) & 0x01))
+    ;
   return (utf_char_t) *UART0DR;
 }
 
diff --git a/src/rv64/rv64-uart.c b/src/rv64/rv64-uart.c
index a859add..3f604fe 100644
--- a/src/rv64/rv64-uart.c
+++ b/src/rv64/rv64-uart.c
@@ -16,7 +16,8 @@ static uint8_t* cb_uart_ptr = (uint8_t*) CB_UART_BASE;
 utf_char_t cb_get_char(void) {
   uintptr_t ptr = CB_UART_BASE;
 
-  while (!(*(((volatile uint8_t*) ptr) + 0x05) & 0x01));
+  while (!(*(((volatile uint8_t*) ptr) + 0x05) & 0x01))
+    ;
 
   return (utf_char_t) *cb_uart_ptr;
 }
-- 
cgit v1.2.3


From 18d33e155d2f56e59eb49dadbb30ab2f7ac3e852 Mon Sep 17 00:00:00 2001
From: Amlal El Mahrouss <amlal@nekernel.org>
Date: Thu, 31 Jul 2025 08:49:33 +0100
Subject: feat: fix magic number of BootNet module, and fix compile_flags.txt

Signed-off-by: Amlal El Mahrouss <amlal@nekernel.org>
---
 compile_flags.txt       |  3 ++-
 lib/bootnet.h           |  4 ++--
 lib/cxx-abi.h           | 21 ---------------------
 lib/cxx-abi.hpp         | 21 +++++++++++++++++++++
 src/coreboot-cxx-abi.cc |  2 +-
 5 files changed, 26 insertions(+), 25 deletions(-)
 delete mode 100644 lib/cxx-abi.h
 create mode 100644 lib/cxx-abi.hpp

(limited to 'src')

diff --git a/compile_flags.txt b/compile_flags.txt
index 4e3bed0..8a21070 100644
--- a/compile_flags.txt
+++ b/compile_flags.txt
@@ -1,3 +1,4 @@
 -I./
--std=c17
+-std=c++20
 -I./vendor/
+-xc++
\ No newline at end of file
diff --git a/lib/bootnet.h b/lib/bootnet.h
index cba847c..2176c04 100644
--- a/lib/bootnet.h
+++ b/lib/bootnet.h
@@ -8,7 +8,7 @@
 
 #include <lib/boot.h>
 
-#define BOOTNET_INET_MAGIC "NETB"
+#define BOOTNET_INET_MAGIC "ONET"
 #define BOOTNET_INET_MAGIC_LEN (4)
 
 #define BOOTNET_NAME_LEN (256)
@@ -26,7 +26,7 @@ typedef struct bootnet_inet_header {
   ascii_char_t m_patch_name[BOOTNET_NAME_LEN];  /// example: ColdChoco
   int32_t      m_length;                        /// The patch's length.
   ascii_char_t m_target[BOOTNET_NAME_LEN];      /// The target file.
-  uint8_t      m_implies_program;               /// does it imply reprogramming?
+  uint8_t      m_implies_rom;               /// does it imply reprogramming?
   uint8_t      m_preflight;  /// Do we just check if this endpoint exists/is valid?
   uint8_t      m_blob[];
 } bootnet_inet_header;
diff --git a/lib/cxx-abi.h b/lib/cxx-abi.h
deleted file mode 100644
index 61225fc..0000000
--- a/lib/cxx-abi.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* -------------------------------------------
-
-  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
-
-------------------------------------------- */
-
-#pragma once
-
-#define DSO_MAX_OBJECTS (128)
-
-struct atexit_func_entry_t {
-  void (*destructor_func)(void*);
-  void* obj_ptr;
-  void* dso_handle;
-};
-
-typedef unsigned uarch_t;
-
-namespace cxxabiv1 {
-typedef void* __guard;
-}
diff --git a/lib/cxx-abi.hpp b/lib/cxx-abi.hpp
new file mode 100644
index 0000000..61225fc
--- /dev/null
+++ b/lib/cxx-abi.hpp
@@ -0,0 +1,21 @@
+/* -------------------------------------------
+
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+
+------------------------------------------- */
+
+#pragma once
+
+#define DSO_MAX_OBJECTS (128)
+
+struct atexit_func_entry_t {
+  void (*destructor_func)(void*);
+  void* obj_ptr;
+  void* dso_handle;
+};
+
+typedef unsigned uarch_t;
+
+namespace cxxabiv1 {
+typedef void* __guard;
+}
diff --git a/src/coreboot-cxx-abi.cc b/src/coreboot-cxx-abi.cc
index 70d9e62..88b2a6a 100644
--- a/src/coreboot-cxx-abi.cc
+++ b/src/coreboot-cxx-abi.cc
@@ -4,7 +4,7 @@
 
 ------------------------------------------- */
 
-#include <lib/cxx-abi.h>
+#include <lib/cxx-abi.hpp>
 
 /// BUGS: 0
 
-- 
cgit v1.2.3


From 1891d7343a9ac25ab157c4495581a0fcbd7fbcbf Mon Sep 17 00:00:00 2001
From: Amlal El Mahrouss <amlal@nekernel.org>
Date: Thu, 31 Jul 2025 08:57:14 +0100
Subject: feat! refactor NeBoot for NeKernel.org v1.0.0

Signed-off-by: Amlal El Mahrouss <amlal@nekernel.org>
---
 Doxyfile                           |   2 +-
 ReadMe.md                          |   4 +
 docs/tex/30pin.tex                 |   4 +-
 lib/30pin.h                        |  10 +--
 lib/boot.h                         |  48 ++++++------
 lib/fd.h                           |   2 +-
 lib/mp-bit.h                       |   2 +-
 lib/pci-tree.h                     |  14 ++--
 lib/ppc64/processor.h              |  16 ++--
 lib/xcoff.h                        |   2 +-
 libfdt/README                      |   2 +-
 libfdt/libfdt_env.h                |   6 +-
 src/amd64/amd64-boot.asm           |   2 +-
 src/amd64/amd64-test.asm           |   2 +-
 src/arm64/arm64-uart.c             |   2 +-
 src/arm64/ci.make                  |   4 +-
 src/arm64/makefile                 |   4 +-
 src/coreboot-bootnet.c             |   7 --
 src/coreboot-cpu-api.c             |  20 -----
 src/coreboot-cxx-abi.cc            |  77 ------------------
 src/coreboot-partition-map-parse.c |  42 ----------
 src/coreboot-partition-map.c       |  30 -------
 src/coreboot-pci-tree.c            |  96 -----------------------
 src/coreboot-print-name.c          |  27 -------
 src/coreboot-start.c               | 155 -------------------------------------
 src/coreboot-string.c              | 153 ------------------------------------
 src/hal/coreboot-ahci-driver.c     |  96 -----------------------
 src/hal/coreboot-flash-driver.c    |  10 ---
 src/hal/neboot-ahci-driver.c       |  96 +++++++++++++++++++++++
 src/hal/neboot-flash-driver.c      |  10 +++
 src/neboot-bootnet.c               |   7 ++
 src/neboot-cpu-api.c               |  20 +++++
 src/neboot-cxx-abi.cc              |  77 ++++++++++++++++++
 src/neboot-partition-map-parse.c   |  42 ++++++++++
 src/neboot-partition-map.c         |  30 +++++++
 src/neboot-pci-tree.c              |  96 +++++++++++++++++++++++
 src/neboot-print-name.c            |  27 +++++++
 src/neboot-start.c                 | 155 +++++++++++++++++++++++++++++++++++++
 src/neboot-string.c                | 153 ++++++++++++++++++++++++++++++++++++
 src/ppc64/makefile                 |   4 +-
 src/ppc64/ppc64-boot.S             |   6 +-
 src/ppc64/ppc64-hal.c              |  12 +--
 src/ppc64/ppc64-uart.c             |   6 +-
 src/rv64/ci.make                   |   4 +-
 src/rv64/makefile                  |   4 +-
 src/rv64/rv64-api.s                |   2 +-
 src/rv64/rv64-boot.s               |   6 +-
 src/rv64/rv64-uart.c               |   4 +-
 48 files changed, 802 insertions(+), 798 deletions(-)
 delete mode 100644 src/coreboot-bootnet.c
 delete mode 100644 src/coreboot-cpu-api.c
 delete mode 100644 src/coreboot-cxx-abi.cc
 delete mode 100644 src/coreboot-partition-map-parse.c
 delete mode 100644 src/coreboot-partition-map.c
 delete mode 100644 src/coreboot-pci-tree.c
 delete mode 100644 src/coreboot-print-name.c
 delete mode 100644 src/coreboot-start.c
 delete mode 100644 src/coreboot-string.c
 delete mode 100644 src/hal/coreboot-ahci-driver.c
 delete mode 100644 src/hal/coreboot-flash-driver.c
 create mode 100644 src/hal/neboot-ahci-driver.c
 create mode 100644 src/hal/neboot-flash-driver.c
 create mode 100644 src/neboot-bootnet.c
 create mode 100644 src/neboot-cpu-api.c
 create mode 100644 src/neboot-cxx-abi.cc
 create mode 100644 src/neboot-partition-map-parse.c
 create mode 100644 src/neboot-partition-map.c
 create mode 100644 src/neboot-pci-tree.c
 create mode 100644 src/neboot-print-name.c
 create mode 100644 src/neboot-start.c
 create mode 100644 src/neboot-string.c

(limited to 'src')

diff --git a/Doxyfile b/Doxyfile
index 89a1faa..b56bcb7 100644
--- a/Doxyfile
+++ b/Doxyfile
@@ -42,7 +42,7 @@ DOXYFILE_ENCODING      = UTF-8
 # title of most generated pages and in a few other places.
 # The default value is: My Project.
 
-PROJECT_NAME           = "CoreBoot"
+PROJECT_NAME           = "NeBoot"
 
 # The PROJECT_NUMBER tag can be used to enter a project or revision number. This
 # could be handy for archiving the generated documentation or if some version
diff --git a/ReadMe.md b/ReadMe.md
index 9d5904f..0ac4b47 100644
--- a/ReadMe.md
+++ b/ReadMe.md
@@ -4,6 +4,10 @@
 [![License: GPL-3.0](https://img.shields.io/badge/license-GPL--3.0-blue.svg)](LICENSE)
 [![QEMU Tested](https://img.shields.io/badge/QEMU-Tested-success)](#)
 
+# Brief
+
+NeBoot is a cross-platform open implementation of a firmware written in C, designed with modularity and portability in mind.
+
 ## Notice for Doxygen:
 
 Build the documentation using Doxygen's `doxygen` CLI tool.
diff --git a/docs/tex/30pin.tex b/docs/tex/30pin.tex
index 4c4b9ae..fa0b314 100644
--- a/docs/tex/30pin.tex
+++ b/docs/tex/30pin.tex
@@ -50,8 +50,8 @@ struct _cb_tpin_recovery_packet
 {
     uint8_t mag[CP_30PIN_MAG_LEN];     // Magic number
     uint8_t kind;                      // Packet kind identifier
-    uint8_t buffer[CB_30PIN_BUFFER_LEN]; // Packet data buffer
-    uint8_t eop[CB_30PIN_EOP_LEN];     // End-of-packet data
+    uint8_t buffer[NB_30PIN_BUFFER_LEN]; // Packet data buffer
+    uint8_t eop[NB_30PIN_EOP_LEN];     // End-of-packet data
 };
 \end{lstlisting}
 
diff --git a/lib/30pin.h b/lib/30pin.h
index 68691b9..7128c3f 100644
--- a/lib/30pin.h
+++ b/lib/30pin.h
@@ -12,11 +12,11 @@
 /// @brief 30pin recovery protocol.
 /// @details This file contains the definitions and structures used for the 30pin recovery protocol.
 
-#define CB_30PIN_MAG "TP"
+#define NB_30PIN_MAG "TP"
 #define CP_30PIN_MAG_LEN (2)
 
-#define CB_30PIN_BUFFER_LEN (498)
-#define CB_30PIN_EOP_LEN (11)
+#define NB_30PIN_BUFFER_LEN (498)
+#define NB_30PIN_EOP_LEN (11)
 
 /// @brief 30pin recovery header.
 /// @param mag magic number.
@@ -26,8 +26,8 @@
 struct _cb_tpin_recovery_packet {
   uint8_t mag[CP_30PIN_MAG_LEN];
   uint8_t kind;
-  uint8_t buffer[CB_30PIN_BUFFER_LEN];
-  uint8_t eop[CB_30PIN_EOP_LEN];
+  uint8_t buffer[NB_30PIN_BUFFER_LEN];
+  uint8_t eop[NB_30PIN_EOP_LEN];
 };
 
 /// @brief 30pin recovery packet kinds.
diff --git a/lib/boot.h b/lib/boot.h
index cf90766..5aab52b 100644
--- a/lib/boot.h
+++ b/lib/boot.h
@@ -8,7 +8,7 @@
 
 ///
 /// @file boot.h
-/// @brief CoreBoot types, data structures, and standard library.
+/// @brief NeBoot types, data structures, and standard library.
 ///
 
 typedef __UINTPTR_TYPE__ uintptr_t;
@@ -66,34 +66,34 @@ typedef ptrtype_t        size_t;
 #define true yes
 #endif  //!_cplusplus
 
-#define CB_RESTART 0
-#define CB_SHUTDOWN 1
+#define NB_RESTART 0
+#define NB_SHUTDOWN 1
 
 #define __COPYRIGHT(s) /* unused */
 
 #ifdef __COMPILE_RISCV__
-#define CB_BOOT_ADDR (0x80020000)
-#define CB_BOOT_ADDR_STR "0x80020000"
-#define CB_FRAMEBUFFER_ADDR 0x40000000L
-#define CB_UART_BASE 0x10000000
-#define CB_FLASH_BASE_ADDR 0x08000000
+#define NB_BOOT_ADDR (0x80020000)
+#define NB_BOOT_ADDR_STR "0x80020000"
+#define NB_FRAMEBUFFER_ADDR 0x40000000L
+#define NB_UART_BASE 0x10000000
+#define NB_FLASH_BASE_ADDR 0x08000000
 
 #define cb_sync_synchronize() __sync_synchronize()
 #elif defined(__COMPILE_POWERPC__)
-#define CB_UART_BASE 0x10000000
-#define CB_BOOT_ADDR 0x1030000
-#define CB_BOOT_ADDR_STR "0x1030000"
-#define CB_FRAMEBUFFER_ADDR 0x40000000L
-#define CB_FLASH_BASE_ADDR 0x08000000
+#define NB_UART_BASE 0x10000000
+#define NB_BOOT_ADDR 0x1030000
+#define NB_BOOT_ADDR_STR "0x1030000"
+#define NB_FRAMEBUFFER_ADDR 0x40000000L
+#define NB_FLASH_BASE_ADDR 0x08000000
 
 #define cb_sync_synchronize() __sync_synchronize()
 #elif defined(__COMPILE_ARM64__)
 
-#define CB_UART_BASE 0x09000000
-#define CB_BOOT_ADDR 0x1030000
-#define CB_BOOT_ADDR_STR "0x1030000"
-#define CB_FRAMEBUFFER_ADDR 0x40000000L
-#define CB_FLASH_BASE_ADDR 0x60000000
+#define NB_UART_BASE 0x09000000
+#define NB_BOOT_ADDR 0x1030000
+#define NB_BOOT_ADDR_STR "0x1030000"
+#define NB_FRAMEBUFFER_ADDR 0x40000000L
+#define NB_FLASH_BASE_ADDR 0x60000000
 
 static inline void __sync_synchronize(void) {
   /// leave it as is.
@@ -102,17 +102,17 @@ static inline void __sync_synchronize(void) {
 #define cb_sync_synchronize() __sync_synchronize()
 #endif  // ifndef __COMPILE_POWERPC__
 
-#define CB_BAUDRATE_TABLE \
+#define NB_BAUDRATE_TABLE \
   { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
 
-#define CB_STRING(s) #s
+#define NB_STRING(s) #s
 
-#define CB_BOOT_MAG_0 'C'
-#define CB_BOOT_MAG_1 'B'
+#define NB_BOOT_MAG_0 'C'
+#define NB_BOOT_MAG_1 'B'
 
-#define CB_BOOT_VER 0x101
+#define NB_BOOT_VER 0x101
 
-#define CB_BOOT_CALL(struct, offset)                                       \
+#define NB_BOOT_CALL(struct, offset)                                       \
   volatile cb_proc_t proc_##offset = (volatile cb_proc_t)(struct->offset); \
   proc_##offset();
 
diff --git a/lib/fd.h b/lib/fd.h
index 23a107d..1949c48 100644
--- a/lib/fd.h
+++ b/lib/fd.h
@@ -10,7 +10,7 @@
 
 struct _cb_file_descriptor;
 
-/// @brief CoreBoot file/device descriptor.
+/// @brief NeBoot file/device descriptor.
 /// @version 1
 typedef struct _cb_file_descriptor {
   int32_t f_kind;
diff --git a/lib/mp-bit.h b/lib/mp-bit.h
index 869c7c3..924fcdf 100644
--- a/lib/mp-bit.h
+++ b/lib/mp-bit.h
@@ -7,7 +7,7 @@
 #ifndef __BITMANIP_H__
 #define __BITMANIP_H__
 
-/// Name: CoreBoot Bits API.
+/// Name: NeBoot Bits API.
 /// Purpose: Bit manip helpers.
 
 #define cb_set_bit(X, O) X = (1 << O) | X
diff --git a/lib/pci-tree.h b/lib/pci-tree.h
index 2c4ca1f..a68fd4c 100644
--- a/lib/pci-tree.h
+++ b/lib/pci-tree.h
@@ -16,16 +16,16 @@
 #define PCI_INVALID_DATA_U16 ((uint16_t) ~0)
 #define PCI_INVALID_DATA_U32 ((uint32_t) ~0)
 
-#define CB_BASE_ADDRESS (0x20008000) /* PCI base mapped in virtual memory. */
-#define CB_PCI_TREE_BASE (0x802000)  /* The PCI tree base address. */
+#define NB_BASE_ADDRESS (0x20008000) /* PCI base mapped in virtual memory. */
+#define NB_PCI_TREE_BASE (0x802000)  /* The PCI tree base address. */
 
 /* version 1.0 */
-#define CB_PCI_VERSION (0x0100)
+#define NB_PCI_VERSION (0x0100)
 
-#define CB_PCI_DEV_MAGIC (0xfeedd00d)
-#define CB_PCI_INT_SZ sizeof(cb_pci_num_t)
+#define NB_PCI_DEV_MAGIC (0xfeedd00d)
+#define NB_PCI_INT_SZ sizeof(cb_pci_num_t)
 
-#define CB_PCI_NAME_LEN (255U)
+#define NB_PCI_NAME_LEN (255U)
 
 #define PCI_CONFIG_SPACE (4096U)
 
@@ -53,7 +53,7 @@ struct hw_cb_pci_tree {
   cb_pci_num_t d_first_node;
   cb_pci_num_t d_next_sibling;
 
-  cb_pci_char_t d_name[CB_PCI_NAME_LEN];
+  cb_pci_char_t d_name[NB_PCI_NAME_LEN];
 };
 
 /// @brief Init PCI tree.
diff --git a/lib/ppc64/processor.h b/lib/ppc64/processor.h
index bbeb0c9..3e6e04d 100644
--- a/lib/ppc64/processor.h
+++ b/lib/ppc64/processor.h
@@ -1023,29 +1023,29 @@ struct pt_regs {
 /*
  * 405EX/EXr CHIP_21 Errata
  */
-#ifdef CONFIG_CB_4xx_CHIP_21_405EX_SECURITY
-#define CONFIG_CB_4xx_CHIP_21_ERRATA
+#ifdef CONFIG_NB_4xx_CHIP_21_405EX_SECURITY
+#define CONFIG_NB_4xx_CHIP_21_ERRATA
 #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX1_RC
 #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX1_RD
 #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x0
 #endif
 
-#ifdef CONFIG_CB_4xx_CHIP_21_405EX_NO_SECURITY
-#define CONFIG_CB_4xx_CHIP_21_ERRATA
+#ifdef CONFIG_NB_4xx_CHIP_21_405EX_NO_SECURITY
+#define CONFIG_NB_4xx_CHIP_21_ERRATA
 #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX2_RC
 #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX2_RD
 #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x1
 #endif
 
-#ifdef CONFIG_CB_4xx_CHIP_21_405EXr_SECURITY
-#define CONFIG_CB_4xx_CHIP_21_ERRATA
+#ifdef CONFIG_NB_4xx_CHIP_21_405EXr_SECURITY
+#define CONFIG_NB_4xx_CHIP_21_ERRATA
 #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR1_RC
 #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR1_RD
 #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x2
 #endif
 
-#ifdef CONFIG_CB_4xx_CHIP_21_405EXr_NO_SECURITY
-#define CONFIG_CB_4xx_CHIP_21_ERRATA
+#ifdef CONFIG_NB_4xx_CHIP_21_405EXr_NO_SECURITY
+#define CONFIG_NB_4xx_CHIP_21_ERRATA
 #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR2_RC
 #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR2_RD
 #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x3
diff --git a/lib/xcoff.h b/lib/xcoff.h
index abfa35a..689c570 100644
--- a/lib/xcoff.h
+++ b/lib/xcoff.h
@@ -3,7 +3,7 @@
   Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
 
   File: xcoff.h
-  Purpose: XCOFF for CoreBoot.
+  Purpose: XCOFF for NeBoot.
 
   Revision History:
 
diff --git a/libfdt/README b/libfdt/README
index a96e4e3..583cbdc 100644
--- a/libfdt/README
+++ b/libfdt/README
@@ -1,4 +1,4 @@
 Flat Device Tree
 ================
 
-A new implementation of fdt compatible with CoreBoot.
\ No newline at end of file
+A new implementation of fdt compatible with NeBoot.
\ No newline at end of file
diff --git a/libfdt/libfdt_env.h b/libfdt/libfdt_env.h
index 6c5616c..b443449 100644
--- a/libfdt/libfdt_env.h
+++ b/libfdt/libfdt_env.h
@@ -4,8 +4,8 @@
 
 ------------------------------------------- */
 
-#ifndef __CB_FDT_H__
-#define __CB_FDT_H__
+#ifndef __NB_FDT_H__
+#define __NB_FDT_H__
 
 #include <lib/boot.h>
 
@@ -60,4 +60,4 @@ static inline fdt64_t cpu_to_fdt64(uint64_t x) {
 #undef CPU_TO_FDT16
 #undef EXTRACT_BYTE
 
-#endif  //!__CB_FDT_H__
+#endif  //!__NB_FDT_H__
diff --git a/src/amd64/amd64-boot.asm b/src/amd64/amd64-boot.asm
index bcd6058..d578aa9 100644
--- a/src/amd64/amd64-boot.asm
+++ b/src/amd64/amd64-boot.asm
@@ -1,4 +1,4 @@
-;; AMD64 CoreBoot Master Boot Program.
+;; AMD64 NeBoot Master Boot Program.
 ;; Written by Amlal EL Mahrouss
 
 %define ENTRYPOINT 0x00FF
diff --git a/src/amd64/amd64-test.asm b/src/amd64/amd64-test.asm
index 2a8bef8..b89e522 100644
--- a/src/amd64/amd64-test.asm
+++ b/src/amd64/amd64-test.asm
@@ -1,4 +1,4 @@
-;; AMD64 CoreBoot Sample program.
+;; AMD64 NeBoot Sample program.
 ;; Written by Amlal EL Mahrouss
 
 [bits 16]
diff --git a/src/arm64/arm64-uart.c b/src/arm64/arm64-uart.c
index 5a7f21d..4723204 100644
--- a/src/arm64/arm64-uart.c
+++ b/src/arm64/arm64-uart.c
@@ -13,7 +13,7 @@
 
 /* this file handles the UART */
 
-static uint32_t* cb_uart_ptr = (uint32_t*) CB_UART_BASE;
+static uint32_t* cb_uart_ptr = (uint32_t*) NB_UART_BASE;
 
 /// @brief Retrieve character from cb_uart_ptr
 utf_char_t cb_get_char(void) {
diff --git a/src/arm64/ci.make b/src/arm64/ci.make
index 07f1746..2b0fed2 100644
--- a/src/arm64/ci.make
+++ b/src/arm64/ci.make
@@ -1,7 +1,7 @@
  #
  #	========================================================
  #
- #	CoreBoot
+ #	NeBoot
  # 	Date Added: 08/11/2023
  # 	Copyright 2024, Amlal El Mahrouss, all rights reserved.
  #
@@ -34,7 +34,7 @@ WAIT=sleep 1
 
 .PHONY: all
 all: firmware-link
-	@echo "[CoreBoot] build done."
+	@echo "[NeBoot] build done."
 
 .PHONY: firmware-link
 firmware-link: firmware-compile
diff --git a/src/arm64/makefile b/src/arm64/makefile
index 8d05e8b..a85553b 100644
--- a/src/arm64/makefile
+++ b/src/arm64/makefile
@@ -1,7 +1,7 @@
  #
  #	========================================================
  #
- #	CoreBoot
+ #	NeBoot
  # 	Date Added: 08/11/2023
  # 	Copyright 2024, Amlal El Mahrouss, all rights reserved.
  #
@@ -34,7 +34,7 @@ WAIT=sleep 1
 
 .PHONY: all
 all: firmware-link
-	@echo "[CoreBoot] build done."
+	@echo "[NeBoot] build done."
 
 .PHONY: firmware-link
 firmware-link: firmware-compile
diff --git a/src/coreboot-bootnet.c b/src/coreboot-bootnet.c
deleted file mode 100644
index a547b35..0000000
--- a/src/coreboot-bootnet.c
+++ /dev/null
@@ -1,7 +0,0 @@
-/* -------------------------------------------
-
-  Copyright (C) 2025, Amlal EL Mahrouss, all rights reserved.
-
-------------------------------------------- */
-
-#include <lib/bootnet.h>
diff --git a/src/coreboot-cpu-api.c b/src/coreboot-cpu-api.c
deleted file mode 100644
index 2491f15..0000000
--- a/src/coreboot-cpu-api.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* -------------------------------------------
-
-  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
-
-------------------------------------------- */
-
-#include <lib/boot.h>
-
-/// @brief Restarts the computer.
-/// @param none.
-void cb_restart_machine(void) {
-#ifdef __COMPILE_RISCV__
-  volatile uint32_t* brd_pwr = (volatile uint32_t*) 0x100000;
-  *brd_pwr                   = 0x7777;  // send reboot signal from DMA.
-
-  while (1) {
-    asm volatile("wfi");
-  }
-#endif
-}
diff --git a/src/coreboot-cxx-abi.cc b/src/coreboot-cxx-abi.cc
deleted file mode 100644
index 88b2a6a..0000000
--- a/src/coreboot-cxx-abi.cc
+++ /dev/null
@@ -1,77 +0,0 @@
-/* -------------------------------------------
-
-  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
-
-------------------------------------------- */
-
-#include <lib/cxx-abi.hpp>
-
-/// BUGS: 0
-
-extern "C" __SIZE_TYPE__ cb_put_string(const char* text);
-extern "C" void          cb_panic(const char* reason);
-
-extern "C" void __stack_chk_fail() {
-  cb_put_string("[stack-canary] Buffer overflow detected, halting...\n");
-  cb_panic("stack_canary_fail");
-}
-
-void* __dso_handle;
-
-extern "C" __SIZE_TYPE__ cb_put_string(const char* text);
-extern "C" void          cb_panic(const char* reason);
-
-atexit_func_entry_t __atexit_funcs[DSO_MAX_OBJECTS];
-uarch_t             __atexit_func_count;
-
-extern "C" void __cxa_pure_virtual() {
-  cb_put_string("[__cxa_pure_virtual] Placeholder\n");
-}
-
-extern "C" int __cxa_atexit(void (*f)(void*), void* arg, void* dso) {
-  if (__atexit_func_count >= DSO_MAX_OBJECTS) return -1;
-
-  __atexit_funcs[__atexit_func_count].destructor_func = f;
-  __atexit_funcs[__atexit_func_count].obj_ptr         = arg;
-  __atexit_funcs[__atexit_func_count].dso_handle      = dso;
-
-  __atexit_func_count++;
-
-  return 0;
-}
-
-extern "C" void __cxa_finalize(void* f) {
-  uarch_t i = __atexit_func_count;
-  if (!f) {
-    while (i--) {
-      if (__atexit_funcs[i].destructor_func) {
-        (*__atexit_funcs[i].destructor_func)(__atexit_funcs[i].obj_ptr);
-      };
-    }
-
-    return;
-  }
-
-  while (i--) {
-    if (__atexit_funcs[i].destructor_func) {
-      (*__atexit_funcs[i].destructor_func)(__atexit_funcs[i].obj_ptr);
-      __atexit_funcs[i].destructor_func = 0;
-    };
-  }
-}
-
-namespace cxxabiv1 {
-extern "C" int __cxa_guard_acquire(__guard* g) {
-  (void) g;
-  return 0;
-}
-
-extern "C" int __cxa_guard_release(__guard* g) {
-  *(char*) g = 1;
-  return 0;
-}
-
-extern "C" void __cxa_guard_abort(__guard* g) {
-  (void) g;
-}
-}  // namespace cxxabiv1
diff --git a/src/coreboot-partition-map-parse.c b/src/coreboot-partition-map-parse.c
deleted file mode 100644
index 7d8f80f..0000000
--- a/src/coreboot-partition-map-parse.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* -------------------------------------------
-
-  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
-
-------------------------------------------- */
-
-#include <lib/partition-map.h>
-
-bool cb_parse_partition_block_data_at(voidptr_t blob, size_t blob_sz, size_t index, size_t* end_lba,
-                                      size_t* start_lba, size_t* sector_sz) {
-  if (!start_lba || !end_lba || !blob || !blob_sz || !sector_sz ||
-      (sizeof(part_block_t) * index) > blob_sz)
-    return false;
-
-  part_block_t* block = (part_block_t*) (blob + (sizeof(part_block_t) * index));
-
-  if (block->version != EPM_REVISION || block->num_blocks < 1 || block->num_blocks > EPM_MAX_BLKS ||
-      strcmp(block->magic, EPM_MAGIC) > 0 || block->lba_end == 0 || block->lba_start == 0) {
-    return false;
-  }
-
-  *end_lba   = block->lba_end;
-  *start_lba = block->lba_start;
-  *sector_sz = block->sector_sz;
-
-  return true;
-}
-
-part_block_t* cb_parse_partition_block_at(voidptr_t blob, size_t blob_sz, size_t index) {
-  if (!blob || !blob_sz || (sizeof(part_block_t) * index) > blob_sz) return nil;
-
-  part_block_t* block = (part_block_t*) (blob + (sizeof(part_block_t) * index));
-
-  cb_put_string(block->magic);
-
-  if (block->version != EPM_REVISION || block->num_blocks < 1 || block->num_blocks > EPM_MAX_BLKS ||
-      strcmp(block->magic, EPM_MAGIC) > 0 || block->lba_end == 0 || block->lba_start == 0) {
-    return nil;
-  }
-
-  return block;
-}
\ No newline at end of file
diff --git a/src/coreboot-partition-map.c b/src/coreboot-partition-map.c
deleted file mode 100644
index f5d937b..0000000
--- a/src/coreboot-partition-map.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* -------------------------------------------
-
-  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
-
-------------------------------------------- */
-
-#include <lib/partition-map.h>
-#include <lib/string.h>
-
-// include this for documentation.
-
-#define CB_FILESYSTEM_COUNT 4
-#define CB_FILESYSTEM_LIST \
-  { "NeFS", "HeFS", "FAT32", "ext4" }
-
-/// @brief check if filesystem is supported by CoreBoot.
-/// @param fs the filesystem magic, as provided by EPM.
-boolean cb_filesystem_exists(caddr_t fs, size_t len) {
-  if (fs == nil || *fs == 0) return no;
-
-  char* fs_list[] = CB_FILESYSTEM_LIST;
-
-  for (size_t fs_index = 0; fs_index < CB_FILESYSTEM_COUNT; fs_index++) {
-    if (strncmp(fs_list[fs_index], fs, strlen(fs_list[fs_index])) == 0) {
-      return yes;
-    }
-  }
-
-  return no;
-}
diff --git a/src/coreboot-pci-tree.c b/src/coreboot-pci-tree.c
deleted file mode 100644
index ce168fd..0000000
--- a/src/coreboot-pci-tree.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* -------------------------------------------
-
-  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
-
-------------------------------------------- */
-
-/**
- * @file coreboot-pci-tree.c
- * @author Amlal EL Mahrouss (amlal@nekernel.org)
- * @brief PCI tree implementation.
- * @version 0.1
- * @date 2024-01-22
- *
- * @copyright Copyright (c) 2024 Amlal EL Mahrouss
- *
- */
-
-#include <lib/pci-tree.h>
-#include <lib/string.h>
-
-/// BUGS: 0
-
-/// Standard Root table (Mahrouss Table)
-#define CB_PCI_ROOT_NAME "/pci-tree/@/"
-
-static struct hw_cb_pci_tree* cb_base_tree   = nil;
-static struct hw_cb_pci_tree* cb_latest_tree = nil;
-static struct hw_cb_pci_tree* cb_last_tree   = nil;
-
-/// \brief Init the PCI device tree structure.
-/// \return if it already exists -> false
-/// Otherwise true.
-boolean cb_pci_init_tree(void) {
-  cb_base_tree = (struct hw_cb_pci_tree*) (CB_PCI_TREE_BASE);
-
-  // huh? anyway let's ignore it then.
-  if (cb_base_tree->d_magic != CB_PCI_DEV_MAGIC) {
-    cb_base_tree->d_magic = CB_PCI_DEV_MAGIC;
-
-    memncpy(cb_base_tree->d_name, CB_PCI_ROOT_NAME, strlen(CB_PCI_ROOT_NAME));
-
-    cb_base_tree->d_next_sibling = 0;
-    cb_base_tree->d_off_props    = 0;
-    cb_base_tree->d_sz_struct    = 0;
-    cb_base_tree->d_sz_props     = 0;
-    cb_base_tree->d_off_struct   = 0;
-    cb_base_tree->d_version      = CB_PCI_VERSION;
-
-    cb_base_tree->d_next_sibling = (cb_pci_num_t) (cb_base_tree + sizeof(struct hw_cb_pci_tree));
-    cb_base_tree->d_first_node   = (cb_pci_num_t) cb_base_tree;
-
-    cb_put_string(">> Append root device: " CB_PCI_ROOT_NAME "\r\n");
-  }
-
-  cb_latest_tree = cb_base_tree;
-
-  return yes;
-}
-
-/// \brief Adds a new device to the tree.
-/// \param name the device name.
-/// \param struct_ptr the struct containing the device.
-/// \param struct_sz the structure size.
-boolean cb_pci_append_tree(const caddr_t name, cb_pci_num_t struct_ptr, cb_pci_num_t struct_sz) {
-  if (!name || *name == 0 || cb_latest_tree == nil) return no;
-
-  struct hw_cb_pci_tree* cb_pci_tree = (struct hw_cb_pci_tree*) (cb_latest_tree);
-
-  while (cb_pci_tree->d_magic == CB_PCI_DEV_MAGIC) {
-    if (strcmp(cb_pci_tree->d_name, name) == 0) return no;
-
-    cb_pci_tree = (struct hw_cb_pci_tree*) (cb_pci_tree + sizeof(struct hw_cb_pci_tree));
-  }
-
-  cb_pci_tree->d_magic = CB_PCI_DEV_MAGIC;
-
-  memncpy(cb_pci_tree->d_name, name, strlen(name));
-
-  cb_pci_tree->d_off_struct = struct_ptr;
-  cb_pci_tree->d_sz_struct  = struct_sz;
-  cb_pci_tree->d_off_props  = 0;
-  cb_pci_tree->d_sz_props   = 0;
-  cb_pci_tree->d_version    = CB_PCI_VERSION;
-
-  cb_pci_tree->d_next_sibling = (cb_pci_num_t) (cb_pci_tree + sizeof(struct hw_cb_pci_tree));
-  cb_pci_tree->d_first_node   = (cb_pci_num_t) cb_latest_tree;
-
-  cb_latest_tree = cb_pci_tree;
-  cb_last_tree   = cb_pci_tree;
-
-  cb_put_string(">> Append device: ");
-  cb_put_string(name);
-  cb_put_string("\r\n");
-
-  return yes;
-}
diff --git a/src/coreboot-print-name.c b/src/coreboot-print-name.c
deleted file mode 100644
index 6adb099..0000000
--- a/src/coreboot-print-name.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* -------------------------------------------
-
-  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
-
-------------------------------------------- */
-
-#include <lib/boot.h>
-
-/// @brief Print firmware name.
-/// @param
-void cb_print_name(void) {
-#ifdef __COMPILE_POWERPC__
-  cb_put_string(">> CoreBoot for POWERPC.\r\n");
-#endif  // __COMPILE_POWERPC__
-
-#ifdef __COMPILE_ARM64__
-  cb_put_string(">> CoreBoot for ARM64.\r\n");
-#endif  // __COMPILE_POWERPC__
-
-#ifdef __COMPILE_AMD64__
-  cb_put_string(">> CoreBoot for AMD64.\r\n");
-#endif  // __COMPILE_POWERPC__
-
-#ifdef __COMPILE_RISCV__
-  cb_put_string(">> CoreBoot for RISC-V.\r\n");
-#endif  // __COMPILE_POWERPC__
-}
diff --git a/src/coreboot-start.c b/src/coreboot-start.c
deleted file mode 100644
index 38aa760..0000000
--- a/src/coreboot-start.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/* -------------------------------------------
-
-  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
-
-------------------------------------------- */
-
-#include <lib/boot.h>
-#include <lib/mp-bit.h>
-#include <lib/partition-map.h>
-#include <lib/pci-tree.h>
-
-/// BUGS: 0
-
-/////////////////////////////////////////////////////////////////////////////////////////
-
-// @name start.c //
-
-// @brief Start file // This is where the firmware starts it's initialization //
-// code. //
-
-// @author Amlal EL Mahrouss //
-
-/////////////////////////////////////////////////////////////////////////////////////////
-
-extern void cb_start_context(uintptr_t);
-extern void cb_start_rom(void);
-
-extern int cb_boot_processor_ready;
-
-/// @brief hardware thread counter (rv64 only)
-#ifdef __COMPILE_RISCV__
-uint64_t __cb_hart_counter = 0UL;
-#endif
-
-/// @brief Start executing the firmware.
-/// @param
-void cb_start_exec(void) {
-#ifndef __COMPILE_RISCV__
-  static uint64_t __cb_hart_counter = 0UL;
-#endif
-
-  ++__cb_hart_counter;
-
-  uintptr_t hart = __cb_hart_counter;
-
-  // let the hart 0 init our stuff.
-  if (hart == 0) {
-    cb_put_string("CB> Welcome to CoreBoot, (c) Amlal EL Mahrouss. Built the ");
-    cb_put_string(__DATE__);
-    cb_put_string("\r\r\n");
-
-#ifdef __COMPILE_POWERPC__
-    cb_put_string("CB> CPU: PowerPC 64-bit Based SoC.\r\r\n");
-#endif  // __COMPILE_POWERPC__
-
-#ifdef __COMPILE_AMD64__
-    cb_put_string("CB> CPU: x64 Based SoC.\r\r\n");
-#endif  // __COMPILE_AMD64__
-
-#ifdef __COMPILE_ARM64__
-    cb_put_string("CB> CPU: AArch64 Based SoC.\r\r\n");
-#endif  // __COMPILE_ARM64__
-
-#ifdef __COMPILE_ARM32__
-    cb_put_string("CB> CPU: AArch32 Based SoC.\r\r\n");
-#endif  // __COMPILE_ARM64__
-
-#ifdef __COMPILE_RISCV__
-    cb_put_string("CB> CPU: RV64 Based SoC.\r\r\n");
-#endif  // __COMPILE_RISCV__
-  }
-
-  /// @brief Boots here if LX header matches what we except.
-
-  volatile struct cb_boot_header* boot_hdr = (volatile struct cb_boot_header*) (CB_FLASH_BASE_ADDR);
-
-  /**
-    boot if:
-      - ident matches.
-      - version matches.
-  */
-
-  if (boot_hdr->h_mag[0] == CB_BOOT_MAG_0 && boot_hdr->h_mag[1] == CB_BOOT_MAG_1) {
-    uint32_t rev = boot_hdr->h_revision;
-
-#ifdef __aarch64__
-    rev = __builtin_bswap32(rev);
-#endif
-
-    if (rev != CB_BOOT_VER) {
-      if (hart == 0) {
-        cb_put_string("CB> Can't Boot the StageTwo, LX invalid signature. (CB0003)\r\n");
-      }
-    } else {
-      if (hart == 0) {
-        cb_pci_append_tree("@stage2-lx", (cb_pci_num_t) boot_hdr, sizeof(struct cb_boot_header));
-
-        cb_put_string("CB> Executing StageTwo: ");
-        cb_put_string((const char*) boot_hdr->h_name);
-        cb_put_char('\r');
-        cb_put_char('\n');
-
-        // printf("CB> address: %x\n", boot_hdr->h_start_address);
-      }
-
-      if (boot_hdr->h_start_address != 0) {
-        cb_boot_processor_ready = 1;
-        cb_start_context(boot_hdr->h_start_address);
-      }
-
-      cb_put_string("CB> StageTwo has returned? (CB0002)\r\n");
-    }
-  } else {
-    cb_put_string("CB> Trying EPM partition...\r\n");
-
-    part_block_t* blk = cb_parse_partition_block_at((voidptr_t) CB_BOOT_ADDR, EPM_PART_BLK_SZ, 0);
-
-    if (blk) {
-      cb_pci_append_tree("@stage2-epm", (cb_pci_num_t) blk, sizeof(part_block_t) * blk->num_blocks);
-
-      size_t indx = 0;
-      size_t end_lba, start_lba, sector_sz;
-
-      while (indx < blk->num_blocks) {
-        if (cb_parse_partition_block_data_at(blk, EPM_PART_BLK_SZ * blk->num_blocks, indx, &end_lba,
-                                             &start_lba, &sector_sz) == no) {
-          ++indx;
-          continue;
-        }
-
-        cb_boot_processor_ready = 1;
-        cb_start_context((uintptr_t) (voidptr_t) blk + start_lba);
-
-        if (hart == 1) {
-          cb_put_string("CB> Can't boot to StageTwo. (CB0001)\r\n");
-        }
-      }
-    }
-
-    if (hart == 1) {
-      cb_put_string(
-          "CB> Can't boot to StageTwo via EPM, no bootable partition blocks found. (CB0001)\r\n");
-    }
-  }
-
-  /// end of TODO
-
-  if (hart > 1) {
-    while (yes) {
-      if (__cb_hart_counter == 0) {
-        cb_restart_machine();
-      }
-    }
-  }
-}
diff --git a/src/coreboot-string.c b/src/coreboot-string.c
deleted file mode 100644
index 355e734..0000000
--- a/src/coreboot-string.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* -------------------------------------------
-
-  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
-
-------------------------------------------- */
-
-/**
- * @file coreboot-string.c
- * @author Amlal EL Mahrouss (amlal@nekernel.org)
- * @brief string library.
- * @version 0.1
- * @date 2024-01-16
- *
- * @copyright Copyright (c) 2024 Amlal EL Mahrouss
- *
- */
-
-#include <lib/string.h>
-
-/// BUGS: 0
-
-size_t strncmp(const char* src, const char* cmp, size_t size) {
-  if (src == nil) return 0;
-
-  int32_t counter = 0;
-
-  for (size_t index = 0; index < size; ++index) {
-    if (src[index] != cmp[index]) ++counter;
-  }
-
-  return counter;
-}
-
-void* memset(void* ptr, const char value, size_t len) {
-  if (ptr == nil) return nil;
-
-  char* start = ptr;
-
-  while (len) {
-    *start = value;
-    ++start;
-
-    --len;
-  }
-
-  return (void*) start;
-}
-
-void* memmove(void* dest, const void* src, size_t len) {
-  memncpy(dest, src, len);
-  return dest;
-}
-
-size_t memcpy(void* dst, const void* src) {
-  if (src == nil || dst == nil) return 0;
-
-  const char* src_chr = src;
-  char*       dst_chr = dst;
-  size_t      index   = 0;
-  size_t      len     = strlen(src);
-
-  while (index < len) {
-    dst_chr[index] = src_chr[index];
-    ++index;
-  }
-
-  return 0;
-}
-
-/* @brief unoptimized memcpy, TODO: use isa specific memcpy. */
-size_t memncpy(void* dst, const void* src, size_t len) {
-#if __OL == 3 && defined(__riscv)
-  riscv_memncpy(dst, src, len);
-#else
-
-  if (src == nil || dst == nil) return 0;
-
-  const char* src_chr = src;
-  char*       dst_chr = dst;
-  size_t      index   = 0;
-
-  while (index < len) {
-    dst_chr[index] = src_chr[index];
-    ++index;
-  }
-
-  return 0;
-#endif
-}
-
-size_t strlen(const char* str) {
-  if (*str == 0) return 0;
-
-  size_t len = 0;
-  while (str[len] != '\0') ++len;
-
-  return len;
-}
-
-size_t strnlen(const char* str, size_t len) {
-  size_t cnt = 0;
-
-  while (len > cnt) {
-    ++cnt;
-
-    if (str[cnt] == '\0') return (size_t) -1;
-  }
-
-  return len;
-}
-
-void strreverse(char* s) {
-  if (s == nil) return;
-  if (*s == '\0') return;
-
-  char *first, *last, temp;
-
-  first = s;
-  last  = s + strlen(s) - 1;
-
-  while (first != last) {
-    temp       = *first;
-    *(first++) = *last;
-    *(last--)  = temp;
-  }
-}
-
-char* strchr(char* str, const char chr) {
-  while (*str != chr) {
-    ++str;
-
-    if (*str == 0) return nil;
-  }
-
-  return str;
-}
-
-/// @brief Compare two strings.
-/// @param src source string
-/// @param cmp string to compare.
-/// @return
-size_t strcmp(caddr_t src, caddr_t cmp) {
-  if (src == null || *src == 0) return 1;
-  if (cmp == null || *cmp == 0) return 1;
-
-  int32_t counter = 0;
-
-  for (size_t index = 0; src[index] != 0; ++index) {
-    if (cmp[index] != src[index]) ++counter;
-  }
-
-  return counter;
-}
diff --git a/src/hal/coreboot-ahci-driver.c b/src/hal/coreboot-ahci-driver.c
deleted file mode 100644
index 26a8907..0000000
--- a/src/hal/coreboot-ahci-driver.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* -------------------------------------------
-
-  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
-
-------------------------------------------- */
-
-/**
- * @file coreboot-ahci-driver.cc
- * @author Amlal EL Mahrouss (amlal@nekernel.org)
- * @brief SATA Disk support, via AHCI.
- * @version 0.2
- * @date 2024-01-16
- *
- * @copyright Copyright (c) 2024-2025, Amlal EL Mahrouss.
- *
- */
-
-#include <lib/boot.h>
-#include <lib/pci-tree.h>
-
-#define CB_AHCI_DRIVER_NAME ("@sata")
-
-/// BUGS: 0
-/// @brief AHCI support for PowerPC.
-
-/// @brief AHCI HBA port.
-typedef struct cb_hba_port {
-  uint32_t clb;            // 0x00, command list base address, 1K-byte aligned
-  uint32_t clbu;           // 0x04, command list base address upper 32 bits
-  uint32_t fb;             // 0x08, FIS base address, 256-byte aligned
-  uint32_t fbu;            // 0x0C, FIS base address upper 32 bits
-  uint32_t is;             // 0x10, interrupt status
-  uint32_t ie;             // 0x14, interrupt enable
-  uint32_t cmd;            // 0x18, command and status
-  uint32_t reserved0;      // 0x1C, Reserved
-  uint32_t tfd;            // 0x20, task file data
-  uint32_t sig;            // 0x24, signature
-  uint32_t ssts;           // 0x28, SATA status (SCR0:SStatus)
-  uint32_t sctl;           // 0x2C, SATA control (SCR2:SControl)
-  uint32_t serr;           // 0x30, SATA error (SCR1:SError)
-  uint32_t sact;           // 0x34, SATA active (SCR3:SActive)
-  uint32_t ci;             // 0x38, command issue
-  uint32_t sntf;           // 0x20, SATA notification (SCR4:SNotification)
-  uint32_t fbs;            // 0x40, FIS-based switch control
-  uint32_t reserved1[11];  // 0x44 ~ 0x6F, Reserved
-  uint32_t vendor[4];      // 0x70 ~ 0x7F, vendor specific
-} cb_hba_port_t;
-
-/// @brief Check if port is active.
-/// @param port host bus address port.
-/// @return whether sact is active or not.
-static boolean cb_hba_port_active(volatile cb_hba_port_t* port) {
-  if (!port) return false;
-
-  return port->sact;
-}
-
-/// @brief Start HBA command processor.
-/// @param port host bus address port.
-/// @return whether it was successful or not.
-static boolean cb_hba_start_cmd(volatile cb_hba_port_t* port) {
-  if (!port) return false;
-
-  size_t timeout = 1000000;
-
-  while ((port->cmd & 0x8000)) {
-    if (!timeout) return false;
-
-    --timeout;
-  }
-
-  port->cmd |= 0x0001;
-  port->cmd |= 0x0010;
-
-  return true;
-}
-
-/// @brief Stop HBA command from processing.
-/// @param port host bus address port.
-/// @return whether it was successful or not.
-static boolean cb_hba_stop_cmd(volatile cb_hba_port_t* port) {
-  if (!port) return false;
-
-  port->cmd &= ~0x0001;
-  port->cmd &= ~0x0010;
-
-  while (yes) {
-    if ((port->cmd & 0x8000)) continue;
-
-    if ((port->cmd & 0x4000)) continue;
-
-    break;
-  }
-
-  return true;
-}
diff --git a/src/hal/coreboot-flash-driver.c b/src/hal/coreboot-flash-driver.c
deleted file mode 100644
index d1b0907..0000000
--- a/src/hal/coreboot-flash-driver.c
+++ /dev/null
@@ -1,10 +0,0 @@
-/* -------------------------------------------
-
-Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
-
-------------------------------------------- */
-
-#include <lib/boot.h>
-#include <lib/mp-bit.h>
-#include <lib/partition-map.h>
-#include <lib/pci-tree.h>
diff --git a/src/hal/neboot-ahci-driver.c b/src/hal/neboot-ahci-driver.c
new file mode 100644
index 0000000..b9badd2
--- /dev/null
+++ b/src/hal/neboot-ahci-driver.c
@@ -0,0 +1,96 @@
+/* -------------------------------------------
+
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+
+------------------------------------------- */
+
+/**
+ * @file neboot-ahci-driver.cc
+ * @author Amlal EL Mahrouss (amlal@nekernel.org)
+ * @brief SATA Disk support, via AHCI.
+ * @version 0.2
+ * @date 2024-01-16
+ *
+ * @copyright Copyright (c) 2024-2025, Amlal EL Mahrouss.
+ *
+ */
+
+#include <lib/boot.h>
+#include <lib/pci-tree.h>
+
+#define NB_AHCI_DRIVER_NAME ("@sata")
+
+/// BUGS: 0
+/// @brief AHCI support for PowerPC.
+
+/// @brief AHCI HBA port.
+typedef struct cb_hba_port {
+  uint32_t clb;            // 0x00, command list base address, 1K-byte aligned
+  uint32_t clbu;           // 0x04, command list base address upper 32 bits
+  uint32_t fb;             // 0x08, FIS base address, 256-byte aligned
+  uint32_t fbu;            // 0x0C, FIS base address upper 32 bits
+  uint32_t is;             // 0x10, interrupt status
+  uint32_t ie;             // 0x14, interrupt enable
+  uint32_t cmd;            // 0x18, command and status
+  uint32_t reserved0;      // 0x1C, Reserved
+  uint32_t tfd;            // 0x20, task file data
+  uint32_t sig;            // 0x24, signature
+  uint32_t ssts;           // 0x28, SATA status (SCR0:SStatus)
+  uint32_t sctl;           // 0x2C, SATA control (SCR2:SControl)
+  uint32_t serr;           // 0x30, SATA error (SCR1:SError)
+  uint32_t sact;           // 0x34, SATA active (SCR3:SActive)
+  uint32_t ci;             // 0x38, command issue
+  uint32_t sntf;           // 0x20, SATA notification (SCR4:SNotification)
+  uint32_t fbs;            // 0x40, FIS-based switch control
+  uint32_t reserved1[11];  // 0x44 ~ 0x6F, Reserved
+  uint32_t vendor[4];      // 0x70 ~ 0x7F, vendor specific
+} cb_hba_port_t;
+
+/// @brief Check if port is active.
+/// @param port host bus address port.
+/// @return whether sact is active or not.
+static boolean cb_hba_port_active(volatile cb_hba_port_t* port) {
+  if (!port) return false;
+
+  return port->sact;
+}
+
+/// @brief Start HBA command processor.
+/// @param port host bus address port.
+/// @return whether it was successful or not.
+static boolean cb_hba_start_cmd(volatile cb_hba_port_t* port) {
+  if (!port) return false;
+
+  size_t timeout = 1000000;
+
+  while ((port->cmd & 0x8000)) {
+    if (!timeout) return false;
+
+    --timeout;
+  }
+
+  port->cmd |= 0x0001;
+  port->cmd |= 0x0010;
+
+  return true;
+}
+
+/// @brief Stop HBA command from processing.
+/// @param port host bus address port.
+/// @return whether it was successful or not.
+static boolean cb_hba_stop_cmd(volatile cb_hba_port_t* port) {
+  if (!port) return false;
+
+  port->cmd &= ~0x0001;
+  port->cmd &= ~0x0010;
+
+  while (yes) {
+    if ((port->cmd & 0x8000)) continue;
+
+    if ((port->cmd & 0x4000)) continue;
+
+    break;
+  }
+
+  return true;
+}
diff --git a/src/hal/neboot-flash-driver.c b/src/hal/neboot-flash-driver.c
new file mode 100644
index 0000000..d1b0907
--- /dev/null
+++ b/src/hal/neboot-flash-driver.c
@@ -0,0 +1,10 @@
+/* -------------------------------------------
+
+Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+
+------------------------------------------- */
+
+#include <lib/boot.h>
+#include <lib/mp-bit.h>
+#include <lib/partition-map.h>
+#include <lib/pci-tree.h>
diff --git a/src/neboot-bootnet.c b/src/neboot-bootnet.c
new file mode 100644
index 0000000..a547b35
--- /dev/null
+++ b/src/neboot-bootnet.c
@@ -0,0 +1,7 @@
+/* -------------------------------------------
+
+  Copyright (C) 2025, Amlal EL Mahrouss, all rights reserved.
+
+------------------------------------------- */
+
+#include <lib/bootnet.h>
diff --git a/src/neboot-cpu-api.c b/src/neboot-cpu-api.c
new file mode 100644
index 0000000..2491f15
--- /dev/null
+++ b/src/neboot-cpu-api.c
@@ -0,0 +1,20 @@
+/* -------------------------------------------
+
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+
+------------------------------------------- */
+
+#include <lib/boot.h>
+
+/// @brief Restarts the computer.
+/// @param none.
+void cb_restart_machine(void) {
+#ifdef __COMPILE_RISCV__
+  volatile uint32_t* brd_pwr = (volatile uint32_t*) 0x100000;
+  *brd_pwr                   = 0x7777;  // send reboot signal from DMA.
+
+  while (1) {
+    asm volatile("wfi");
+  }
+#endif
+}
diff --git a/src/neboot-cxx-abi.cc b/src/neboot-cxx-abi.cc
new file mode 100644
index 0000000..88b2a6a
--- /dev/null
+++ b/src/neboot-cxx-abi.cc
@@ -0,0 +1,77 @@
+/* -------------------------------------------
+
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+
+------------------------------------------- */
+
+#include <lib/cxx-abi.hpp>
+
+/// BUGS: 0
+
+extern "C" __SIZE_TYPE__ cb_put_string(const char* text);
+extern "C" void          cb_panic(const char* reason);
+
+extern "C" void __stack_chk_fail() {
+  cb_put_string("[stack-canary] Buffer overflow detected, halting...\n");
+  cb_panic("stack_canary_fail");
+}
+
+void* __dso_handle;
+
+extern "C" __SIZE_TYPE__ cb_put_string(const char* text);
+extern "C" void          cb_panic(const char* reason);
+
+atexit_func_entry_t __atexit_funcs[DSO_MAX_OBJECTS];
+uarch_t             __atexit_func_count;
+
+extern "C" void __cxa_pure_virtual() {
+  cb_put_string("[__cxa_pure_virtual] Placeholder\n");
+}
+
+extern "C" int __cxa_atexit(void (*f)(void*), void* arg, void* dso) {
+  if (__atexit_func_count >= DSO_MAX_OBJECTS) return -1;
+
+  __atexit_funcs[__atexit_func_count].destructor_func = f;
+  __atexit_funcs[__atexit_func_count].obj_ptr         = arg;
+  __atexit_funcs[__atexit_func_count].dso_handle      = dso;
+
+  __atexit_func_count++;
+
+  return 0;
+}
+
+extern "C" void __cxa_finalize(void* f) {
+  uarch_t i = __atexit_func_count;
+  if (!f) {
+    while (i--) {
+      if (__atexit_funcs[i].destructor_func) {
+        (*__atexit_funcs[i].destructor_func)(__atexit_funcs[i].obj_ptr);
+      };
+    }
+
+    return;
+  }
+
+  while (i--) {
+    if (__atexit_funcs[i].destructor_func) {
+      (*__atexit_funcs[i].destructor_func)(__atexit_funcs[i].obj_ptr);
+      __atexit_funcs[i].destructor_func = 0;
+    };
+  }
+}
+
+namespace cxxabiv1 {
+extern "C" int __cxa_guard_acquire(__guard* g) {
+  (void) g;
+  return 0;
+}
+
+extern "C" int __cxa_guard_release(__guard* g) {
+  *(char*) g = 1;
+  return 0;
+}
+
+extern "C" void __cxa_guard_abort(__guard* g) {
+  (void) g;
+}
+}  // namespace cxxabiv1
diff --git a/src/neboot-partition-map-parse.c b/src/neboot-partition-map-parse.c
new file mode 100644
index 0000000..7d8f80f
--- /dev/null
+++ b/src/neboot-partition-map-parse.c
@@ -0,0 +1,42 @@
+/* -------------------------------------------
+
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+
+------------------------------------------- */
+
+#include <lib/partition-map.h>
+
+bool cb_parse_partition_block_data_at(voidptr_t blob, size_t blob_sz, size_t index, size_t* end_lba,
+                                      size_t* start_lba, size_t* sector_sz) {
+  if (!start_lba || !end_lba || !blob || !blob_sz || !sector_sz ||
+      (sizeof(part_block_t) * index) > blob_sz)
+    return false;
+
+  part_block_t* block = (part_block_t*) (blob + (sizeof(part_block_t) * index));
+
+  if (block->version != EPM_REVISION || block->num_blocks < 1 || block->num_blocks > EPM_MAX_BLKS ||
+      strcmp(block->magic, EPM_MAGIC) > 0 || block->lba_end == 0 || block->lba_start == 0) {
+    return false;
+  }
+
+  *end_lba   = block->lba_end;
+  *start_lba = block->lba_start;
+  *sector_sz = block->sector_sz;
+
+  return true;
+}
+
+part_block_t* cb_parse_partition_block_at(voidptr_t blob, size_t blob_sz, size_t index) {
+  if (!blob || !blob_sz || (sizeof(part_block_t) * index) > blob_sz) return nil;
+
+  part_block_t* block = (part_block_t*) (blob + (sizeof(part_block_t) * index));
+
+  cb_put_string(block->magic);
+
+  if (block->version != EPM_REVISION || block->num_blocks < 1 || block->num_blocks > EPM_MAX_BLKS ||
+      strcmp(block->magic, EPM_MAGIC) > 0 || block->lba_end == 0 || block->lba_start == 0) {
+    return nil;
+  }
+
+  return block;
+}
\ No newline at end of file
diff --git a/src/neboot-partition-map.c b/src/neboot-partition-map.c
new file mode 100644
index 0000000..c13907c
--- /dev/null
+++ b/src/neboot-partition-map.c
@@ -0,0 +1,30 @@
+/* -------------------------------------------
+
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+
+------------------------------------------- */
+
+#include <lib/partition-map.h>
+#include <lib/string.h>
+
+// include this for documentation.
+
+#define NB_FILESYSTEM_COUNT 4
+#define NB_FILESYSTEM_LIST \
+  { "NeFS", "HeFS", "FAT32", "ext4" }
+
+/// @brief check if filesystem is supported by NeBoot.
+/// @param fs the filesystem magic, as provided by EPM.
+boolean cb_filesystem_exists(caddr_t fs, size_t len) {
+  if (fs == nil || *fs == 0) return no;
+
+  char* fs_list[] = NB_FILESYSTEM_LIST;
+
+  for (size_t fs_index = 0; fs_index < NB_FILESYSTEM_COUNT; fs_index++) {
+    if (strncmp(fs_list[fs_index], fs, strlen(fs_list[fs_index])) == 0) {
+      return yes;
+    }
+  }
+
+  return no;
+}
diff --git a/src/neboot-pci-tree.c b/src/neboot-pci-tree.c
new file mode 100644
index 0000000..a506323
--- /dev/null
+++ b/src/neboot-pci-tree.c
@@ -0,0 +1,96 @@
+/* -------------------------------------------
+
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+
+------------------------------------------- */
+
+/**
+ * @file neboot-pci-tree.c
+ * @author Amlal EL Mahrouss (amlal@nekernel.org)
+ * @brief PCI tree implementation.
+ * @version 0.1
+ * @date 2024-01-22
+ *
+ * @copyright Copyright (c) 2024 Amlal EL Mahrouss
+ *
+ */
+
+#include <lib/pci-tree.h>
+#include <lib/string.h>
+
+/// BUGS: 0
+
+/// Standard Root table (Mahrouss Table)
+#define NB_PCI_ROOT_NAME "/pci-tree/@/"
+
+static struct hw_cb_pci_tree* cb_base_tree   = nil;
+static struct hw_cb_pci_tree* cb_latest_tree = nil;
+static struct hw_cb_pci_tree* cb_last_tree   = nil;
+
+/// \brief Init the PCI device tree structure.
+/// \return if it already exists -> false
+/// Otherwise true.
+boolean cb_pci_init_tree(void) {
+  cb_base_tree = (struct hw_cb_pci_tree*) (NB_PCI_TREE_BASE);
+
+  // huh? anyway let's ignore it then.
+  if (cb_base_tree->d_magic != NB_PCI_DEV_MAGIC) {
+    cb_base_tree->d_magic = NB_PCI_DEV_MAGIC;
+
+    memncpy(cb_base_tree->d_name, NB_PCI_ROOT_NAME, strlen(NB_PCI_ROOT_NAME));
+
+    cb_base_tree->d_next_sibling = 0;
+    cb_base_tree->d_off_props    = 0;
+    cb_base_tree->d_sz_struct    = 0;
+    cb_base_tree->d_sz_props     = 0;
+    cb_base_tree->d_off_struct   = 0;
+    cb_base_tree->d_version      = NB_PCI_VERSION;
+
+    cb_base_tree->d_next_sibling = (cb_pci_num_t) (cb_base_tree + sizeof(struct hw_cb_pci_tree));
+    cb_base_tree->d_first_node   = (cb_pci_num_t) cb_base_tree;
+
+    cb_put_string(">> Append root device: " NB_PCI_ROOT_NAME "\r\n");
+  }
+
+  cb_latest_tree = cb_base_tree;
+
+  return yes;
+}
+
+/// \brief Adds a new device to the tree.
+/// \param name the device name.
+/// \param struct_ptr the struct containing the device.
+/// \param struct_sz the structure size.
+boolean cb_pci_append_tree(const caddr_t name, cb_pci_num_t struct_ptr, cb_pci_num_t struct_sz) {
+  if (!name || *name == 0 || cb_latest_tree == nil) return no;
+
+  struct hw_cb_pci_tree* cb_pci_tree = (struct hw_cb_pci_tree*) (cb_latest_tree);
+
+  while (cb_pci_tree->d_magic == NB_PCI_DEV_MAGIC) {
+    if (strcmp(cb_pci_tree->d_name, name) == 0) return no;
+
+    cb_pci_tree = (struct hw_cb_pci_tree*) (cb_pci_tree + sizeof(struct hw_cb_pci_tree));
+  }
+
+  cb_pci_tree->d_magic = NB_PCI_DEV_MAGIC;
+
+  memncpy(cb_pci_tree->d_name, name, strlen(name));
+
+  cb_pci_tree->d_off_struct = struct_ptr;
+  cb_pci_tree->d_sz_struct  = struct_sz;
+  cb_pci_tree->d_off_props  = 0;
+  cb_pci_tree->d_sz_props   = 0;
+  cb_pci_tree->d_version    = NB_PCI_VERSION;
+
+  cb_pci_tree->d_next_sibling = (cb_pci_num_t) (cb_pci_tree + sizeof(struct hw_cb_pci_tree));
+  cb_pci_tree->d_first_node   = (cb_pci_num_t) cb_latest_tree;
+
+  cb_latest_tree = cb_pci_tree;
+  cb_last_tree   = cb_pci_tree;
+
+  cb_put_string(">> Append device: ");
+  cb_put_string(name);
+  cb_put_string("\r\n");
+
+  return yes;
+}
diff --git a/src/neboot-print-name.c b/src/neboot-print-name.c
new file mode 100644
index 0000000..90fe104
--- /dev/null
+++ b/src/neboot-print-name.c
@@ -0,0 +1,27 @@
+/* -------------------------------------------
+
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+
+------------------------------------------- */
+
+#include <lib/boot.h>
+
+/// @brief Print firmware name.
+/// @param
+void cb_print_name(void) {
+#ifdef __COMPILE_POWERPC__
+  cb_put_string(">> NeBoot for POWERPC.\r\n");
+#endif  // __COMPILE_POWERPC__
+
+#ifdef __COMPILE_ARM64__
+  cb_put_string(">> NeBoot for ARM64.\r\n");
+#endif  // __COMPILE_POWERPC__
+
+#ifdef __COMPILE_AMD64__
+  cb_put_string(">> NeBoot for AMD64.\r\n");
+#endif  // __COMPILE_POWERPC__
+
+#ifdef __COMPILE_RISCV__
+  cb_put_string(">> NeBoot for RISC-V.\r\n");
+#endif  // __COMPILE_POWERPC__
+}
diff --git a/src/neboot-start.c b/src/neboot-start.c
new file mode 100644
index 0000000..8384791
--- /dev/null
+++ b/src/neboot-start.c
@@ -0,0 +1,155 @@
+/* -------------------------------------------
+
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+
+------------------------------------------- */
+
+#include <lib/boot.h>
+#include <lib/mp-bit.h>
+#include <lib/partition-map.h>
+#include <lib/pci-tree.h>
+
+/// BUGS: 0
+
+/////////////////////////////////////////////////////////////////////////////////////////
+
+// @name start.c //
+
+// @brief Start file // This is where the firmware starts it's initialization //
+// code. //
+
+// @author Amlal EL Mahrouss //
+
+/////////////////////////////////////////////////////////////////////////////////////////
+
+extern void cb_start_context(uintptr_t);
+extern void cb_start_rom(void);
+
+extern int cb_boot_processor_ready;
+
+/// @brief hardware thread counter (rv64 only)
+#ifdef __COMPILE_RISCV__
+uint64_t __cb_hart_counter = 0UL;
+#endif
+
+/// @brief Start executing the firmware.
+/// @param
+void cb_start_exec(void) {
+#ifndef __COMPILE_RISCV__
+  static uint64_t __cb_hart_counter = 0UL;
+#endif
+
+  ++__cb_hart_counter;
+
+  uintptr_t hart = __cb_hart_counter;
+
+  // let the hart 0 init our stuff.
+  if (hart == 0) {
+    cb_put_string("CB> Welcome to NeBoot, (c) Amlal EL Mahrouss. Built the ");
+    cb_put_string(__DATE__);
+    cb_put_string("\r\r\n");
+
+#ifdef __COMPILE_POWERPC__
+    cb_put_string("CB> CPU: PowerPC 64-bit Based SoC.\r\r\n");
+#endif  // __COMPILE_POWERPC__
+
+#ifdef __COMPILE_AMD64__
+    cb_put_string("CB> CPU: x64 Based SoC.\r\r\n");
+#endif  // __COMPILE_AMD64__
+
+#ifdef __COMPILE_ARM64__
+    cb_put_string("CB> CPU: AArch64 Based SoC.\r\r\n");
+#endif  // __COMPILE_ARM64__
+
+#ifdef __COMPILE_ARM32__
+    cb_put_string("CB> CPU: AArch32 Based SoC.\r\r\n");
+#endif  // __COMPILE_ARM64__
+
+#ifdef __COMPILE_RISCV__
+    cb_put_string("CB> CPU: RV64 Based SoC.\r\r\n");
+#endif  // __COMPILE_RISCV__
+  }
+
+  /// @brief Boots here if LX header matches what we except.
+
+  volatile struct cb_boot_header* boot_hdr = (volatile struct cb_boot_header*) (NB_FLASH_BASE_ADDR);
+
+  /**
+    boot if:
+      - ident matches.
+      - version matches.
+  */
+
+  if (boot_hdr->h_mag[0] == NB_BOOT_MAG_0 && boot_hdr->h_mag[1] == NB_BOOT_MAG_1) {
+    uint32_t rev = boot_hdr->h_revision;
+
+#ifdef __aarch64__
+    rev = __builtin_bswap32(rev);
+#endif
+
+    if (rev != NB_BOOT_VER) {
+      if (hart == 0) {
+        cb_put_string("CB> Can't Boot the StageTwo, LX invalid signature. (CB0003)\r\n");
+      }
+    } else {
+      if (hart == 0) {
+        cb_pci_append_tree("@stage2-lx", (cb_pci_num_t) boot_hdr, sizeof(struct cb_boot_header));
+
+        cb_put_string("CB> Executing StageTwo: ");
+        cb_put_string((const char*) boot_hdr->h_name);
+        cb_put_char('\r');
+        cb_put_char('\n');
+
+        // printf("CB> address: %x\n", boot_hdr->h_start_address);
+      }
+
+      if (boot_hdr->h_start_address != 0) {
+        cb_boot_processor_ready = 1;
+        cb_start_context(boot_hdr->h_start_address);
+      }
+
+      cb_put_string("CB> StageTwo has returned? (CB0002)\r\n");
+    }
+  } else {
+    cb_put_string("CB> Trying EPM partition...\r\n");
+
+    part_block_t* blk = cb_parse_partition_block_at((voidptr_t) NB_BOOT_ADDR, EPM_PART_BLK_SZ, 0);
+
+    if (blk) {
+      cb_pci_append_tree("@stage2-epm", (cb_pci_num_t) blk, sizeof(part_block_t) * blk->num_blocks);
+
+      size_t indx = 0;
+      size_t end_lba, start_lba, sector_sz;
+
+      while (indx < blk->num_blocks) {
+        if (cb_parse_partition_block_data_at(blk, EPM_PART_BLK_SZ * blk->num_blocks, indx, &end_lba,
+                                             &start_lba, &sector_sz) == no) {
+          ++indx;
+          continue;
+        }
+
+        cb_boot_processor_ready = 1;
+        cb_start_context((uintptr_t) (voidptr_t) blk + start_lba);
+
+        if (hart == 1) {
+          cb_put_string("CB> Can't boot to StageTwo. (CB0001)\r\n");
+        }
+      }
+    }
+
+    if (hart == 1) {
+      cb_put_string(
+          "CB> Can't boot to StageTwo via EPM, no bootable partition blocks found. (CB0001)\r\n");
+    }
+  }
+
+  /// end of TODO
+
+  if (hart > 1) {
+    while (yes) {
+      if (__cb_hart_counter == 0) {
+        cb_restart_machine();
+      }
+    }
+  }
+}
diff --git a/src/neboot-string.c b/src/neboot-string.c
new file mode 100644
index 0000000..0c249a4
--- /dev/null
+++ b/src/neboot-string.c
@@ -0,0 +1,153 @@
+/* -------------------------------------------
+
+  Copyright (C) 2024, Amlal EL Mahrouss, all rights reserved.
+
+------------------------------------------- */
+
+/**
+ * @file neboot-string.c
+ * @author Amlal EL Mahrouss (amlal@nekernel.org)
+ * @brief string library.
+ * @version 0.1
+ * @date 2024-01-16
+ *
+ * @copyright Copyright (c) 2024 Amlal EL Mahrouss
+ *
+ */
+
+#include <lib/string.h>
+
+/// BUGS: 0
+
+size_t strncmp(const char* src, const char* cmp, size_t size) {
+  if (src == nil) return 0;
+
+  int32_t counter = 0;
+
+  for (size_t index = 0; index < size; ++index) {
+    if (src[index] != cmp[index]) ++counter;
+  }
+
+  return counter;
+}
+
+void* memset(void* ptr, const char value, size_t len) {
+  if (ptr == nil) return nil;
+
+  char* start = ptr;
+
+  while (len) {
+    *start = value;
+    ++start;
+
+    --len;
+  }
+
+  return (void*) start;
+}
+
+void* memmove(void* dest, const void* src, size_t len) {
+  memncpy(dest, src, len);
+  return dest;
+}
+
+size_t memcpy(void* dst, const void* src) {
+  if (src == nil || dst == nil) return 0;
+
+  const char* src_chr = src;
+  char*       dst_chr = dst;
+  size_t      index   = 0;
+  size_t      len     = strlen(src);
+
+  while (index < len) {
+    dst_chr[index] = src_chr[index];
+    ++index;
+  }
+
+  return 0;
+}
+
+/* @brief unoptimized memcpy, TODO: use isa specific memcpy. */
+size_t memncpy(void* dst, const void* src, size_t len) {
+#if __OL == 3 && defined(__riscv)
+  riscv_memncpy(dst, src, len);
+#else
+
+  if (src == nil || dst == nil) return 0;
+
+  const char* src_chr = src;
+  char*       dst_chr = dst;
+  size_t      index   = 0;
+
+  while (index < len) {
+    dst_chr[index] = src_chr[index];
+    ++index;
+  }
+
+  return 0;
+#endif
+}
+
+size_t strlen(const char* str) {
+  if (*str == 0) return 0;
+
+  size_t len = 0;
+  while (str[len] != '\0') ++len;
+
+  return len;
+}
+
+size_t strnlen(const char* str, size_t len) {
+  size_t cnt = 0;
+
+  while (len > cnt) {
+    ++cnt;
+
+    if (str[cnt] == '\0') return (size_t) -1;
+  }
+
+  return len;
+}
+
+void strreverse(char* s) {
+  if (s == nil) return;
+  if (*s == '\0') return;
+
+  char *first, *last, temp;
+
+  first = s;
+  last  = s + strlen(s) - 1;
+
+  while (first != last) {
+    temp       = *first;
+    *(first++) = *last;
+    *(last--)  = temp;
+  }
+}
+
+char* strchr(char* str, const char chr) {
+  while (*str != chr) {
+    ++str;
+
+    if (*str == 0) return nil;
+  }
+
+  return str;
+}
+
+/// @brief Compare two strings.
+/// @param src source string
+/// @param cmp string to compare.
+/// @return
+size_t strcmp(caddr_t src, caddr_t cmp) {
+  if (src == null || *src == 0) return 1;
+  if (cmp == null || *cmp == 0) return 1;
+
+  int32_t counter = 0;
+
+  for (size_t index = 0; src[index] != 0; ++index) {
+    if (cmp[index] != src[index]) ++counter;
+  }
+
+  return counter;
+}
diff --git a/src/ppc64/makefile b/src/ppc64/makefile
index 8adb03f..d046098 100644
--- a/src/ppc64/makefile
+++ b/src/ppc64/makefile
@@ -1,7 +1,7 @@
  #
  #	========================================================
  #
- #	CoreBoot
+ #	NeBoot
  # 	Date Added: 08/11/2023
  # 	Copyright 2024, Amlal El Mahrouss, all rights reserved.
  #
@@ -35,7 +35,7 @@ IMG_CMD=qemu-img create -f qcow2 epm.img 256M
 
 .PHONY: all
 all: firmware-link
-	@echo "[CoreBoot] build done."
+	@echo "[NeBoot] build done."
 
 .PHONY: firmware-link
 firmware-link: firmware-compile
diff --git a/src/ppc64/ppc64-boot.S b/src/ppc64/ppc64-boot.S
index 28d1865..de366fc 100644
--- a/src/ppc64/ppc64-boot.S
+++ b/src/ppc64/ppc64-boot.S
@@ -29,11 +29,11 @@ cb_reset_vector:
 .global cb_start_context
 .global cb_boot_processor_ready
 
-.equ CB_BOOT_ADDR, 0x1030000
+.equ NB_BOOT_ADDR, 0x1030000
 
 cb_start_rom:
-	lis 3, CB_BOOT_ADDR@h
-	addi 3, 3, CB_BOOT_ADDR@l
+	lis 3, NB_BOOT_ADDR@h
+	addi 3, 3, NB_BOOT_ADDR@l
 
 	blr
 
diff --git a/src/ppc64/ppc64-hal.c b/src/ppc64/ppc64-hal.c
index 74d18c4..993e5be 100644
--- a/src/ppc64/ppc64-hal.c
+++ b/src/ppc64/ppc64-hal.c
@@ -41,7 +41,7 @@ void cb_set_tlb(uint8_t tlb, uint32_t epn, uint64_t rpn, uint8_t perms, uint8_t
 void cb_init_hw(void) {
   /// amlal:
   /// map VGA framebuffer
-  cb_set_tlb(0, CB_FRAMEBUFFER_ADDR, /* v_addr, 0x0000A0000 */
+  cb_set_tlb(0, NB_FRAMEBUFFER_ADDR, /* v_addr, 0x0000A0000 */
              0x0000A000,             /* p_addr. 0x0000A0000  */
              MAS3_SW | MAS3_SR,      /* perm  type=TLB_MAP_IO */
              MAS2_I | MAS2_G,        /* wimge type=TLB_MAP_IO */
@@ -52,7 +52,7 @@ void cb_init_hw(void) {
 
   // map ccsrbar and uart.
   // at start we execute from esel = 0, so chose something else..
-  cb_set_tlb(1, CB_UART_BASE,   /* v_addr   0xe0000000 see  qemu-ppce500.h */
+  cb_set_tlb(1, NB_UART_BASE,   /* v_addr   0xe0000000 see  qemu-ppce500.h */
              0xfe0000000,       /* p_addr. 0xfe0000000  */
              MAS3_SW | MAS3_SR, /* perm  type=TLB_MAP_IO */
              MAS2_I | MAS2_G,   /* wimge type=TLB_MAP_IO */
@@ -63,7 +63,7 @@ void cb_init_hw(void) {
 
   /// amlal:
   /// map pci base for kernel
-  cb_set_tlb(0, CB_BASE_ADDRESS, /* v_addr, 0xFE008000 */
+  cb_set_tlb(0, NB_BASE_ADDRESS, /* v_addr, 0xFE008000 */
              0xFE0008000,        /* p_addr. 0xfe0000000  */
              MAS3_SW | MAS3_SR,  /* perm  type=TLB_MAP_IO */
              MAS2_I | MAS2_G,    /* wimge type=TLB_MAP_IO */
@@ -74,10 +74,10 @@ void cb_init_hw(void) {
 
   cb_pci_init_tree();
 
-  cb_pci_append_tree("@fb", CB_FRAMEBUFFER_ADDR, 0x0);
+  cb_pci_append_tree("@fb", NB_FRAMEBUFFER_ADDR, 0x0);
   cb_pci_append_tree("@mbci", 0x0, 0x0);  // did not found a MBCI base for now...
-  cb_pci_append_tree("@serial", CB_UART_BASE, 0);
-  cb_pci_append_tree("@pci", CB_BASE_ADDRESS, 0x0);
+  cb_pci_append_tree("@serial", NB_UART_BASE, 0);
+  cb_pci_append_tree("@pci", NB_BASE_ADDRESS, 0x0);
 
   cb_flush_tlb();
 }
diff --git a/src/ppc64/ppc64-uart.c b/src/ppc64/ppc64-uart.c
index b3b5717..9830342 100644
--- a/src/ppc64/ppc64-uart.c
+++ b/src/ppc64/ppc64-uart.c
@@ -9,10 +9,10 @@
 
 /// BUGS: 0
 
-#define CB_NS16550_COM1 (CB_UART_BASE + 0x4500)
-#define CB_NS16550_COM2 (CB_UART_BASE + 0x4600)
+#define NB_NS16550_COM1 (NB_UART_BASE + 0x4500)
+#define NB_NS16550_COM2 (NB_UART_BASE + 0x4600)
 
-volatile ascii_char_t* const UART0DR = (ascii_char_t*) CB_NS16550_COM1;
+volatile ascii_char_t* const UART0DR = (ascii_char_t*) NB_NS16550_COM1;
 
 /* this file handles the UART */
 
diff --git a/src/rv64/ci.make b/src/rv64/ci.make
index 757d6c1..c9936dd 100644
--- a/src/rv64/ci.make
+++ b/src/rv64/ci.make
@@ -1,7 +1,7 @@
  #
  #	========================================================
  #
- #	CoreBoot
+ #	NeBoot
  # 	Date Added: 08/11/2023
  # 	Copyright 2024, Amlal El Mahrouss, all rights reserved.
  #
@@ -24,7 +24,7 @@ EMU=qemu-system-riscv64 -m 4G -smp 2 -machine virt -bios $(FIRMWARE) -d int -dev
 
 .PHONY: all
 all: firmware-link
-	@echo "[CoreBoot] Done."
+	@echo "[NeBoot] Done."
 
 # link (make firmware)
 .PHONY: firmware-link
diff --git a/src/rv64/makefile b/src/rv64/makefile
index 757d6c1..c9936dd 100644
--- a/src/rv64/makefile
+++ b/src/rv64/makefile
@@ -1,7 +1,7 @@
  #
  #	========================================================
  #
- #	CoreBoot
+ #	NeBoot
  # 	Date Added: 08/11/2023
  # 	Copyright 2024, Amlal El Mahrouss, all rights reserved.
  #
@@ -24,7 +24,7 @@ EMU=qemu-system-riscv64 -m 4G -smp 2 -machine virt -bios $(FIRMWARE) -d int -dev
 
 .PHONY: all
 all: firmware-link
-	@echo "[CoreBoot] Done."
+	@echo "[NeBoot] Done."
 
 # link (make firmware)
 .PHONY: firmware-link
diff --git a/src/rv64/rv64-api.s b/src/rv64/rv64-api.s
index 8fe29e1..b4a0749 100644
--- a/src/rv64/rv64-api.s
+++ b/src/rv64/rv64-api.s
@@ -1,6 +1,6 @@
 # ====================================
 #
-#   Amlal EL Mahrouss CoreBoot
+#   Amlal EL Mahrouss NeBoot
 #   (c) Amlal EL Mahrouss all rights reserved.
 #
 #   Purpose: Assembler API for RISC-V
diff --git a/src/rv64/rv64-boot.s b/src/rv64/rv64-boot.s
index fb95d55..a9afd02 100644
--- a/src/rv64/rv64-boot.s
+++ b/src/rv64/rv64-boot.s
@@ -1,7 +1,7 @@
 /*
  *	========================================================
  *
- *	CoreBoot
+ *	NeBoot
  * 	Copyright 2024, Amlal EL Mahrouss, all rights reserved.
  *
  *  	Purpose: Startup code for RISC-V.
@@ -81,10 +81,10 @@ cb_start_context:
 	add ra, zero, a1
 	mret
 
-.equ CB_BOOT_ADDR, 0x80020000
+.equ NB_BOOT_ADDR, 0x80020000
 
 cb_start_rom:
-	li x5, CB_BOOT_ADDR
+	li x5, NB_BOOT_ADDR
 	mv ra, zero
 	add ra, zero, t0
 	mret
diff --git a/src/rv64/rv64-uart.c b/src/rv64/rv64-uart.c
index 3f604fe..22b0793 100644
--- a/src/rv64/rv64-uart.c
+++ b/src/rv64/rv64-uart.c
@@ -11,10 +11,10 @@
 
 /* this file handles the UART */
 
-static uint8_t* cb_uart_ptr = (uint8_t*) CB_UART_BASE;
+static uint8_t* cb_uart_ptr = (uint8_t*) NB_UART_BASE;
 
 utf_char_t cb_get_char(void) {
-  uintptr_t ptr = CB_UART_BASE;
+  uintptr_t ptr = NB_UART_BASE;
 
   while (!(*(((volatile uint8_t*) ptr) + 0x05) & 0x01))
     ;
-- 
cgit v1.2.3


From 6318c40aa018427322b8f14eb4059c4df985c0d7 Mon Sep 17 00:00:00 2001
From: Amlal <amlal@nekernel.org>
Date: Sat, 9 Aug 2025 19:56:10 +0200
Subject: feat: ran format command

Signed-off-by: Amlal <amlal@nekernel.org>
---
 lib/bootnet.h          |   2 +-
 lib/ppc64/mmu.h        |  12 ++---
 lib/ppc64/processor.h  | 128 ++++++++++++++++++++++++-------------------------
 src/ppc64/ppc64-uart.c |   3 +-
 src/rv64/rv64-uart.c   |   3 +-
 5 files changed, 73 insertions(+), 75 deletions(-)

(limited to 'src')

diff --git a/lib/bootnet.h b/lib/bootnet.h
index 2176c04..8363c39 100644
--- a/lib/bootnet.h
+++ b/lib/bootnet.h
@@ -26,7 +26,7 @@ typedef struct bootnet_inet_header {
   ascii_char_t m_patch_name[BOOTNET_NAME_LEN];  /// example: ColdChoco
   int32_t      m_length;                        /// The patch's length.
   ascii_char_t m_target[BOOTNET_NAME_LEN];      /// The target file.
-  uint8_t      m_implies_rom;               /// does it imply reprogramming?
+  uint8_t      m_implies_rom;                   /// does it imply reprogramming?
   uint8_t      m_preflight;  /// Do we just check if this endpoint exists/is valid?
   uint8_t      m_blob[];
 } bootnet_inet_header;
diff --git a/lib/ppc64/mmu.h b/lib/ppc64/mmu.h
index cbfbf47..1953ab5 100644
--- a/lib/ppc64/mmu.h
+++ b/lib/ppc64/mmu.h
@@ -402,7 +402,7 @@ extern void print_bats(void);
 #define MAS0_TLBSEL(x) (((x) << 28) & MAS0_TLBSEL_MSK)
 #define MAS0_ESEL_MSK 0x0FFF0000
 #define MAS0_ESEL(x) (((x) << 16) & MAS0_ESEL_MSK)
-#define MAS0_NV(x) ((x) &0x00000FFF)
+#define MAS0_NV(x) ((x) & 0x00000FFF)
 
 #define MAS1_VALID 0x80000000
 #define MAS1_IPROT 0x40000000
@@ -454,8 +454,8 @@ extern void print_bats(void);
 #define FSL_BOOKE_MAS1(v, iprot, tid, ts, tsize)                                   \
   ((((v) << 31) & MAS1_VALID) | (((iprot) << 30) & MAS1_IPROT) | (MAS1_TID(tid)) | \
    (((ts) << 12) & MAS1_TS) | (MAS1_TSIZE(tsize)))
-#define FSL_BOOKE_MAS2(epn, wimge) (((epn) &MAS3_RPN) | (wimge))
-#define FSL_BOOKE_MAS3(rpn, user, perms) (((rpn) &MAS3_RPN) | (user) | (perms))
+#define FSL_BOOKE_MAS2(epn, wimge) (((epn) & MAS3_RPN) | (wimge))
+#define FSL_BOOKE_MAS3(rpn, user, perms) (((rpn) & MAS3_RPN) | (user) | (perms))
 #define FSL_BOOKE_MAS7(rpn) (((uint64_t) (rpn)) >> 32)
 
 #define BOOKE_PAGESZ_1K 0
@@ -621,10 +621,10 @@ extern int                    num_tlb_entries;
 
 /* Some handy macros */
 
-#define EPN(e) ((e) &0xfffffc00)
+#define EPN(e) ((e) & 0xfffffc00)
 #define TLB0(epn, sz) ((EPN((epn)) | (sz) | TLB_VALID))
-#define TLB1(rpn, erpn) (((rpn) &0xfffffc00) | (erpn))
-#define TLB2(a) ((a) &0x00000fbf)
+#define TLB1(rpn, erpn) (((rpn) & 0xfffffc00) | (erpn))
+#define TLB2(a) ((a) & 0x00000fbf)
 
 #define tlbtab_start \
   mflr r1;           \
diff --git a/lib/ppc64/processor.h b/lib/ppc64/processor.h
index 3e6e04d..8ce9606 100644
--- a/lib/ppc64/processor.h
+++ b/lib/ppc64/processor.h
@@ -143,36 +143,36 @@ struct pt_regs {
 #define SPRN_DBCR 0x3F2   /* Debug Control Regsiter */
 #define DBCR_EDM 0x80000000
 #define DBCR_IDM 0x40000000
-#define DBCR_RST(x) (((x) &0x3) << 28)
+#define DBCR_RST(x) (((x) & 0x3) << 28)
 #define DBCR_RST_NONE 0
 #define DBCR_RST_CORE 1
 #define DBCR_RST_CHIP 2
 #define DBCR_RST_SYSTEM 3
-#define DBCR_IC 0x08000000             /* Instruction Completion Debug Evnt */
-#define DBCR_BT 0x04000000             /* Branch Taken Debug Event */
-#define DBCR_EDE 0x02000000            /* Exception Debug Event */
-#define DBCR_TDE 0x01000000            /* TRAP Debug Event */
-#define DBCR_FER 0x00F80000            /* First Events Remaining Mask */
-#define DBCR_FT 0x00040000             /* Freeze Timers on Debug Event */
-#define DBCR_IA1 0x00020000            /* Instr. Addr. Compare 1 Enable */
-#define DBCR_IA2 0x00010000            /* Instr. Addr. Compare 2 Enable */
-#define DBCR_D1R 0x00008000            /* Data Addr. Compare 1 Read Enable */
-#define DBCR_D1W 0x00004000            /* Data Addr. Compare 1 Write Enable */
-#define DBCR_D1S(x) (((x) &0x3) << 12) /* Data Adrr. Compare 1 Size */
+#define DBCR_IC 0x08000000              /* Instruction Completion Debug Evnt */
+#define DBCR_BT 0x04000000              /* Branch Taken Debug Event */
+#define DBCR_EDE 0x02000000             /* Exception Debug Event */
+#define DBCR_TDE 0x01000000             /* TRAP Debug Event */
+#define DBCR_FER 0x00F80000             /* First Events Remaining Mask */
+#define DBCR_FT 0x00040000              /* Freeze Timers on Debug Event */
+#define DBCR_IA1 0x00020000             /* Instr. Addr. Compare 1 Enable */
+#define DBCR_IA2 0x00010000             /* Instr. Addr. Compare 2 Enable */
+#define DBCR_D1R 0x00008000             /* Data Addr. Compare 1 Read Enable */
+#define DBCR_D1W 0x00004000             /* Data Addr. Compare 1 Write Enable */
+#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
 #define DAC_BYTE 0
 #define DAC_HALF 1
 #define DAC_WORD 2
 #define DAC_QUAD 3
-#define DBCR_D2R 0x00000800           /* Data Addr. Compare 2 Read Enable */
-#define DBCR_D2W 0x00000400           /* Data Addr. Compare 2 Write Enable */
-#define DBCR_D2S(x) (((x) &0x3) << 8) /* Data Addr. Compare 2 Size */
-#define DBCR_SBT 0x00000040           /* Second Branch Taken Debug Event */
-#define DBCR_SED 0x00000020           /* Second Exception Debug Event */
-#define DBCR_STD 0x00000010           /* Second Trap Debug Event */
-#define DBCR_SIA 0x00000008           /* Second IAC Enable */
-#define DBCR_SDA 0x00000004           /* Second DAC Enable */
-#define DBCR_JOI 0x00000002           /* JTAG Serial Outbound Int. Enable */
-#define DBCR_JII 0x00000001           /* JTAG Serial Inbound Int. Enable */
+#define DBCR_D2R 0x00000800            /* Data Addr. Compare 2 Read Enable */
+#define DBCR_D2W 0x00000400            /* Data Addr. Compare 2 Write Enable */
+#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
+#define DBCR_SBT 0x00000040            /* Second Branch Taken Debug Event */
+#define DBCR_SED 0x00000020            /* Second Exception Debug Event */
+#define DBCR_STD 0x00000010            /* Second Trap Debug Event */
+#define DBCR_SIA 0x00000008            /* Second IAC Enable */
+#define DBCR_SDA 0x00000004            /* Second DAC Enable */
+#define DBCR_JOI 0x00000002            /* JTAG Serial Outbound Int. Enable */
+#define DBCR_JII 0x00000001            /* JTAG Serial Inbound Int. Enable */
 #ifndef CONFIG_BOOKE
 #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
 #else
@@ -396,27 +396,27 @@ struct pt_regs {
 #ifdef CONFIG_E500MC
 #define TCR_WP(x) (((64 - x) & 0x3) << 30) | (((64 - x) & 0x3c) << 15) /* WDT Period 2^x clocks*/
 #else
-#define TCR_WP(x) (((x) &0x3) << 30)  /* WDT Period */
-#define WP_2_17 0                     /* 2^17 clocks */
-#define WP_2_21 1                     /* 2^21 clocks */
-#define WP_2_25 2                     /* 2^25 clocks */
-#define WP_2_29 3                     /* 2^29 clocks */
-#endif                                /* CONFIG_E500 */
-#define TCR_WRC(x) (((x) &0x3) << 28) /* WDT Reset Control */
-#define WRC_NONE 0                    /* No reset will occur */
-#define WRC_CORE 1                    /* Core reset will occur */
-#define WRC_CHIP 2                    /* Chip reset will occur */
-#define WRC_SYSTEM 3                  /* System reset will occur */
-#define TCR_WIE 0x08000000            /* WDT Interrupt Enable */
-#define TCR_PIE 0x04000000            /* PIT Interrupt Enable */
-#define TCR_FP(x) (((x) &0x3) << 24)  /* FIT Period */
-#define FP_2_9 0                      /* 2^9 clocks */
-#define FP_2_13 1                     /* 2^13 clocks */
-#define FP_2_17 2                     /* 2^17 clocks */
-#define FP_2_21 3                     /* 2^21 clocks */
-#define TCR_FIE 0x00800000            /* FIT Interrupt Enable */
-#define TCR_ARE 0x00400000            /* Auto Reload Enable */
-#define SPRN_THRM1 0x3FC              /* Thermal Management Register 1 */
+#define TCR_WP(x) (((x) & 0x3) << 30)  /* WDT Period */
+#define WP_2_17 0                      /* 2^17 clocks */
+#define WP_2_21 1                      /* 2^21 clocks */
+#define WP_2_25 2                      /* 2^25 clocks */
+#define WP_2_29 3                      /* 2^29 clocks */
+#endif                                 /* CONFIG_E500 */
+#define TCR_WRC(x) (((x) & 0x3) << 28) /* WDT Reset Control */
+#define WRC_NONE 0                     /* No reset will occur */
+#define WRC_CORE 1                     /* Core reset will occur */
+#define WRC_CHIP 2                     /* Chip reset will occur */
+#define WRC_SYSTEM 3                   /* System reset will occur */
+#define TCR_WIE 0x08000000             /* WDT Interrupt Enable */
+#define TCR_PIE 0x04000000             /* PIT Interrupt Enable */
+#define TCR_FP(x) (((x) & 0x3) << 24)  /* FIT Period */
+#define FP_2_9 0                       /* 2^9 clocks */
+#define FP_2_13 1                      /* 2^13 clocks */
+#define FP_2_17 2                      /* 2^17 clocks */
+#define FP_2_21 3                      /* 2^21 clocks */
+#define TCR_FIE 0x00800000             /* FIT Interrupt Enable */
+#define TCR_ARE 0x00400000             /* Auto Reload Enable */
+#define SPRN_THRM1 0x3FC               /* Thermal Management Register 1 */
 #define THRM1_TIN (1 << 0)
 #define THRM1_TIV (1 << 1)
 #define THRM1_THRES (0x7f << 2)
@@ -430,26 +430,26 @@ struct pt_regs {
 #ifndef CONFIG_BOOKE
 #define SPRN_TSR 0x3D8 /* Timer Status Register */
 #else
-#define SPRN_TSR 0x150                /* Book E Timer Status Register */
-#endif                                /* CONFIG_BOOKE */
-#define TSR_ENW 0x80000000            /* Enable Next Watchdog */
-#define TSR_WIS 0x40000000            /* WDT Interrupt Status */
-#define TSR_WRS(x) (((x) &0x3) << 28) /* WDT Reset Status */
-#define WRS_NONE 0                    /* No WDT reset occurred */
-#define WRS_CORE 1                    /* WDT forced core reset */
-#define WRS_CHIP 2                    /* WDT forced chip reset */
-#define WRS_SYSTEM 3                  /* WDT forced system reset */
-#define TSR_PIS 0x08000000            /* PIT Interrupt Status */
-#define TSR_FIS 0x04000000            /* FIT Interrupt Status */
-#define SPRN_UMMCR0 0x3A8             /* User Monitor Mode Control Register 0 */
-#define SPRN_UMMCR1 0x3AC             /* User Monitor Mode Control Register 0 */
-#define SPRN_UPMC1 0x3A9              /* User Performance Counter Register 1 */
-#define SPRN_UPMC2 0x3AA              /* User Performance Counter Register 2 */
-#define SPRN_UPMC3 0x3AD              /* User Performance Counter Register 3 */
-#define SPRN_UPMC4 0x3AE              /* User Performance Counter Register 4 */
-#define SPRN_USIA 0x3AB               /* User Sampled Instruction Address Register */
-#define SPRN_XER 0x001                /* Fixed Point Exception Register */
-#define SPRN_ZPR 0x3B0                /* Zone Protection Register */
+#define SPRN_TSR 0x150                 /* Book E Timer Status Register */
+#endif                                 /* CONFIG_BOOKE */
+#define TSR_ENW 0x80000000             /* Enable Next Watchdog */
+#define TSR_WIS 0x40000000             /* WDT Interrupt Status */
+#define TSR_WRS(x) (((x) & 0x3) << 28) /* WDT Reset Status */
+#define WRS_NONE 0                     /* No WDT reset occurred */
+#define WRS_CORE 1                     /* WDT forced core reset */
+#define WRS_CHIP 2                     /* WDT forced chip reset */
+#define WRS_SYSTEM 3                   /* WDT forced system reset */
+#define TSR_PIS 0x08000000             /* PIT Interrupt Status */
+#define TSR_FIS 0x04000000             /* FIT Interrupt Status */
+#define SPRN_UMMCR0 0x3A8              /* User Monitor Mode Control Register 0 */
+#define SPRN_UMMCR1 0x3AC              /* User Monitor Mode Control Register 0 */
+#define SPRN_UPMC1 0x3A9               /* User Performance Counter Register 1 */
+#define SPRN_UPMC2 0x3AA               /* User Performance Counter Register 2 */
+#define SPRN_UPMC3 0x3AD               /* User Performance Counter Register 3 */
+#define SPRN_UPMC4 0x3AE               /* User Performance Counter Register 4 */
+#define SPRN_USIA 0x3AB                /* User Sampled Instruction Address Register */
+#define SPRN_XER 0x001                 /* Fixed Point Exception Register */
+#define SPRN_ZPR 0x3B0                 /* Zone Protection Register */
 
 /* Book E definitions */
 #define SPRN_DECAR 0x036   /* Decrementer Auto Reload Register */
@@ -854,7 +854,7 @@ struct pt_regs {
 #define IOCR_PTD 0x00000400
 #define IOCR_ARE 0x00000080
 #define IOCR_DRC 0x00000020
-#define IOCR_RDM(x) (((x) &0x3) << 3)
+#define IOCR_RDM(x) (((x) & 0x3) << 3)
 #define IOCR_TCS 0x00000004
 #define IOCR_SCS 0x00000002
 #define IOCR_SPC 0x00000001
diff --git a/src/ppc64/ppc64-uart.c b/src/ppc64/ppc64-uart.c
index 9830342..a26a806 100644
--- a/src/ppc64/ppc64-uart.c
+++ b/src/ppc64/ppc64-uart.c
@@ -20,8 +20,7 @@ volatile ascii_char_t* const UART0DR = (ascii_char_t*) NB_NS16550_COM1;
 /// @param
 /// @return
 utf_char_t cb_get_char(void) {
-  while (!(*(((volatile uint8_t*) UART0DR) + 0x05) & 0x01))
-    ;
+  while (!(*(((volatile uint8_t*) UART0DR) + 0x05) & 0x01));
   return (utf_char_t) *UART0DR;
 }
 
diff --git a/src/rv64/rv64-uart.c b/src/rv64/rv64-uart.c
index 22b0793..0fb8ab4 100644
--- a/src/rv64/rv64-uart.c
+++ b/src/rv64/rv64-uart.c
@@ -16,8 +16,7 @@ static uint8_t* cb_uart_ptr = (uint8_t*) NB_UART_BASE;
 utf_char_t cb_get_char(void) {
   uintptr_t ptr = NB_UART_BASE;
 
-  while (!(*(((volatile uint8_t*) ptr) + 0x05) & 0x01))
-    ;
+  while (!(*(((volatile uint8_t*) ptr) + 0x05) & 0x01));
 
   return (utf_char_t) *cb_uart_ptr;
 }
-- 
cgit v1.2.3


From 95cd41c10e6da95a3a3eb3435d207394d68cf04f Mon Sep 17 00:00:00 2001
From: Amlal <amlal@nekernel.org>
Date: Tue, 12 Aug 2025 10:32:46 +0200
Subject: fix: Fix comment in AHCI driver.

Signed-off-by: Amlal <amlal@nekernel.org>
---
 src/hal/neboot-ahci-driver.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/hal/neboot-ahci-driver.c b/src/hal/neboot-ahci-driver.c
index b9badd2..1ee1272 100644
--- a/src/hal/neboot-ahci-driver.c
+++ b/src/hal/neboot-ahci-driver.c
@@ -21,7 +21,7 @@
 #define NB_AHCI_DRIVER_NAME ("@sata")
 
 /// BUGS: 0
-/// @brief AHCI support for PowerPC.
+/// @brief Generic AHCI support.
 
 /// @brief AHCI HBA port.
 typedef struct cb_hba_port {
-- 
cgit v1.2.3


From 06cfc7292fa973d23c4019ea1d4749b59e1be5e3 Mon Sep 17 00:00:00 2001
From: Amlal <amlal@nekernel.org>
Date: Fri, 15 Aug 2025 12:13:26 +0200
Subject: feat: include SNU's XeFS filesystem into known filesystems.

Signed-off-by: Amlal <amlal@nekernel.org>
---
 src/neboot-partition-map.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/neboot-partition-map.c b/src/neboot-partition-map.c
index c13907c..edc66e7 100644
--- a/src/neboot-partition-map.c
+++ b/src/neboot-partition-map.c
@@ -9,9 +9,9 @@
 
 // include this for documentation.
 
-#define NB_FILESYSTEM_COUNT 4
+#define NB_FILESYSTEM_COUNT (5U)
 #define NB_FILESYSTEM_LIST \
-  { "NeFS", "HeFS", "FAT32", "ext4" }
+  { "NeFS", "HeFS", "FAT32", "ext4", "XeFS" }
 
 /// @brief check if filesystem is supported by NeBoot.
 /// @param fs the filesystem magic, as provided by EPM.
-- 
cgit v1.2.3