Kernel: Lots of changes.

ArchKit: Remove rt_wait_400ns, as it is unused outside the AMD64 HAL.
Processor.hpp: Fix typo inside AMD64's StackFrame.
HalPageAlloc.hpp: Rename ControlRegisterBits::Paging to ControlRegisterBits::PageEnable.
HalPageAlloc.cpp: Rework Page allocation API.
HalHardwareMP.cpp: Rename from HalHardwareAPIC.cpp, implement primitive routines.
MBCI: Add new fields inside MBCI host according to standard.

Signed-off-by: Amlal El Mahrouss <amlal@el-mahrouss-logic.com>

21 files changed, 443 insertions, 403 deletions

diff --git a/Private/ArchKit/ArchKit.hpp b/Private/ArchKit/ArchKit.hpp
index ce22d70c..ddccbb47 100644
--- a/Private/ArchKit/ArchKit.hpp
+++ b/Private/ArchKit/ArchKit.hpp
@@ -41,7 +41,6 @@ extern NewOS::Array<rt_syscall_proc,
                     kKernelMaxSystemCalls>
     kSyscalls;
 
-EXTERN_C NewOS::Void rt_wait_400ns();
 EXTERN_C NewOS::HAL::StackFramePtr rt_get_current_context();
 EXTERN_C NewOS::Void rt_do_context_switch(NewOS::HAL::StackFramePtr stackFrame);
 
diff --git a/Private/Builtins/AHCI/AHCI.hxx b/Private/Builtins/AHCI/AHCI.hxx
new file mode 100644
index 00000000..f5e139ac
--- /dev/null
+++ b/Private/Builtins/AHCI/AHCI.hxx
@@ -0,0 +1,344 @@
+/* -------------------------------------------
+
+    Copyright Mahrouss Logic
+
+    File: Defines.hxx
+    Purpose: AHCI header.
+
+    Revision History:
+
+    03/02/24: Added file (amlel)
+
+------------------------------------------- */
+
+#pragma once
+
+#include <NewKit/Defines.hpp>
+#include <Builtins/ACPI/ACPI.hxx>
+
+// Forward declarations of structs.
+
+struct HbaPort;
+struct FisData;
+struct FisRegD2H;
+struct FisRegH2D;
+
+/// @brief Frame information type.
+enum {
+  kFISTypeRegH2D = 0x27,    // Register FIS - host to device
+  kFISTypeRegD2H = 0x34,    // Register FIS - device to host
+  kFISTypeDMAAct = 0x39,    // DMA activate FIS - device to host
+  kFISTypeDMASetup = 0x41,  // DMA setup FIS - bidirectional
+  kFISTypeData = 0x46,       // Data FIS - bidirectional
+  kFISTypeBIST = 0x58,       // BIST activate FIS - bidirectional
+  kFISTypePIOSetup = 0x5F,  // PIO setup FIS - device to host
+  kFISTypeDevBits = 0xA1,   // Set device bits FIS - device to host
+};
+
+enum {
+  kAHCICmdIdentify = 0xEC,
+  kAHCICmdReadDma = 0xC8,
+  kAHCICmdReadDmaEx = 0x25,
+  kAHCICmdWriteDma = 0xCA,
+  kAHCICmdWriteDmaEx = 0x35
+};
+
+typedef struct FisRegH2D final {
+  // DWORD 0
+  NewOS::UInt8 FisType;  // FIS_TYPE_REG_H2D
+
+  NewOS::UInt8 PortMul : 4;    // Port multiplier
+  NewOS::UInt8 Reserved0 : 3;  // Reserved
+  NewOS::UInt8 CmdOrCtrl : 1;  // 1: Command, 0: Control
+
+  NewOS::UInt8 Command;   // Command register
+  NewOS::UInt8 Featurel;  // Feature register, 7:0
+
+  // DWORD 1
+  NewOS::UInt8 Lba0;    // LBA low register, 7:0
+  NewOS::UInt8 Lba1;    // LBA mid register, 15:8
+  NewOS::UInt8 Lba2;    // LBA high register, 23:16
+  NewOS::UInt8 Device;  // Device register
+
+  // DWORD 2
+  NewOS::UInt8 Lba3;         // LBA register, 31:24
+  NewOS::UInt8 Lba4;         // LBA register, 39:32
+  NewOS::UInt8 Lba5;         // LBA register, 47:40
+  NewOS::UInt8 FeatureHigh;  // Feature register, 15:8
+
+  // DWORD 3
+  NewOS::UInt8 CountLow;   // Count register, 7:0
+  NewOS::UInt8 CountHigh;  // Count register, 15:8
+  NewOS::UInt8 Icc;        // Isochronous command completion
+  NewOS::UInt8 Control;    // Control register
+
+  // DWORD 4
+  NewOS::UInt8 Reserved1[4];  // Reserved
+} FisRegH2D;
+
+typedef struct FisRegD2H final {
+  // DWORD 0
+  NewOS::UInt8 FisType;  // FIS_TYPE_REG_D2H
+
+  NewOS::UInt8 PortMul : 4;       // Port multiplier
+  NewOS::UInt8 Reserved0 : 2;     // Reserved
+  NewOS::UInt8 InterruptBit : 1;  // Interrupt bit
+  NewOS::UInt8 Reserved1 : 1;     // Reserved
+
+  NewOS::UInt8 Status;  // Status register
+  NewOS::UInt8 Rrror;   // Error register
+
+  // DWORD 1
+  NewOS::UInt8 Lba0;    // LBA low register, 7:0
+  NewOS::UInt8 Lba1;    // LBA mid register, 15:8
+  NewOS::UInt8 Lba2;    // LBA high register, 23:16
+  NewOS::UInt8 Device;  // Device register
+
+  // DWORD 2
+  NewOS::UInt8 Lba3;  // LBA register, 31:24
+  NewOS::UInt8 Lba4;  // LBA register, 39:32
+  NewOS::UInt8 Lba5;  // LBA register, 47:40
+  NewOS::UInt8 Rsv2;  // Reserved
+
+  // DWORD 3
+  NewOS::UInt8 CountLow;   // Count register, 7:0
+  NewOS::UInt8 CountHigh;  // Count register, 15:8
+  NewOS::UInt8 Rsv3[2];    // Reserved
+
+  // DWORD 4
+  NewOS::UInt8 Rsv4[4];  // Reserved
+} FisRegD2H;
+
+typedef struct FisData final {
+  // DWORD 0
+  NewOS::UInt8 FisType;  // FIS_TYPE_DATA
+
+  NewOS::UInt8 PortMul : 4;    // Port multiplier
+  NewOS::UInt8 Reserved0 : 4;  // Reserved
+
+  NewOS::UInt8 Reserved1[2];  // Reserved
+
+  // DWORD 1 ~ N
+  NewOS::UInt32 Data[1];  // Payload
+} FisData;
+
+typedef struct FisPioSetup final {
+  // DWORD 0
+  NewOS::UInt8 FisType;  // FIS_TYPE_PIO_SETUP
+
+  NewOS::UInt8 PortMul : 4;       // Port multiplier
+  NewOS::UInt8 Reserved0 : 1;     // Reserved
+  NewOS::UInt8 DTD : 1;             // Data transfer direction, 1 - device to host
+  NewOS::UInt8 InterruptBit : 1;  // Interrupt bit
+  NewOS::UInt8 Reserved1 : 1;
+
+  NewOS::UInt8 Status;  // Status register
+  NewOS::UInt8 Error;   // Error register
+
+  // DWORD 1
+  NewOS::UInt8 Lba0;    // LBA low register, 7:0
+  NewOS::UInt8 Lba1;    // LBA mid register, 15:8
+  NewOS::UInt8 Lba2;    // LBA high register, 23:16
+  NewOS::UInt8 Device;  // Device register
+
+  // DWORD 2
+  NewOS::UInt8 Lba3;  // LBA register, 31:24
+  NewOS::UInt8 Lba4;  // LBA register, 39:32
+  NewOS::UInt8 Lba5;  // LBA register, 47:40
+  NewOS::UInt8 Rsv2;  // Reserved
+
+  // DWORD 3
+  NewOS::UInt8 CountLow;   // Count register, 7:0
+  NewOS::UInt8 CountHigh;  // Count register, 15:8
+  NewOS::UInt8 Rsv3;       // Reserved
+  NewOS::UInt8 EStatus;    // New value of status register
+
+  // DWORD 4
+  NewOS::UInt16 TranferCount;      // Transfer count
+  NewOS::UInt8 Rsv4[2];  // Reserved
+} FisPioSetup;
+
+typedef struct FisDmaSetup final {
+  // DWORD 0
+  NewOS::UInt8 FisType;  // FIS_TYPE_DMA_SETUP
+
+  NewOS::UInt8 PortMul : 4;       // Port multiplier
+  NewOS::UInt8 Reserved0 : 1;     // Reserved
+  NewOS::UInt8 DTD : 1;           // Data transfer direction, 1 - device to host
+  NewOS::UInt8 InterruptBit : 1;  // Interrupt bit
+  NewOS::UInt8 AutoEnable : 1;  // Auto-activate. Specifies if DMA Activate FIS is needed
+
+  NewOS::UInt8 Reserved1[2];  // Reserved
+
+  // DWORD 1&2
+  NewOS::UInt64 DmaBufferId;  // DMA Buffer Identifier. Used to Identify DMA buffer in
+                       // host memory. SATA Spec says host specific and not in
+                       // Spec. Trying AHCI spec might work.
+
+  // DWORD 3
+  NewOS::UInt32 Rsvd;  // More reserved
+
+  // DWORD 4
+  NewOS::UInt32 DmabufOffset;  // Byte offset into buffer. First 2 bits must be 0
+
+  // DWORD 5
+  NewOS::UInt32 TransferCount;  // Number of bytes to transfer. Bit 0 must be 0
+
+  // DWORD 6
+  NewOS::UInt32 Reserved3;  // Reserved
+} FisDmaSetup;
+
+typedef struct FisDevBits final {
+  // DWORD 0
+  NewOS::UInt8 FisType;  // FIS_TYPE_DMA_SETUP (A1h)
+
+  NewOS::UInt8 Reserved0 : 5;  // Reserved
+  NewOS::UInt8 R0 : 1;
+  NewOS::UInt8 InterruptBit : 1;
+  NewOS::UInt8 N : 1;
+
+  NewOS::UInt8 StatusLow : 3;
+  NewOS::UInt8 R1 : 1;
+  NewOS::UInt8 StatusHigh : 3;
+
+  NewOS::UInt8 R2 : 1;
+  NewOS::UInt8 Error;
+
+  // DWORD 1
+  NewOS::UInt32 Act;
+} FisDevBits;
+
+/// \brief Enable AHCI device bit in GHC register.
+#ifndef kAhciGHC_AE
+#define kAhciGHC_AE (31)
+#endif  //! ifndef kAhciGHC_AE
+
+typedef struct HbaPort final {
+  NewOS::UInt32 Clb;            // 0x00, command list base address, 1K-byte aligned
+  NewOS::UInt32 Clbu;           // 0x04, command list base address upper 32 bits
+  NewOS::UInt32 Fb;             // 0x08, FIS base address, 256-byte aligned
+  NewOS::UInt32 Fbu;            // 0x0C, FIS base address upper 32 bits
+  NewOS::UInt32 Is;             // 0x10, interrupt status
+  NewOS::UInt32 Ie;             // 0x14, interrupt enable
+  NewOS::UInt32 Cmd;            // 0x18, command and status
+  NewOS::UInt32 Reserved0;      // 0x1C, Reserved
+  NewOS::UInt32 Tfd;            // 0x20, task file data
+  NewOS::UInt32 Sig;            // 0x24, signature
+  NewOS::UInt32 Ssts;           // 0x28, SATA status (SCR0:SStatus)
+  NewOS::UInt32 Sctl;           // 0x2C, SATA control (SCR2:SControl)
+  NewOS::UInt32 Serr;           // 0x30, SATA error (SCR1:SError)
+  NewOS::UInt32 Sact;           // 0x34, SATA active (SCR3:SActive)
+  NewOS::UInt32 Ci;             // 0x38, command issue
+  NewOS::UInt32 Sntf;           // 0x20, SATA notification (SCR4:SNotification)
+  NewOS::UInt32 Fbs;            // 0x40, FIS-based switch control
+  NewOS::UInt32 Reserved1[11];  // 0x44 ~ 0x6F, Reserved
+  NewOS::UInt32 Vendor[4];      // 0x70 ~ 0x7F, vendor specific
+} HbaPort;
+
+typedef struct HbaMem final {
+  // 0x00 - 0x2B, Generic Host Control
+  NewOS::UInt32 Cap;      // 0x00, Host capability
+  NewOS::UInt32 Ghc;      // 0x04, Global host control
+  NewOS::UInt32 Is;       // 0x08, Interrupt status
+  NewOS::UInt32 Pi;       // 0x0C, Port implemented
+  NewOS::UInt32 Vs;       // 0x10, Version
+  NewOS::UInt32 Ccc_ctl;  // 0x14, Command completion coalescing control
+  NewOS::UInt32 Ccc_pts;  // 0x18, Command completion coalescing ports
+  NewOS::UInt32 Em_loc;   // 0x1C, Enclosure management location
+  NewOS::UInt32 Em_ctl;   // 0x20, Enclosure management control
+  NewOS::UInt32 Cap2;     // 0x24, Host capabilities extended
+  NewOS::UInt32 Bohc;     // 0x28, BIOS/OS handoff control and status
+
+  NewOS::UInt16 Resv0;
+  NewOS::UInt32 Resv2;
+
+  HbaPort Ports[1];  // 1 ~ 32
+} HbaMem;
+
+typedef struct HbaCmdHeader final {
+  // DW0
+  NewOS::UInt8 Cfl : 5;           // Command FIS length in DWORDS, 2 ~ 16
+  NewOS::UInt8 Atapi : 1;         // ATAPI
+  NewOS::UInt8 Write : 1;         // Write, 1: H2D, 0: D2H
+  NewOS::UInt8 Prefetchable : 1;  // Prefetchable
+
+  NewOS::UInt8 Reset : 1;      // Reset
+  NewOS::UInt8 BIST : 1;       // BIST
+  NewOS::UInt8 Clear : 1;      // Clear busy upon R_OK
+  NewOS::UInt8 Reserved0 : 1;  // Reserved
+  NewOS::UInt8 Pmp : 4;        // Port multiplier port
+
+  NewOS::UInt16 Prdtl;           // Physical region descriptor table length in entries
+  volatile NewOS::UInt32 Prdbc;  // Physical region descriptor byte count transferred
+
+  NewOS::UInt32 Ctba;   // Command table descriptor base address
+  NewOS::UInt32 Ctbau;  // Command table descriptor base address upper 32 bits
+
+  NewOS::UInt32 Reserved1[4];  // Reserved
+} HbaCmdHeader;
+
+typedef struct HbaFis final {
+  // 0x00
+  FisDmaSetup Dsfis;  // DMA Setup FIS
+  NewOS::UInt8 Pad0[4];
+  // 0x20
+  FisPioSetup Psfis;  // PIO Setup FIS
+  NewOS::UInt8 Pad1[12];
+  // 0x40
+  FisRegD2H Rfis;  // Register – Device to Host FIS
+  NewOS::UInt8 Pad2[4];
+  // 0x58
+  FisDevBits Sdbfis;  // Set Device Bit FIS
+  // 0x60
+  NewOS::UInt8 Ufis[64];
+  // 0xA0
+  NewOS::UInt8 Rsv[0x100 - 0xA0];
+} HbaFis;
+
+typedef struct HbaPrdtEntry final {
+  NewOS::UInt32 Dba;        // Data base address
+  NewOS::UInt32 Dbau;       // Data base address upper 32 bits
+  NewOS::UInt32 Reserved0;  // Reserved
+  // DW3
+  NewOS::UInt32 Dbc : 22;          // Byte count, 4M max
+  NewOS::UInt32 Reserved1 : 9;     // Reserved
+  NewOS::UInt32 InterruptBit : 1;  // Interrupt on completion
+} HbaPrdtEntry;
+
+typedef struct HbaCmdTbl final {
+  NewOS::UInt8 Cfis[64];  // Command FIS
+  NewOS::UInt8 Acmd[16];  // ATAPI command, 12 or 16 bytes
+  NewOS::UInt8 Rsv[48];   // Reserved
+  struct HbaPrdtEntry prdtEntries[1];  // Physical region descriptor table entries, 0 ~ 65535
+} HbaCmdTbl;
+
+/* EOF */
+
+#if defined(__AHCI__)
+
+/// @brief Initializes an AHCI disk.
+/// @param PortsImplemented the amount of port that have been detected.
+/// @return 
+NewOS::Boolean drv_std_init(NewOS::UInt16& PortsImplemented);
+
+NewOS::Boolean drv_std_detected(NewOS::Void);
+
+/// @brief Read from disk.
+/// @param Lba 
+/// @param Buf 
+/// @param SectorSz 
+/// @param Size 
+/// @return 
+NewOS::Void drv_std_read(NewOS::UInt64 Lba, NewOS::Char* Buf,
+                   NewOS::SizeT SectorSz, NewOS::SizeT Size);
+
+/// @brief Write to disk.
+/// @param Lba 
+/// @param Buf 
+/// @param SectorSz 
+/// @param Size 
+/// @return 
+NewOS::Void drv_std_write(NewOS::UInt64 Lba, NewOS::Char* Buf,
+                    NewOS::SizeT SectorSz, NewOS::SizeT Size);
+
+#endif // ifdef __KERNEL__
diff --git a/Private/Builtins/AHCI/Defines.hxx b/Private/Builtins/AHCI/Defines.hxx
deleted file mode 100644
index 3af3cd4c..00000000
--- a/Private/Builtins/AHCI/Defines.hxx
+++ /dev/null
@@ -1,346 +0,0 @@
-/* -------------------------------------------
-
-    Copyright Mahrouss Logic
-
-    File: Defines.hxx
-    Purpose: AHCI header.
-
-    Revision History:
-
-    03/02/24: Added file (amlel)
-
-------------------------------------------- */
-
-#pragma once
-
-#include <NewKit/Defines.hpp>
-#include <Builtins/ACPI/ACPI.hxx>
-
-// Forward declarations of structs.
-
-struct HbaPort;
-struct FisData;
-struct FisRegD2H;
-struct FisRegH2D;
-
-// Enum types
-
-typedef enum {
-  FIS_TYPE_REG_H2D = 0x27,    // Register FIS - host to device
-  FIS_TYPE_REG_D2H = 0x34,    // Register FIS - device to host
-  FIS_TYPE_DMA_ACT = 0x39,    // DMA activate FIS - device to host
-  FIS_TYPE_DMA_SETUP = 0x41,  // DMA setup FIS - bidirectional
-  FIS_TYPE_DATA = 0x46,       // Data FIS - bidirectional
-  FIS_TYPE_BIST = 0x58,       // BIST activate FIS - bidirectional
-  FIS_TYPE_PIO_SETUP = 0x5F,  // PIO setup FIS - device to host
-  FIS_TYPE_DEV_BITS = 0xA1,   // Set device bits FIS - device to host
-} AHCI_FIS_TYPE;
-
-typedef enum {
-  AHCI_ATA_CMD_IDENTIFY = 0xEC,
-  AHCI_ATA_CMD_READ_DMA = 0xC8,
-  AHCI_ATA_CMD_READ_DMA_EX = 0x25,
-  AHCI_ATA_CMD_WRITE_DMA = 0xCA,
-  AHCI_ATA_CMD_WRITE_DMA_EX = 0x35
-} AHCI_FIS_COMMAND;
-
-typedef struct FisRegH2D final {
-  // DWORD 0
-  NewOS::UInt8 fisType;  // FIS_TYPE_REG_H2D
-
-  NewOS::UInt8 portMul : 4;    // Port multiplier
-  NewOS::UInt8 reserved0 : 3;  // Reserved
-  NewOS::UInt8 cmdOrCtrl : 1;  // 1: Command, 0: Control
-
-  NewOS::UInt8 command;   // Command register
-  NewOS::UInt8 featurel;  // Feature register, 7:0
-
-  // DWORD 1
-  NewOS::UInt8 lba0;    // LBA low register, 7:0
-  NewOS::UInt8 lba1;    // LBA mid register, 15:8
-  NewOS::UInt8 lba2;    // LBA high register, 23:16
-  NewOS::UInt8 device;  // Device register
-
-  // DWORD 2
-  NewOS::UInt8 lba3;         // LBA register, 31:24
-  NewOS::UInt8 lba4;         // LBA register, 39:32
-  NewOS::UInt8 lba5;         // LBA register, 47:40
-  NewOS::UInt8 featureHigh;  // Feature register, 15:8
-
-  // DWORD 3
-  NewOS::UInt8 countLow;   // Count register, 7:0
-  NewOS::UInt8 countHigh;  // Count register, 15:8
-  NewOS::UInt8 icc;        // Isochronous command completion
-  NewOS::UInt8 control;    // Control register
-
-  // DWORD 4
-  NewOS::UInt8 reserved1[4];  // Reserved
-} FisRegH2D;
-
-typedef struct FisRegD2H final {
-  // DWORD 0
-  NewOS::UInt8 fisType;  // FIS_TYPE_REG_D2H
-
-  NewOS::UInt8 portMul : 4;       // Port multiplier
-  NewOS::UInt8 reserved0 : 2;     // Reserved
-  NewOS::UInt8 interruptBit : 1;  // Interrupt bit
-  NewOS::UInt8 reserved1 : 1;     // Reserved
-
-  NewOS::UInt8 status;  // Status register
-  NewOS::UInt8 error;   // Error register
-
-  // DWORD 1
-  NewOS::UInt8 lba0;    // LBA low register, 7:0
-  NewOS::UInt8 lba1;    // LBA mid register, 15:8
-  NewOS::UInt8 lba2;    // LBA high register, 23:16
-  NewOS::UInt8 device;  // Device register
-
-  // DWORD 2
-  NewOS::UInt8 lba3;  // LBA register, 31:24
-  NewOS::UInt8 lba4;  // LBA register, 39:32
-  NewOS::UInt8 lba5;  // LBA register, 47:40
-  NewOS::UInt8 rsv2;  // Reserved
-
-  // DWORD 3
-  NewOS::UInt8 countLow;   // Count register, 7:0
-  NewOS::UInt8 countHigh;  // Count register, 15:8
-  NewOS::UInt8 rsv3[2];    // Reserved
-
-  // DWORD 4
-  NewOS::UInt8 rsv4[4];  // Reserved
-} FisRegD2H;
-
-typedef struct FisData final {
-  // DWORD 0
-  NewOS::UInt8 fisType;  // FIS_TYPE_DATA
-
-  NewOS::UInt8 portMul : 4;    // Port multiplier
-  NewOS::UInt8 reserved0 : 4;  // Reserved
-
-  NewOS::UInt8 reserved1[2];  // Reserved
-
-  // DWORD 1 ~ N
-  NewOS::UInt32 data[1];  // Payload
-} FisData;
-
-typedef struct FisPioSetup final {
-  // DWORD 0
-  NewOS::UInt8 fisType;  // FIS_TYPE_PIO_SETUP
-
-  NewOS::UInt8 portMul : 4;       // Port multiplier
-  NewOS::UInt8 reserved0 : 1;     // Reserved
-  NewOS::UInt8 d : 1;             // Data transfer direction, 1 - device to host
-  NewOS::UInt8 interruptBit : 1;  // Interrupt bit
-  NewOS::UInt8 reserved1 : 1;
-
-  NewOS::UInt8 status;  // Status register
-  NewOS::UInt8 error;   // Error register
-
-  // DWORD 1
-  NewOS::UInt8 lba0;    // LBA low register, 7:0
-  NewOS::UInt8 lba1;    // LBA mid register, 15:8
-  NewOS::UInt8 lba2;    // LBA high register, 23:16
-  NewOS::UInt8 device;  // Device register
-
-  // DWORD 2
-  NewOS::UInt8 lba3;  // LBA register, 31:24
-  NewOS::UInt8 lba4;  // LBA register, 39:32
-  NewOS::UInt8 lba5;  // LBA register, 47:40
-  NewOS::UInt8 rsv2;  // Reserved
-
-  // DWORD 3
-  NewOS::UInt8 countLow;   // Count register, 7:0
-  NewOS::UInt8 countHigh;  // Count register, 15:8
-  NewOS::UInt8 rsv3;       // Reserved
-  NewOS::UInt8 eStatus;    // New value of status register
-
-  // DWORD 4
-  NewOS::UInt16 tc;      // Transfer count
-  NewOS::UInt8 rsv4[2];  // Reserved
-} FisPioSetup;
-
-typedef struct FisDmaSetup final {
-  // DWORD 0
-  NewOS::UInt8 fisType;  // FIS_TYPE_DMA_SETUP
-
-  NewOS::UInt8 portMul : 4;       // Port multiplier
-  NewOS::UInt8 reserved0 : 1;     // Reserved
-  NewOS::UInt8 dtd : 1;           // Data transfer direction, 1 - device to host
-  NewOS::UInt8 interruptBit : 1;  // Interrupt bit
-  NewOS::UInt8
-      autoEnable : 1;  // Auto-activate. Specifies if DMA Activate FIS is needed
-
-  NewOS::UInt8 reserved1[2];  // Reserved
-
-  // DWORD 1&2
-  NewOS::UInt64 dmaBufferId;  // DMA Buffer Identifier. Used to Identify DMA buffer in
-                       // host memory. SATA Spec says host specific and not in
-                       // Spec. Trying AHCI spec might work.
-
-  // DWORD 3
-  NewOS::UInt32 rsvd;  // More reserved
-
-  // DWORD 4
-  NewOS::UInt32 dmabufOffset;  // Byte offset into buffer. First 2 bits must be 0
-
-  // DWORD 5
-  NewOS::UInt32 transferCount;  // Number of bytes to transfer. Bit 0 must be 0
-
-  // DWORD 6
-  NewOS::UInt32 reserved3;  // Reserved
-} FisDmaSetup;
-
-typedef struct FisDevBits final {
-  // DWORD 0
-  NewOS::UInt8 fisType;  // FIS_TYPE_DMA_SETUP (A1h)
-
-  NewOS::UInt8 reserved0 : 5;  // Reserved
-  NewOS::UInt8 r0 : 1;
-  NewOS::UInt8 interruptBit : 1;
-  NewOS::UInt8 n : 1;
-
-  NewOS::UInt8 statusLow : 3;
-  NewOS::UInt8 r1 : 1;
-  NewOS::UInt8 statusHigh : 3;
-
-  NewOS::UInt8 r2 : 1;
-  NewOS::UInt8 error;
-
-  // DWORD 1
-  NewOS::UInt32 act;
-} FisDevBits;
-
-/// \brief Enable AHCI device bit in GHC register.
-#ifndef kAhciGHC_AE
-#define kAhciGHC_AE (31)
-#endif  //! ifndef kAhciGHC_AE
-
-typedef struct HbaPort final {
-  NewOS::UInt32 clb;            // 0x00, command list base address, 1K-byte aligned
-  NewOS::UInt32 clbu;           // 0x04, command list base address upper 32 bits
-  NewOS::UInt32 fb;             // 0x08, FIS base address, 256-byte aligned
-  NewOS::UInt32 fbu;            // 0x0C, FIS base address upper 32 bits
-  NewOS::UInt32 is;             // 0x10, interrupt status
-  NewOS::UInt32 ie;             // 0x14, interrupt enable
-  NewOS::UInt32 cmd;            // 0x18, command and status
-  NewOS::UInt32 reserved0;      // 0x1C, Reserved
-  NewOS::UInt32 tfd;            // 0x20, task file data
-  NewOS::UInt32 sig;            // 0x24, signature
-  NewOS::UInt32 ssts;           // 0x28, SATA status (SCR0:SStatus)
-  NewOS::UInt32 sctl;           // 0x2C, SATA control (SCR2:SControl)
-  NewOS::UInt32 serr;           // 0x30, SATA error (SCR1:SError)
-  NewOS::UInt32 sact;           // 0x34, SATA active (SCR3:SActive)
-  NewOS::UInt32 ci;             // 0x38, command issue
-  NewOS::UInt32 sntf;           // 0x20, SATA notification (SCR4:SNotification)
-  NewOS::UInt32 fbs;            // 0x40, FIS-based switch control
-  NewOS::UInt32 reserved1[11];  // 0x44 ~ 0x6F, Reserved
-  NewOS::UInt32 vendor[4];      // 0x70 ~ 0x7F, vendor specific
-} HbaPort;
-
-typedef struct HbaMem final {
-  // 0x00 - 0x2B, Generic Host Control
-  NewOS::UInt32 cap;      // 0x00, Host capability
-  NewOS::UInt32 ghc;      // 0x04, Global host control
-  NewOS::UInt32 is;       // 0x08, Interrupt status
-  NewOS::UInt32 pi;       // 0x0C, Port implemented
-  NewOS::UInt32 vs;       // 0x10, Version
-  NewOS::UInt32 ccc_ctl;  // 0x14, Command completion coalescing control
-  NewOS::UInt32 ccc_pts;  // 0x18, Command completion coalescing ports
-  NewOS::UInt32 em_loc;   // 0x1C, Enclosure management location
-  NewOS::UInt32 em_ctl;   // 0x20, Enclosure management control
-  NewOS::UInt32 cap2;     // 0x24, Host capabilities extended
-  NewOS::UInt32 bohc;     // 0x28, BIOS/OS handoff control and status
-
-  NewOS::UInt16 rsv;
-  NewOS::UInt32 resv2;
-
-  HbaPort ports[1];  // 1 ~ 32
-} HbaMem;
-
-typedef struct HbaCmdHeader final {
-  // DW0
-  NewOS::UInt8 cfl : 5;           // Command FIS length in DWORDS, 2 ~ 16
-  NewOS::UInt8 atapi : 1;         // ATAPI
-  NewOS::UInt8 write : 1;         // Write, 1: H2D, 0: D2H
-  NewOS::UInt8 prefetchable : 1;  // Prefetchable
-
-  NewOS::UInt8 reset : 1;      // Reset
-  NewOS::UInt8 BIST : 1;       // BIST
-  NewOS::UInt8 clear : 1;      // Clear busy upon R_OK
-  NewOS::UInt8 reserved0 : 1;  // Reserved
-  NewOS::UInt8 pmp : 4;        // Port multiplier port
-
-  NewOS::UInt16 prdtl;           // Physical region descriptor table length in entries
-  volatile NewOS::UInt32 prdbc;  // Physical region descriptor byte count transferred
-
-  NewOS::UInt32 ctba;   // Command table descriptor base address
-  NewOS::UInt32 ctbau;  // Command table descriptor base address upper 32 bits
-
-  NewOS::UInt32 reserved1[4];  // Reserved
-} HbaCmdHeader;
-
-typedef struct HbaFis final {
-  // 0x00
-  FisDmaSetup dsfis;  // DMA Setup FIS
-  NewOS::UInt8 pad0[4];
-  // 0x20
-  FisPioSetup psfis;  // PIO Setup FIS
-  NewOS::UInt8 pad1[12];
-  // 0x40
-  FisRegD2H rfis;  // Register – Device to Host FIS
-  NewOS::UInt8 pad2[4];
-  // 0x58
-  FisDevBits sdbfis;  // Set Device Bit FIS
-  // 0x60
-  NewOS::UInt8 ufis[64];
-  // 0xA0
-  NewOS::UInt8 rsv[0x100 - 0xA0];
-} HbaFis;
-
-typedef struct HbaPrdtEntry final {
-  NewOS::UInt32 dba;        // Data base address
-  NewOS::UInt32 dbau;       // Data base address upper 32 bits
-  NewOS::UInt32 reserved0;  // Reserved
-  // DW3
-  NewOS::UInt32 dbc : 22;          // Byte count, 4M max
-  NewOS::UInt32 reserved1 : 9;     // Reserved
-  NewOS::UInt32 interruptBit : 1;  // Interrupt on completion
-} HbaPrdtEntry;
-
-typedef struct HbaCmdTbl final {
-  NewOS::UInt8 cfis[64];  // Command FIS
-  NewOS::UInt8 acmd[16];  // ATAPI command, 12 or 16 bytes
-  NewOS::UInt8 rsv[48];   // Reserved
-  struct HbaPrdtEntry prdtEntries[1];  // Physical region descriptor table entries, 0 ~ 65535
-} HbaCmdTbl;
-
-/* EOF */
-
-#if defined(__AHCI__)
-
-/// @brief Initializes an AHCI disk.
-/// @param PortsImplemented the amount of port that have been detected.
-/// @return 
-NewOS::Boolean drv_std_init(NewOS::UInt16& PortsImplemented);
-
-NewOS::Boolean drv_std_detected(NewOS::Void);
-
-/// @brief Read from disk.
-/// @param Lba 
-/// @param Buf 
-/// @param SectorSz 
-/// @param Size 
-/// @return 
-NewOS::Void drv_std_read(NewOS::UInt64 Lba, NewOS::Char* Buf,
-                   NewOS::SizeT SectorSz, NewOS::SizeT Size);
-
-/// @brief Write to disk.
-/// @param Lba 
-/// @param Buf 
-/// @param SectorSz 
-/// @param Size 
-/// @return 
-NewOS::Void drv_std_write(NewOS::UInt64 Lba, NewOS::Char* Buf,
-                    NewOS::SizeT SectorSz, NewOS::SizeT Size);
-
-#endif // ifdef __KERNEL__
diff --git a/Private/Builtins/ATA/Defines.hxx b/Private/Builtins/ATA/ATA.hxx
index 9eed6039..66856d8a 100644
--- a/Private/Builtins/ATA/Defines.hxx
+++ b/Private/Builtins/ATA/ATA.hxx
@@ -13,6 +13,8 @@
 
 #pragma once
 
+#ifndef __AHCI__
+
 #include <CompilerKit/CompilerKit.hxx>
 #include <NewKit/Defines.hpp>
 
@@ -146,3 +148,4 @@ NewOS::Void drv_std_write(NewOS::UInt64 Lba, NewOS::UInt16 IO, NewOS::UInt8 Mast
                     NewOS::SizeT SectorSz, NewOS::SizeT Size);
 
 #endif // ifdef __KERNEL__
+#endif // ifndef __AHCI__
diff --git a/Private/Builtins/MBCI/Interface.hxx b/Private/Builtins/MBCI/Interface.hxx
new file mode 100644
index 00000000..37c6d5d6
--- /dev/null
+++ b/Private/Builtins/MBCI/Interface.hxx
@@ -0,0 +1,10 @@
+/* -------------------------------------------
+
+    Copyright Mahrouss Logic
+
+------------------------------------------- */
+
+#pragma once
+
+#include <NewKit/Defines.hpp>
+#include <Builtins/MBCI/MBCI.hxx>
\ No newline at end of file
diff --git a/Private/Builtins/MBCI/Defines.hxx b/Private/Builtins/MBCI/MBCI.hxx
index 18b73ddf..a41b0569 100644
--- a/Private/Builtins/MBCI/Defines.hxx
+++ b/Private/Builtins/MBCI/MBCI.hxx
@@ -14,15 +14,19 @@ struct MBCIHostInterface;
 struct MBCIDeviceInterface;
 struct MBCIPacketInterface;
 
-/// @brief Host interface
+/// @brief MBCI Host Interface header.
 struct MBCIHostInterface final {
 	UInt32 HostId;
-	UInt32 VendorId;
-	UInt64 BaseAddressRegister;
-	UInt64 DeviceSize;
+	UInt16 VendorId;
+	UInt16 DeviceId;
 	UInt8  MemoryType;
 	UInt8  HostType;
 	UInt8  HostFlags;
+	UInt8  Error;
+	UInt8  Status;
+	UInt8  InterruptEnable;
+	UInt64 BaseAddressRegister;
+	UInt64 BaseAddressRegisterSize;
 };
 
 /// @brief MBCI host flags.
@@ -34,6 +38,4 @@ enum MBCIHostFlags {
 	kMBCIHostFlagsSupportsDMA, /// Has DMA.
 	kMBCIHostFlagsCount,
 };
-
-MBCIHostInterface* drv_get_mbi_host(void);
 } // namespace NewOS
diff --git a/Private/HALKit/AMD64/HalHardwareAPIC.cpp b/Private/HALKit/AMD64/HalHardwareMP.cpp
index 6d5fe234..0e9f3022 100644
--- a/Private/HALKit/AMD64/HalHardwareAPIC.cpp
+++ b/Private/HALKit/AMD64/HalHardwareMP.cpp
@@ -9,27 +9,31 @@
 // bugs = 0
 
 namespace NewOS {
-// @brief wakes up thread.
-// wakes up thread from hang.
+/// @brief wakes up thread.
+/// wakes up thread from hang.
 void rt_wakeup_thread(HAL::StackFrame* stack) {
   HAL::rt_cli();
 
-    // TODO
+  stack->Rcx = 0;
 
   HAL::rt_sti();
 }
 
-static void __rt_hang_proc(void) {
-  while (1) {
-
+/// @brief Hangs until RCX register is cleared.
+/// @param stack 
+static void __rt_hang_proc(HAL::StackFrame* stack) {
+  while (stack->Rcx == 1) {
+    ;
   }
 }
 
-// @brief makes thread sleep.
-// hooks and hangs thread to prevent code from executing.
+/// @brief makes thread sleep.
+/// hooks and hangs thread to prevent code from executing.
 void rt_hang_thread(HAL::StackFrame* stack) {
   HAL::rt_cli();
 
+  __rt_hang_proc(stack);
+
   HAL::rt_sti();
 }
 }  // namespace NewOS
diff --git a/Private/HALKit/AMD64/HalPageAlloc.cpp b/Private/HALKit/AMD64/HalPageAlloc.cpp
index 53680668..3a8d3047 100644
--- a/Private/HALKit/AMD64/HalPageAlloc.cpp
+++ b/Private/HALKit/AMD64/HalPageAlloc.cpp
@@ -12,34 +12,65 @@
 STATIC NewOS::Boolean kAllocationInProgress = false;
 namespace NewOS {
 namespace HAL {
+namespace Detail {
+struct VirtualMemoryHeader {
+  Boolean Present : 1;
+  Boolean ReadWrite : 1;
+  Boolean User : 1;
+};
+
+struct VirtualMemoryHeaderTraits {
+  /// @brief Get next header.
+  /// @param current 
+  /// @return 
+  VirtualMemoryHeader* Next(VirtualMemoryHeader* current) {
+    return current + sizeof(PTE);
+  }
+
+  /// @brief Get previous header.
+  /// @param current 
+  /// @return 
+  VirtualMemoryHeader* Prev(VirtualMemoryHeader* current) {
+    return current - sizeof(PTE);
+  }
+};
+}
+
 /// @brief Allocates a new page of memory.
 /// @param sz the size of it.
 /// @param rw read/write flag.
 /// @param user user flag.
 /// @return the page table of it.
 STATIC auto hal_try_alloc_new_page(Boolean rw, Boolean user) -> VoidPtr {
+  if (kAllocationInProgress) return nullptr;
+
   kAllocationInProgress = true;
-  PTE* newAddress = (PTE*)kKernelVirtualStart;
 
-  while (newAddress->Present) {
-    newAddress = newAddress + sizeof(PTE);
+  ///! fetch from the start.
+  Detail::VirtualMemoryHeader* vmHeader = reinterpret_cast<Detail::VirtualMemoryHeader*>(kKernelVirtualStart);
+  Detail::VirtualMemoryHeaderTraits traits;
+
+  while (vmHeader->Present) {
+    vmHeader = traits.Next(vmHeader);
   }
 
-  newAddress->Present = true;
-  newAddress->Rw = rw;
-  newAddress->User = user;
+  vmHeader->Present = true;
+  vmHeader->ReadWrite = rw;
+  vmHeader->User = user;
 
   kAllocationInProgress = false;
 
-  return reinterpret_cast<VoidPtr>(newAddress);
+  return reinterpret_cast<VoidPtr>(vmHeader);
 }
 
 /// @brief Allocate a new page to be used by the OS.
-/// @param rw
-/// @param user
+/// @param rw read/write bit.
+/// @param user user bit.
 /// @return
 auto hal_alloc_page(Boolean rw, Boolean user) -> VoidPtr {
+  /// Wait for a ongoing allocation to complete.
   while (kAllocationInProgress) {
+    ;
   }
 
   /// allocate new page.
diff --git a/Private/HALKit/AMD64/HalPageAlloc.hpp b/Private/HALKit/AMD64/HalPageAlloc.hpp
index 9cd10213..d23c6e96 100644
--- a/Private/HALKit/AMD64/HalPageAlloc.hpp
+++ b/Private/HALKit/AMD64/HalPageAlloc.hpp
@@ -60,7 +60,7 @@ enum class ControlRegisterBits {
   AlignementMask = 18,
   NotWriteThrough = 29,
   CacheDisable = 30,
-  Paging = 31,
+  PageEnable = 31,
 };
 
 inline UInt8 control_register_cast(ControlRegisterBits reg) {
diff --git a/Private/HALKit/AMD64/Processor.hpp b/Private/HALKit/AMD64/Processor.hpp
index a2aaf8f7..7e2624d7 100644
--- a/Private/HALKit/AMD64/Processor.hpp
+++ b/Private/HALKit/AMD64/Processor.hpp
@@ -82,7 +82,7 @@ using interruptTrap = UIntPtr(UIntPtr sp);
 typedef UIntPtr Reg;
 
 struct PACKED StackFrame final {
-    Reg IntNum, Excpetion;
+    Reg IntNum, Exception;
     Reg Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
     Reg R8, R9, R10, R11, R12, R13, R14, R15;
     Reg Gs, Fs;
diff --git a/Private/HALKit/AMD64/Storage/AHCI.cxx b/Private/HALKit/AMD64/Storage/AHCI.cxx
index 2b58b744..5e6b3348 100644
--- a/Private/HALKit/AMD64/Storage/AHCI.cxx
+++ b/Private/HALKit/AMD64/Storage/AHCI.cxx
@@ -15,7 +15,7 @@
  *
  */
 
-#include <Builtins/AHCI/Defines.hxx>
+#include <Builtins/AHCI/AHCI.hxx>
 #include <KernelKit/PCI/Iterator.hpp>
 
 #ifdef __AHCI__
@@ -36,7 +36,7 @@ NewOS::Boolean drv_std_init(NewOS::UInt16& PortsImplemented) {
       iterator[devIndex].Leak().EnableMmio();
       kAhciDevice = iterator[devIndex].Leak();
 
-      kcout << "NewKernel: Found AHCI controller.\r\n";
+      kcout << "NewKernel: [PCI] Found AHCI controller.\r\n";
     
       return true;
     }
diff --git a/Private/HALKit/AMD64/Storage/ATA-DMA.cxx b/Private/HALKit/AMD64/Storage/ATA-DMA.cxx
index 523c7e17..b40910ab 100644
--- a/Private/HALKit/AMD64/Storage/ATA-DMA.cxx
+++ b/Private/HALKit/AMD64/Storage/ATA-DMA.cxx
@@ -17,7 +17,7 @@
 
 #include <StorageKit/PRDT.hpp>
 
-#include <Builtins/ATA/Defines.hxx>
+#include <Builtins/ATA/ATA.hxx>
 #include <ArchKit/ArchKit.hpp>
 
 using namespace NewOS;
diff --git a/Private/HALKit/AMD64/Storage/ATA-PIO.cxx b/Private/HALKit/AMD64/Storage/ATA-PIO.cxx
index 0ff3591e..ebced11c 100644
--- a/Private/HALKit/AMD64/Storage/ATA-PIO.cxx
+++ b/Private/HALKit/AMD64/Storage/ATA-PIO.cxx
@@ -15,7 +15,7 @@
  *
  */
 
-#include <Builtins/ATA/Defines.hxx>
+#include <Builtins/ATA/ATA.hxx>
 #include <ArchKit/ArchKit.hpp>
 
 #ifdef __ATA_PIO__
diff --git a/Private/HALKit/PowerPC/HalThread.cxx b/Private/HALKit/PowerPC/HalThread.cxx
index af8bcc6f..a91e7f28 100644
--- a/Private/HALKit/PowerPC/HalThread.cxx
+++ b/Private/HALKit/PowerPC/HalThread.cxx
@@ -7,7 +7,4 @@
 #include <HALKit/PowerPC/Processor.hpp>
 #include <KernelKit/DebugOutput.hpp>
 
-extern "C" void hal_flush_tlb() {}
-extern "C" void rt_wait_400ns() {}
-
 extern "C" NewOS::HAL::StackFramePtr rt_get_current_context() { return nullptr; }
diff --git a/Private/HALKit/PowerPC/HalVirtualMemory.cxx b/Private/HALKit/PowerPC/HalVirtualMemory.cxx
new file mode 100644
index 00000000..0015257e
--- /dev/null
+++ b/Private/HALKit/PowerPC/HalVirtualMemory.cxx
@@ -0,0 +1,10 @@
+/* -------------------------------------------
+
+    Copyright Mahrouss Logic
+
+------------------------------------------- */
+
+#include <HALKit/PowerPC/Processor.hpp>
+#include <KernelKit/DebugOutput.hpp>
+
+extern "C" void hal_flush_tlb() {}
diff --git a/Private/NewBoot/BootKit/Device.hxx b/Private/NewBoot/BootKit/Device.hxx
index 8158b0d6..45bc7e69 100644
--- a/Private/NewBoot/BootKit/Device.hxx
+++ b/Private/NewBoot/BootKit/Device.hxx
@@ -6,7 +6,7 @@
 
 #pragma once
 
-#include <Builtins/ATA/Defines.hxx>
+#include <Builtins/ATA/ATA.hxx>
 
 using namespace NewOS;
 
diff --git a/Private/NewBoot/BootKit/HW/ATA.hxx b/Private/NewBoot/BootKit/HW/ATA.hxx
index e74c7a20..9127e598 100644
--- a/Private/NewBoot/BootKit/HW/ATA.hxx
+++ b/Private/NewBoot/BootKit/HW/ATA.hxx
@@ -6,7 +6,7 @@
 
 #pragma once
 
-#include <Builtins/ATA/Defines.hxx>
+#include <Builtins/ATA/ATA.hxx>
 #include <BootKit/Device.hxx>
 
 using namespace NewOS;
diff --git a/Private/NewBoot/BootKit/HW/SATA.hxx b/Private/NewBoot/BootKit/HW/SATA.hxx
index b061a1aa..24c08c01 100644
--- a/Private/NewBoot/BootKit/HW/SATA.hxx
+++ b/Private/NewBoot/BootKit/HW/SATA.hxx
@@ -7,7 +7,7 @@
 #pragma once
 
 #include <CompilerKit/CompilerKit.hxx>
-#include <Builtins/AHCI/Defines.hxx>
+#include <Builtins/AHCI/AHCI.hxx>
 
 class BootDeviceSATA final {
  public:
diff --git a/Private/Source/DriveManager.cxx b/Private/Source/DriveManager.cxx
index 46c6f150..86478831 100644
--- a/Private/Source/DriveManager.cxx
+++ b/Private/Source/DriveManager.cxx
@@ -6,8 +6,8 @@
 
 #include <KernelKit/DebugOutput.hpp>
 #include <KernelKit/DriveManager.hxx>
-#include <Builtins/ATA/Defines.hxx>
-#include <Builtins/AHCI/Defines.hxx>
+#include <Builtins/ATA/ATA.hxx>
+#include <Builtins/AHCI/AHCI.hxx>
 #include <NewKit/Utils.hpp>
 
 /// @file DriveManager.cxx
diff --git a/Public/Developer/SystemLib/Headers/Dialog.h b/Public/Developer/SystemLib/Headers/Dialog.h
index 0c0e4dbc..872eae5d 100644
--- a/Public/Developer/SystemLib/Headers/Dialog.h
+++ b/Public/Developer/SystemLib/Headers/Dialog.h
@@ -12,7 +12,7 @@ struct _DialogPort;
 struct _DialogPoint;
 
 /// @brief Dialog procedure type.
-typedef VoidType(*WmDialogProc)(struct _DialogPort* port, UInt32Type msg, UIntPtrType pParam, UIntPtrType iParam);
+typedef VoidType(*WmDialogFn)(struct _DialogPort* port, UInt32Type msg, UIntPtrType pParam, UIntPtrType iParam);
 
 /// @brief A point, can represent the size, position of a window.
 typedef struct _DialogPoint {
@@ -25,7 +25,7 @@ typedef struct _DialogPort {
   BooleanType dlgVisible;
   BooleanType dlgMoving;
   DialogPoint dlgPosition;
-  WmDialogProc dlgProc;
+  WmDialogFn dlgProc;
   struct _WindowPort* parentPort;
 } DialogPort;
 
diff --git a/Public/Developer/SystemLib/Headers/Window.h b/Public/Developer/SystemLib/Headers/Window.h
index 58b10d8e..ad626e2e 100644
--- a/Public/Developer/SystemLib/Headers/Window.h
+++ b/Public/Developer/SystemLib/Headers/Window.h
@@ -27,7 +27,7 @@ struct _WmPoint;
 typedef QWordType DCRef;
 
 /// @brief Window procedure type.
-typedef VoidType(*WmWindowProc)(struct _WindowPort* port, UInt32Type msg, UIntPtrType pParam, UIntPtrType iParam);
+typedef VoidType(*WmWindowFn)(struct _WindowPort* port, UInt32Type msg, UIntPtrType pParam, UIntPtrType iParam);
 
 /// @brief A point, can represent the size, position of a window.
 typedef struct _WmPoint {
@@ -48,7 +48,7 @@ typedef struct _WindowPort {
   WmPoint windowSize;
   BooleanType windowInvalidate;
   DWordType windowClearColor;
-  WmWindowProc windowProc;
+  WmWindowFn windowProc;
   struct _WindowPort* windowMenuPort; ///! Attached menu to it.
   struct _WindowPort* windowParentPort;
 } WindowPort;
@@ -60,7 +60,7 @@ typedef struct _ControlPort {
   BooleanType controlVisible;
   BooleanType controlMoving;
   WmPoint controlPosition;
-  WmWindowProc controlProc;
+  WmWindowFn controlProc;
   WindowPort* parentPort;
 } ControlPort;
 
@@ -156,17 +156,3 @@ CA_EXTERN_C VoidType      WmReleaseMenu(WindowPort* port);
 /// @param where to move.
 /// @return error code.
 CA_EXTERN_C Int32Type     WmMoveWindow(WindowPort* id, WmPoint where);
-
-/// @brief Get last message.
-/// @param id 
-/// @return 
-CA_EXTERN_C Int64Type     WmGetMessage(WindowPort* id);
-
-/// @brief Translate message internally.
-/// @return 
-CA_EXTERN_C VoidType      WmTranslateMessage(WindowPort* port, Int64Type msg);
-
-/// @brief Dispatch message to event queue.
-/// @param id 
-/// @return 
-CA_EXTERN_C Int32Type     WmDispatchMessage(WindowPort* id);