Kernel: :boom: breaking changes, Update API and the HCORE based

macros, rename HCore to NewOS.

Signed-off-by: Amlal El Mahrouss <amlal@el-mahrouss-logic.com>

9 files changed, 190 insertions, 190 deletions

diff --git a/Private/Builtins/ACPI/ACPI.hxx b/Private/Builtins/ACPI/ACPI.hxx
index c0076c5e..f0412b9e 100644
--- a/Private/Builtins/ACPI/ACPI.hxx
+++ b/Private/Builtins/ACPI/ACPI.hxx
@@ -13,7 +13,7 @@
 
 #include <NewKit/Defines.hpp>
 
-namespace HCore {
+namespace NewOS {
 class SDT {
  public:
   Char Signature[4];
@@ -62,6 +62,6 @@ class Address {
   UInt8 Reserved;
   UIntPtr Address;
 };
-}  // namespace HCore
+}  // namespace NewOS
 
 #endif  // !__ACPI__
diff --git a/Private/Builtins/ACPI/ACPIFactoryInterface.hxx b/Private/Builtins/ACPI/ACPIFactoryInterface.hxx
index b81a8dde..6d2325fe 100644
--- a/Private/Builtins/ACPI/ACPIFactoryInterface.hxx
+++ b/Private/Builtins/ACPI/ACPIFactoryInterface.hxx
@@ -12,7 +12,7 @@
 #include <NewKit/Defines.hpp>
 #include <NewKit/Ref.hpp>
 
-namespace HCore {
+namespace NewOS {
 class ACPIFactoryInterface final {
  public:
   explicit ACPIFactoryInterface(voidPtr rsdPtr);
@@ -47,6 +47,6 @@ class ACPIFactoryInterface final {
   SSizeT m_Entries;  // number of entries, -1 tells that no invalid entries were
                      // found.
 };
-}  // namespace HCore
+}  // namespace NewOS
 
 #endif // !__ACPI_MANAGER__
diff --git a/Private/Builtins/AHCI/Defines.hxx b/Private/Builtins/AHCI/Defines.hxx
index e1aa72ae..23c86049 100644
--- a/Private/Builtins/AHCI/Defines.hxx
+++ b/Private/Builtins/AHCI/Defines.hxx
@@ -45,168 +45,168 @@ typedef enum {
 
 typedef struct FisRegH2D final {
   // DWORD 0
-  HCore::UInt8 fisType;  // FIS_TYPE_REG_H2D
+  NewOS::UInt8 fisType;  // FIS_TYPE_REG_H2D
 
-  HCore::UInt8 portMul : 4;    // Port multiplier
-  HCore::UInt8 reserved0 : 3;  // Reserved
-  HCore::UInt8 cmdOrCtrl : 1;  // 1: Command, 0: Control
+  NewOS::UInt8 portMul : 4;    // Port multiplier
+  NewOS::UInt8 reserved0 : 3;  // Reserved
+  NewOS::UInt8 cmdOrCtrl : 1;  // 1: Command, 0: Control
 
-  HCore::UInt8 command;   // Command register
-  HCore::UInt8 featurel;  // Feature register, 7:0
+  NewOS::UInt8 command;   // Command register
+  NewOS::UInt8 featurel;  // Feature register, 7:0
 
   // DWORD 1
-  HCore::UInt8 lba0;    // LBA low register, 7:0
-  HCore::UInt8 lba1;    // LBA mid register, 15:8
-  HCore::UInt8 lba2;    // LBA high register, 23:16
-  HCore::UInt8 device;  // Device register
+  NewOS::UInt8 lba0;    // LBA low register, 7:0
+  NewOS::UInt8 lba1;    // LBA mid register, 15:8
+  NewOS::UInt8 lba2;    // LBA high register, 23:16
+  NewOS::UInt8 device;  // Device register
 
   // DWORD 2
-  HCore::UInt8 lba3;         // LBA register, 31:24
-  HCore::UInt8 lba4;         // LBA register, 39:32
-  HCore::UInt8 lba5;         // LBA register, 47:40
-  HCore::UInt8 featureHigh;  // Feature register, 15:8
+  NewOS::UInt8 lba3;         // LBA register, 31:24
+  NewOS::UInt8 lba4;         // LBA register, 39:32
+  NewOS::UInt8 lba5;         // LBA register, 47:40
+  NewOS::UInt8 featureHigh;  // Feature register, 15:8
 
   // DWORD 3
-  HCore::UInt8 countLow;   // Count register, 7:0
-  HCore::UInt8 countHigh;  // Count register, 15:8
-  HCore::UInt8 icc;        // Isochronous command completion
-  HCore::UInt8 control;    // Control register
+  NewOS::UInt8 countLow;   // Count register, 7:0
+  NewOS::UInt8 countHigh;  // Count register, 15:8
+  NewOS::UInt8 icc;        // Isochronous command completion
+  NewOS::UInt8 control;    // Control register
 
   // DWORD 4
-  HCore::UInt8 reserved1[4];  // Reserved
+  NewOS::UInt8 reserved1[4];  // Reserved
 } FisRegH2D;
 
 typedef struct FisRegD2H final {
   // DWORD 0
-  HCore::UInt8 fisType;  // FIS_TYPE_REG_D2H
+  NewOS::UInt8 fisType;  // FIS_TYPE_REG_D2H
 
-  HCore::UInt8 portMul : 4;       // Port multiplier
-  HCore::UInt8 reserved0 : 2;     // Reserved
-  HCore::UInt8 interruptBit : 1;  // Interrupt bit
-  HCore::UInt8 reserved1 : 1;     // Reserved
+  NewOS::UInt8 portMul : 4;       // Port multiplier
+  NewOS::UInt8 reserved0 : 2;     // Reserved
+  NewOS::UInt8 interruptBit : 1;  // Interrupt bit
+  NewOS::UInt8 reserved1 : 1;     // Reserved
 
-  HCore::UInt8 status;  // Status register
-  HCore::UInt8 error;   // Error register
+  NewOS::UInt8 status;  // Status register
+  NewOS::UInt8 error;   // Error register
 
   // DWORD 1
-  HCore::UInt8 lba0;    // LBA low register, 7:0
-  HCore::UInt8 lba1;    // LBA mid register, 15:8
-  HCore::UInt8 lba2;    // LBA high register, 23:16
-  HCore::UInt8 device;  // Device register
+  NewOS::UInt8 lba0;    // LBA low register, 7:0
+  NewOS::UInt8 lba1;    // LBA mid register, 15:8
+  NewOS::UInt8 lba2;    // LBA high register, 23:16
+  NewOS::UInt8 device;  // Device register
 
   // DWORD 2
-  HCore::UInt8 lba3;  // LBA register, 31:24
-  HCore::UInt8 lba4;  // LBA register, 39:32
-  HCore::UInt8 lba5;  // LBA register, 47:40
-  HCore::UInt8 rsv2;  // Reserved
+  NewOS::UInt8 lba3;  // LBA register, 31:24
+  NewOS::UInt8 lba4;  // LBA register, 39:32
+  NewOS::UInt8 lba5;  // LBA register, 47:40
+  NewOS::UInt8 rsv2;  // Reserved
 
   // DWORD 3
-  HCore::UInt8 countLow;   // Count register, 7:0
-  HCore::UInt8 countHigh;  // Count register, 15:8
-  HCore::UInt8 rsv3[2];    // Reserved
+  NewOS::UInt8 countLow;   // Count register, 7:0
+  NewOS::UInt8 countHigh;  // Count register, 15:8
+  NewOS::UInt8 rsv3[2];    // Reserved
 
   // DWORD 4
-  HCore::UInt8 rsv4[4];  // Reserved
+  NewOS::UInt8 rsv4[4];  // Reserved
 } FisRegD2H;
 
 typedef struct FisData final {
   // DWORD 0
-  HCore::UInt8 fisType;  // FIS_TYPE_DATA
+  NewOS::UInt8 fisType;  // FIS_TYPE_DATA
 
-  HCore::UInt8 portMul : 4;    // Port multiplier
-  HCore::UInt8 reserved0 : 4;  // Reserved
+  NewOS::UInt8 portMul : 4;    // Port multiplier
+  NewOS::UInt8 reserved0 : 4;  // Reserved
 
-  HCore::UInt8 reserved1[2];  // Reserved
+  NewOS::UInt8 reserved1[2];  // Reserved
 
   // DWORD 1 ~ N
-  HCore::UInt32 data[1];  // Payload
+  NewOS::UInt32 data[1];  // Payload
 } FisData;
 
 typedef struct FisPioSetup final {
   // DWORD 0
-  HCore::UInt8 fisType;  // FIS_TYPE_PIO_SETUP
+  NewOS::UInt8 fisType;  // FIS_TYPE_PIO_SETUP
 
-  HCore::UInt8 portMul : 4;       // Port multiplier
-  HCore::UInt8 reserved0 : 1;     // Reserved
-  HCore::UInt8 d : 1;             // Data transfer direction, 1 - device to host
-  HCore::UInt8 interruptBit : 1;  // Interrupt bit
-  HCore::UInt8 reserved1 : 1;
+  NewOS::UInt8 portMul : 4;       // Port multiplier
+  NewOS::UInt8 reserved0 : 1;     // Reserved
+  NewOS::UInt8 d : 1;             // Data transfer direction, 1 - device to host
+  NewOS::UInt8 interruptBit : 1;  // Interrupt bit
+  NewOS::UInt8 reserved1 : 1;
 
-  HCore::UInt8 status;  // Status register
-  HCore::UInt8 error;   // Error register
+  NewOS::UInt8 status;  // Status register
+  NewOS::UInt8 error;   // Error register
 
   // DWORD 1
-  HCore::UInt8 lba0;    // LBA low register, 7:0
-  HCore::UInt8 lba1;    // LBA mid register, 15:8
-  HCore::UInt8 lba2;    // LBA high register, 23:16
-  HCore::UInt8 device;  // Device register
+  NewOS::UInt8 lba0;    // LBA low register, 7:0
+  NewOS::UInt8 lba1;    // LBA mid register, 15:8
+  NewOS::UInt8 lba2;    // LBA high register, 23:16
+  NewOS::UInt8 device;  // Device register
 
   // DWORD 2
-  HCore::UInt8 lba3;  // LBA register, 31:24
-  HCore::UInt8 lba4;  // LBA register, 39:32
-  HCore::UInt8 lba5;  // LBA register, 47:40
-  HCore::UInt8 rsv2;  // Reserved
+  NewOS::UInt8 lba3;  // LBA register, 31:24
+  NewOS::UInt8 lba4;  // LBA register, 39:32
+  NewOS::UInt8 lba5;  // LBA register, 47:40
+  NewOS::UInt8 rsv2;  // Reserved
 
   // DWORD 3
-  HCore::UInt8 countLow;   // Count register, 7:0
-  HCore::UInt8 countHigh;  // Count register, 15:8
-  HCore::UInt8 rsv3;       // Reserved
-  HCore::UInt8 eStatus;    // New value of status register
+  NewOS::UInt8 countLow;   // Count register, 7:0
+  NewOS::UInt8 countHigh;  // Count register, 15:8
+  NewOS::UInt8 rsv3;       // Reserved
+  NewOS::UInt8 eStatus;    // New value of status register
 
   // DWORD 4
-  HCore::UInt16 tc;      // Transfer count
-  HCore::UInt8 rsv4[2];  // Reserved
+  NewOS::UInt16 tc;      // Transfer count
+  NewOS::UInt8 rsv4[2];  // Reserved
 } FisPioSetup;
 
 typedef struct FisDmaSetup final {
   // DWORD 0
-  HCore::UInt8 fisType;  // FIS_TYPE_DMA_SETUP
+  NewOS::UInt8 fisType;  // FIS_TYPE_DMA_SETUP
 
-  HCore::UInt8 portMul : 4;       // Port multiplier
-  HCore::UInt8 reserved0 : 1;     // Reserved
-  HCore::UInt8 dtd : 1;           // Data transfer direction, 1 - device to host
-  HCore::UInt8 interruptBit : 1;  // Interrupt bit
-  HCore::UInt8
+  NewOS::UInt8 portMul : 4;       // Port multiplier
+  NewOS::UInt8 reserved0 : 1;     // Reserved
+  NewOS::UInt8 dtd : 1;           // Data transfer direction, 1 - device to host
+  NewOS::UInt8 interruptBit : 1;  // Interrupt bit
+  NewOS::UInt8
       autoEnable : 1;  // Auto-activate. Specifies if DMA Activate FIS is needed
 
-  HCore::UInt8 reserved1[2];  // Reserved
+  NewOS::UInt8 reserved1[2];  // Reserved
 
   // DWORD 1&2
-  HCore::UInt64 dmaBufferId;  // DMA Buffer Identifier. Used to Identify DMA buffer in
+  NewOS::UInt64 dmaBufferId;  // DMA Buffer Identifier. Used to Identify DMA buffer in
                        // host memory. SATA Spec says host specific and not in
                        // Spec. Trying AHCI spec might work.
 
   // DWORD 3
-  HCore::UInt32 rsvd;  // More reserved
+  NewOS::UInt32 rsvd;  // More reserved
 
   // DWORD 4
-  HCore::UInt32 dmabufOffset;  // Byte offset into buffer. First 2 bits must be 0
+  NewOS::UInt32 dmabufOffset;  // Byte offset into buffer. First 2 bits must be 0
 
   // DWORD 5
-  HCore::UInt32 transferCount;  // Number of bytes to transfer. Bit 0 must be 0
+  NewOS::UInt32 transferCount;  // Number of bytes to transfer. Bit 0 must be 0
 
   // DWORD 6
-  HCore::UInt32 reserved3;  // Reserved
+  NewOS::UInt32 reserved3;  // Reserved
 } FisDmaSetup;
 
 typedef struct FisDevBits final {
   // DWORD 0
-  HCore::UInt8 fisType;  // FIS_TYPE_DMA_SETUP (A1h)
+  NewOS::UInt8 fisType;  // FIS_TYPE_DMA_SETUP (A1h)
 
-  HCore::UInt8 reserved0 : 5;  // Reserved
-  HCore::UInt8 r0 : 1;
-  HCore::UInt8 interruptBit : 1;
-  HCore::UInt8 n : 1;
+  NewOS::UInt8 reserved0 : 5;  // Reserved
+  NewOS::UInt8 r0 : 1;
+  NewOS::UInt8 interruptBit : 1;
+  NewOS::UInt8 n : 1;
 
-  HCore::UInt8 statusLow : 3;
-  HCore::UInt8 r1 : 1;
-  HCore::UInt8 statusHigh : 3;
+  NewOS::UInt8 statusLow : 3;
+  NewOS::UInt8 r1 : 1;
+  NewOS::UInt8 statusHigh : 3;
 
-  HCore::UInt8 r2 : 1;
-  HCore::UInt8 error;
+  NewOS::UInt8 r2 : 1;
+  NewOS::UInt8 error;
 
   // DWORD 1
-  HCore::UInt32 act;
+  NewOS::UInt32 act;
 } FisDevBits;
 
 /// \brief Enable AHCI device bit in GHC register.
@@ -215,101 +215,101 @@ typedef struct FisDevBits final {
 #endif  //! ifndef kAhciGHC_AE
 
 typedef struct HbaPort final {
-  HCore::UInt32 clb;            // 0x00, command list base address, 1K-byte aligned
-  HCore::UInt32 clbu;           // 0x04, command list base address upper 32 bits
-  HCore::UInt32 fb;             // 0x08, FIS base address, 256-byte aligned
-  HCore::UInt32 fbu;            // 0x0C, FIS base address upper 32 bits
-  HCore::UInt32 is;             // 0x10, interrupt status
-  HCore::UInt32 ie;             // 0x14, interrupt enable
-  HCore::UInt32 cmd;            // 0x18, command and status
-  HCore::UInt32 reserved0;      // 0x1C, Reserved
-  HCore::UInt32 tfd;            // 0x20, task file data
-  HCore::UInt32 sig;            // 0x24, signature
-  HCore::UInt32 ssts;           // 0x28, SATA status (SCR0:SStatus)
-  HCore::UInt32 sctl;           // 0x2C, SATA control (SCR2:SControl)
-  HCore::UInt32 serr;           // 0x30, SATA error (SCR1:SError)
-  HCore::UInt32 sact;           // 0x34, SATA active (SCR3:SActive)
-  HCore::UInt32 ci;             // 0x38, command issue
-  HCore::UInt32 sntf;           // 0x20, SATA notification (SCR4:SNotification)
-  HCore::UInt32 fbs;            // 0x40, FIS-based switch control
-  HCore::UInt32 reserved1[11];  // 0x44 ~ 0x6F, Reserved
-  HCore::UInt32 vendor[4];      // 0x70 ~ 0x7F, vendor specific
+  NewOS::UInt32 clb;            // 0x00, command list base address, 1K-byte aligned
+  NewOS::UInt32 clbu;           // 0x04, command list base address upper 32 bits
+  NewOS::UInt32 fb;             // 0x08, FIS base address, 256-byte aligned
+  NewOS::UInt32 fbu;            // 0x0C, FIS base address upper 32 bits
+  NewOS::UInt32 is;             // 0x10, interrupt status
+  NewOS::UInt32 ie;             // 0x14, interrupt enable
+  NewOS::UInt32 cmd;            // 0x18, command and status
+  NewOS::UInt32 reserved0;      // 0x1C, Reserved
+  NewOS::UInt32 tfd;            // 0x20, task file data
+  NewOS::UInt32 sig;            // 0x24, signature
+  NewOS::UInt32 ssts;           // 0x28, SATA status (SCR0:SStatus)
+  NewOS::UInt32 sctl;           // 0x2C, SATA control (SCR2:SControl)
+  NewOS::UInt32 serr;           // 0x30, SATA error (SCR1:SError)
+  NewOS::UInt32 sact;           // 0x34, SATA active (SCR3:SActive)
+  NewOS::UInt32 ci;             // 0x38, command issue
+  NewOS::UInt32 sntf;           // 0x20, SATA notification (SCR4:SNotification)
+  NewOS::UInt32 fbs;            // 0x40, FIS-based switch control
+  NewOS::UInt32 reserved1[11];  // 0x44 ~ 0x6F, Reserved
+  NewOS::UInt32 vendor[4];      // 0x70 ~ 0x7F, vendor specific
 } HbaPort;
 
 typedef struct HbaMem final {
   // 0x00 - 0x2B, Generic Host Control
-  HCore::UInt32 cap;      // 0x00, Host capability
-  HCore::UInt32 ghc;      // 0x04, Global host control
-  HCore::UInt32 is;       // 0x08, Interrupt status
-  HCore::UInt32 pi;       // 0x0C, Port implemented
-  HCore::UInt32 vs;       // 0x10, Version
-  HCore::UInt32 ccc_ctl;  // 0x14, Command completion coalescing control
-  HCore::UInt32 ccc_pts;  // 0x18, Command completion coalescing ports
-  HCore::UInt32 em_loc;   // 0x1C, Enclosure management location
-  HCore::UInt32 em_ctl;   // 0x20, Enclosure management control
-  HCore::UInt32 cap2;     // 0x24, Host capabilities extended
-  HCore::UInt32 bohc;     // 0x28, BIOS/OS handoff control and status
-
-  HCore::UInt16 rsv;
-  HCore::UInt32 resv2;
+  NewOS::UInt32 cap;      // 0x00, Host capability
+  NewOS::UInt32 ghc;      // 0x04, Global host control
+  NewOS::UInt32 is;       // 0x08, Interrupt status
+  NewOS::UInt32 pi;       // 0x0C, Port implemented
+  NewOS::UInt32 vs;       // 0x10, Version
+  NewOS::UInt32 ccc_ctl;  // 0x14, Command completion coalescing control
+  NewOS::UInt32 ccc_pts;  // 0x18, Command completion coalescing ports
+  NewOS::UInt32 em_loc;   // 0x1C, Enclosure management location
+  NewOS::UInt32 em_ctl;   // 0x20, Enclosure management control
+  NewOS::UInt32 cap2;     // 0x24, Host capabilities extended
+  NewOS::UInt32 bohc;     // 0x28, BIOS/OS handoff control and status
+
+  NewOS::UInt16 rsv;
+  NewOS::UInt32 resv2;
 
   HbaPort ports[1];  // 1 ~ 32
 } HbaMem;
 
 typedef struct HbaCmdHeader final {
   // DW0
-  HCore::UInt8 cfl : 5;           // Command FIS length in DWORDS, 2 ~ 16
-  HCore::UInt8 atapi : 1;         // ATAPI
-  HCore::UInt8 write : 1;         // Write, 1: H2D, 0: D2H
-  HCore::UInt8 prefetchable : 1;  // Prefetchable
+  NewOS::UInt8 cfl : 5;           // Command FIS length in DWORDS, 2 ~ 16
+  NewOS::UInt8 atapi : 1;         // ATAPI
+  NewOS::UInt8 write : 1;         // Write, 1: H2D, 0: D2H
+  NewOS::UInt8 prefetchable : 1;  // Prefetchable
 
-  HCore::UInt8 reset : 1;      // Reset
-  HCore::UInt8 BIST : 1;       // BIST
-  HCore::UInt8 clear : 1;      // Clear busy upon R_OK
-  HCore::UInt8 reserved0 : 1;  // Reserved
-  HCore::UInt8 pmp : 4;        // Port multiplier port
+  NewOS::UInt8 reset : 1;      // Reset
+  NewOS::UInt8 BIST : 1;       // BIST
+  NewOS::UInt8 clear : 1;      // Clear busy upon R_OK
+  NewOS::UInt8 reserved0 : 1;  // Reserved
+  NewOS::UInt8 pmp : 4;        // Port multiplier port
 
-  HCore::UInt16 prdtl;           // Physical region descriptor table length in entries
-  volatile HCore::UInt32 prdbc;  // Physical region descriptor byte count transferred
+  NewOS::UInt16 prdtl;           // Physical region descriptor table length in entries
+  volatile NewOS::UInt32 prdbc;  // Physical region descriptor byte count transferred
 
-  HCore::UInt32 ctba;   // Command table descriptor base address
-  HCore::UInt32 ctbau;  // Command table descriptor base address upper 32 bits
+  NewOS::UInt32 ctba;   // Command table descriptor base address
+  NewOS::UInt32 ctbau;  // Command table descriptor base address upper 32 bits
 
-  HCore::UInt32 reserved1[4];  // Reserved
+  NewOS::UInt32 reserved1[4];  // Reserved
 } HbaCmdHeader;
 
 typedef struct HbaFis final {
   // 0x00
   FisDmaSetup dsfis;  // DMA Setup FIS
-  HCore::UInt8 pad0[4];
+  NewOS::UInt8 pad0[4];
   // 0x20
   FisPioSetup psfis;  // PIO Setup FIS
-  HCore::UInt8 pad1[12];
+  NewOS::UInt8 pad1[12];
   // 0x40
   FisRegD2H rfis;  // Register – Device to Host FIS
-  HCore::UInt8 pad2[4];
+  NewOS::UInt8 pad2[4];
   // 0x58
   FisDevBits sdbfis;  // Set Device Bit FIS
   // 0x60
-  HCore::UInt8 ufis[64];
+  NewOS::UInt8 ufis[64];
   // 0xA0
-  HCore::UInt8 rsv[0x100 - 0xA0];
+  NewOS::UInt8 rsv[0x100 - 0xA0];
 } HbaFis;
 
 typedef struct HbaPrdtEntry final {
-  HCore::UInt32 dba;        // Data base address
-  HCore::UInt32 dbau;       // Data base address upper 32 bits
-  HCore::UInt32 reserved0;  // Reserved
+  NewOS::UInt32 dba;        // Data base address
+  NewOS::UInt32 dbau;       // Data base address upper 32 bits
+  NewOS::UInt32 reserved0;  // Reserved
   // DW3
-  HCore::UInt32 dbc : 22;          // Byte count, 4M max
-  HCore::UInt32 reserved1 : 9;     // Reserved
-  HCore::UInt32 interruptBit : 1;  // Interrupt on completion
+  NewOS::UInt32 dbc : 22;          // Byte count, 4M max
+  NewOS::UInt32 reserved1 : 9;     // Reserved
+  NewOS::UInt32 interruptBit : 1;  // Interrupt on completion
 } HbaPrdtEntry;
 
 typedef struct HbaCmdTbl final {
-  HCore::UInt8 cfis[64];  // Command FIS
-  HCore::UInt8 acmd[16];  // ATAPI command, 12 or 16 bytes
-  HCore::UInt8 rsv[48];   // Reserved
+  NewOS::UInt8 cfis[64];  // Command FIS
+  NewOS::UInt8 acmd[16];  // ATAPI command, 12 or 16 bytes
+  NewOS::UInt8 rsv[48];   // Reserved
   struct HbaPrdtEntry prdtEntries[1];  // Physical region descriptor table entries, 0 ~ 65535
 } HbaCmdTbl;
 
@@ -320,14 +320,14 @@ typedef struct HbaCmdTbl final {
 /// @brief Initializes an AHCI disk.
 /// @param PortsImplemented the amount of port that have been detected.
 /// @return 
-HCore::Boolean drv_ahci_init(HCore::UInt16& PortsImplemented);
+NewOS::Boolean drv_ahci_init(NewOS::UInt16& PortsImplemented);
 
-HCore::Boolean drv_ahci_detected(HCore::Void);
+NewOS::Boolean drv_ahci_detected(NewOS::Void);
 
-HCore::Void drv_ahci_read(HCore::UInt64 Lba, HCore::UInt16 IO, HCore::UInt8 Master, HCore::Char* Buf,
-                   HCore::SizeT SectorSz, HCore::SizeT Size);
+NewOS::Void drv_ahci_read(NewOS::UInt64 Lba, NewOS::UInt16 IO, NewOS::UInt8 Master, NewOS::Char* Buf,
+                   NewOS::SizeT SectorSz, NewOS::SizeT Size);
 
-HCore::Void drv_ahci_write(HCore::UInt64 Lba, HCore::UInt16 IO, HCore::UInt8 Master, HCore::Char* Buf,
-                    HCore::SizeT SectorSz, HCore::SizeT Size);
+NewOS::Void drv_ahci_write(NewOS::UInt64 Lba, NewOS::UInt16 IO, NewOS::UInt8 Master, NewOS::Char* Buf,
+                    NewOS::SizeT SectorSz, NewOS::SizeT Size);
 
 #endif // ifdef __KERNEL__
diff --git a/Private/Builtins/ATA/Defines.hxx b/Private/Builtins/ATA/Defines.hxx
index fbb7c63c..0a07bc68 100644
--- a/Private/Builtins/ATA/Defines.hxx
+++ b/Private/Builtins/ATA/Defines.hxx
@@ -127,19 +127,19 @@ enum {
 
 #ifdef __KERNEL__
 
-HCore::Boolean drv_ata_init(HCore::UInt16 Bus, HCore::UInt8 Drive, HCore::UInt16& OutBus,
-                      HCore::UInt8& OutMaster);
+NewOS::Boolean drv_ata_init(NewOS::UInt16 Bus, NewOS::UInt8 Drive, NewOS::UInt16& OutBus,
+                      NewOS::UInt8& OutMaster);
 
-HCore::Boolean drv_ata_detected(HCore::Void);
+NewOS::Boolean drv_ata_detected(NewOS::Void);
 
-HCore::Void drv_ata_select(HCore::UInt16 Bus);
+NewOS::Void drv_ata_select(NewOS::UInt16 Bus);
 
-HCore::Boolean drv_ata_wait_io(HCore::UInt16 IO);
+NewOS::Boolean drv_ata_wait_io(NewOS::UInt16 IO);
 
-HCore::Void drv_ata_read(HCore::UInt64 Lba, HCore::UInt16 IO, HCore::UInt8 Master, HCore::Char* Buf,
-                   HCore::SizeT SectorSz, HCore::SizeT Size);
+NewOS::Void drv_ata_read(NewOS::UInt64 Lba, NewOS::UInt16 IO, NewOS::UInt8 Master, NewOS::Char* Buf,
+                   NewOS::SizeT SectorSz, NewOS::SizeT Size);
 
-HCore::Void drv_ata_write(HCore::UInt64 Lba, HCore::UInt16 IO, HCore::UInt8 Master, HCore::Char* Buf,
-                    HCore::SizeT SectorSz, HCore::SizeT Size);
+NewOS::Void drv_ata_write(NewOS::UInt64 Lba, NewOS::UInt16 IO, NewOS::UInt8 Master, NewOS::Char* Buf,
+                    NewOS::SizeT SectorSz, NewOS::SizeT Size);
 
 #endif // ifdef __KERNEL__
diff --git a/Private/Builtins/PS2/PS2MouseInterface.hxx b/Private/Builtins/PS2/PS2MouseInterface.hxx
index 2be85af1..8ef47581 100644
--- a/Private/Builtins/PS2/PS2MouseInterface.hxx
+++ b/Private/Builtins/PS2/PS2MouseInterface.hxx
@@ -17,7 +17,7 @@
 #include <CompilerKit/CompilerKit.hxx>
 #include <NewKit/Defines.hpp>
 
-namespace HCore {
+namespace NewOS {
 /// @brief PS/2 Mouse driver interface
 class PS2MouseInterface final {
  public:
@@ -98,4 +98,4 @@ class PS2MouseInterface final {
     return HAL::In8(0x60);
   }
 };
-}  // namespace HCore
+}  // namespace NewOS
diff --git a/Private/Builtins/README.TXT b/Private/Builtins/README.TXT
index 2e341e5d..4cb791f7 100644
--- a/Private/Builtins/README.TXT
+++ b/Private/Builtins/README.TXT
@@ -1,12 +1,12 @@
 ==============
-HCore Builtins
+NewOS Builtins
 ==============
 
 ===============
 What are these?
 ===============
 
-These are HCore builtins device drivers.
+These are NewOS builtins device drivers.
 
 ===========
 Maintainers
diff --git a/Private/Builtins/Toolbox/Toolbox.hxx b/Private/Builtins/Toolbox/Toolbox.hxx
index ebd8fc1e..f831acb5 100644
--- a/Private/Builtins/Toolbox/Toolbox.hxx
+++ b/Private/Builtins/Toolbox/Toolbox.hxx
@@ -8,11 +8,11 @@
 
 #include <NewKit/Defines.hpp>
 
-EXTERN_C HCore::Void _hal_init_mouse();
-EXTERN_C HCore::Boolean _hal_draw_mouse();
-EXTERN_C HCore::Void _hal_handle_mouse();
-EXTERN_C HCore::Boolean _hal_left_button_pressed();
-EXTERN_C HCore::Boolean _hal_middle_button_pressed();
-EXTERN_C HCore::Boolean _hal_right_button_pressed();
+EXTERN_C NewOS::Void _hal_init_mouse();
+EXTERN_C NewOS::Boolean _hal_draw_mouse();
+EXTERN_C NewOS::Void _hal_handle_mouse();
+EXTERN_C NewOS::Boolean _hal_left_button_pressed();
+EXTERN_C NewOS::Boolean _hal_middle_button_pressed();
+EXTERN_C NewOS::Boolean _hal_right_button_pressed();
 
 #include <Builtins/Toolbox/Utils.hxx>
diff --git a/Private/Builtins/Toolbox/Utils.hxx b/Private/Builtins/Toolbox/Utils.hxx
index 7dec8608..29ca585a 100644
--- a/Private/Builtins/Toolbox/Utils.hxx
+++ b/Private/Builtins/Toolbox/Utils.hxx
@@ -4,7 +4,7 @@
 // Last Rev
 // Sat Feb 24 CET 2024
 
-#define ToolboxInitRsrc() HCore::SizeT uA = 0
+#define ToolboxInitRsrc() NewOS::SizeT uA = 0
 
 #define kClearClr RGB(00, 00, 00)
 
@@ -14,17 +14,17 @@
 #define ToolboxDrawRsrc(ImgPtr, _Height, _Width, BaseX, BaseY) \
   uA = 0;                                                                   \
                                                                             \
-  for (HCore::SizeT i = BaseX; i < _Height + BaseX; ++i) {                  \
-    for (HCore::SizeT u = BaseY; u < _Width + BaseY; ++u) {                 \
+  for (NewOS::SizeT i = BaseX; i < _Height + BaseX; ++i) {                  \
+    for (NewOS::SizeT u = BaseY; u < _Width + BaseY; ++u) {                 \
       if (ImgPtr[uA] == 0) {                                                \
-        *(((volatile HCore::UInt32*)(kHandoverHeader->f_GOP.f_The +          \
+        *(((volatile NewOS::UInt32*)(kHandoverHeader->f_GOP.f_The +          \
                                      4 *                                    \
                                          kHandoverHeader->f_GOP              \
                                              .f_PixelPerLine *              \
                                          i +                                \
                                      4 * u))) |= ImgPtr[uA];                \
       } else {                                                              \
-        *(((volatile HCore::UInt32*)(kHandoverHeader->f_GOP.f_The +          \
+        *(((volatile NewOS::UInt32*)(kHandoverHeader->f_GOP.f_The +          \
                                      4 *                                    \
                                          kHandoverHeader->f_GOP              \
                                              .f_PixelPerLine *              \
@@ -40,9 +40,9 @@
 /// @brief Cleans a resource.
 #define ToolboxClearZone(_Height, _Width, BaseX, BaseY) \
                                                                             \
-  for (HCore::SizeT i = BaseX; i < _Height + BaseX; ++i) {                  \
-    for (HCore::SizeT u = BaseY; u < _Width + BaseY; ++u) {                 \
-        *(((volatile HCore::UInt32*)(kHandoverHeader->f_GOP.f_The +          \
+  for (NewOS::SizeT i = BaseX; i < _Height + BaseX; ++i) {                  \
+    for (NewOS::SizeT u = BaseY; u < _Width + BaseY; ++u) {                 \
+        *(((volatile NewOS::UInt32*)(kHandoverHeader->f_GOP.f_The +          \
                                      4 *                                    \
                                          kHandoverHeader->f_GOP              \
                                              .f_PixelPerLine *              \
@@ -55,9 +55,9 @@
 /// @brief Draws inside a zone.
 #define ToolboxDrawZone(_Clr, _Height, _Width, BaseX, BaseY) \
                                                                             \
-  for (HCore::SizeT i = BaseX; i < _Width + BaseX; ++i) {                  \
-    for (HCore::SizeT u = BaseY; u < _Height + BaseY; ++u) {                 \
-        *(((volatile HCore::UInt32*)(kHandoverHeader->f_GOP.f_The +          \
+  for (NewOS::SizeT i = BaseX; i < _Width + BaseX; ++i) {                  \
+    for (NewOS::SizeT u = BaseY; u < _Height + BaseY; ++u) {                 \
+        *(((volatile NewOS::UInt32*)(kHandoverHeader->f_GOP.f_The +          \
                                      4 *                                    \
                                          kHandoverHeader->f_GOP              \
                                              .f_PixelPerLine *              \
diff --git a/Private/Builtins/XHCI/Defines.hxx b/Private/Builtins/XHCI/Defines.hxx
index 32eb8cca..519d6635 100644
--- a/Private/Builtins/XHCI/Defines.hxx
+++ b/Private/Builtins/XHCI/Defines.hxx
@@ -16,7 +16,7 @@
 
 #include <NewKit/Defines.hpp>
 
-using namespace HCore;
+using namespace NewOS;
 
 #define kUSBCommand (UInt16)0x0
 #define kUSBStatus (UInt16)0x2