Kernel: Many improvements done to the kernel and it's HAL and protocols.

Will implement BFileReader on next commit.

Signed-off-by: Amlal El Mahrouss <amlal.elmahrouss@icloud.com>

7 files changed, 231 insertions, 12 deletions

diff --git a/Private/HALKit/AMD64/CPUID.hxx b/Private/HALKit/AMD64/CPUID.hxx
new file mode 100644
index 00000000..16e73eb6
--- /dev/null
+++ b/Private/HALKit/AMD64/CPUID.hxx
@@ -0,0 +1,78 @@
+/* -------------------------------------------
+
+    Copyright Mahrouss Logic
+
+    File: CPUID.hpp
+    Purpose: CPUID flags.
+
+    Revision History:
+
+    30/01/24: Added file (amlel)
+
+------------------------------------------- */
+
+#pragma once
+
+typedef enum {
+  CPU_FEATURE_ECX_SSE3 = 1 << 0,
+  CPU_FEATURE_ECX_PCLMUL = 1 << 1,
+  CPU_FEATURE_ECX_DTES64 = 1 << 2,
+  CPU_FEATURE_ECX_MONITOR = 1 << 3,
+  CPU_FEATURE_ECX_DS_CPL = 1 << 4,
+  CPU_FEATURE_ECX_VMX = 1 << 5,
+  CPU_FEATURE_ECX_SMX = 1 << 6,
+  CPU_FEATURE_ECX_EST = 1 << 7,
+  CPU_FEATURE_ECX_TM2 = 1 << 8,
+  CPU_FEATURE_ECX_SSSE3 = 1 << 9,
+  CPU_FEATURE_ECX_CID = 1 << 10,
+  CPU_FEATURE_ECX_SDBG = 1 << 11,
+  CPU_FEATURE_ECX_FMA = 1 << 12,
+  CPU_FEATURE_ECX_CX16 = 1 << 13,
+  CPU_FEATURE_ECX_XTPR = 1 << 14,
+  CPU_FEATURE_ECX_PDCM = 1 << 15,
+  CPU_FEATURE_ECX_PCID = 1 << 17,
+  CPU_FEATURE_ECX_DCA = 1 << 18,
+  CPU_FEATURE_ECX_SSE4_1 = 1 << 19,
+  CPU_FEATURE_ECX_SSE4_2 = 1 << 20,
+  CPU_FEATURE_ECX_X2APIC = 1 << 21,
+  CPU_FEATURE_ECX_MOVBE = 1 << 22,
+  CPU_FEATURE_ECX_POP3C = 1 << 23,
+  CPU_FEATURE_ECX_TSC = 1 << 24,
+  CPU_FEATURE_ECX_AES = 1 << 25,
+  CPU_FEATURE_ECX_XSAVE = 1 << 26,
+  CPU_FEATURE_ECX_OSXSAVE = 1 << 27,
+  CPU_FEATURE_ECX_AVX = 1 << 28,
+  CPU_FEATURE_ECX_F16C = 1 << 29,
+  CPU_FEATURE_ECX_RDRAND = 1 << 30,
+  CPU_FEATURE_ECX_HYPERVISOR = 1 << 31,
+  CPU_FEATURE_EDX_FPU = 1 << 0,
+  CPU_FEATURE_EDX_VME = 1 << 1,
+  CPU_FEATURE_EDX_DE = 1 << 2,
+  CPU_FEATURE_EDX_PSE = 1 << 3,
+  CPU_FEATURE_EDX_TSC = 1 << 4,
+  CPU_FEATURE_EDX_MSR = 1 << 5,
+  CPU_FEATURE_EDX_PAE = 1 << 6,
+  CPU_FEATURE_EDX_MCE = 1 << 7,
+  CPU_FEATURE_EDX_CX8 = 1 << 8,
+  CPU_FEATURE_EDX_APIC = 1 << 9,
+  CPU_FEATURE_EDX_SEP = 1 << 11,
+  CPU_FEATURE_EDX_MTRR = 1 << 12,
+  CPU_FEATURE_EDX_PGE = 1 << 13,
+  CPU_FEATURE_EDX_MCA = 1 << 14,
+  CPU_FEATURE_EDX_CMOV = 1 << 15,
+  CPU_FEATURE_EDX_PAT = 1 << 16,
+  CPU_FEATURE_EDX_PSE36 = 1 << 17,
+  CPU_FEATURE_EDX_PSN = 1 << 18,
+  CPU_FEATURE_EDX_CLFLUSH = 1 << 19,
+  CPU_FEATURE_EDX_DS = 1 << 21,
+  CPU_FEATURE_EDX_ACPI = 1 << 22,
+  CPU_FEATURE_EDX_MMX = 1 << 23,
+  CPU_FEATURE_EDX_FXSR = 1 << 24,
+  CPU_FEATURE_EDX_SSE = 1 << 25,
+  CPU_FEATURE_EDX_SSE2 = 1 << 26,
+  CPU_FEATURE_EDX_SS = 1 << 27,
+  CPU_FEATURE_EDX_HTT = 1 << 28,
+  CPU_FEATURE_EDX_TM = 1 << 29,
+  CPU_FEATURE_EDX_IA64 = 1 << 30,
+  CPU_FEATURE_EDX_PBE = 1 << 31
+} CPU_FEATURE;
diff --git a/Private/HALKit/AMD64/CoreInterruptHandlerAMD64.cpp b/Private/HALKit/AMD64/CoreInterruptHandlerAMD64.cpp
index e49e9c1e..8399d9ce 100644
--- a/Private/HALKit/AMD64/CoreInterruptHandlerAMD64.cpp
+++ b/Private/HALKit/AMD64/CoreInterruptHandlerAMD64.cpp
@@ -16,7 +16,7 @@ extern "C" void idt_handle_system_call(HCore::UIntPtr rsp) {
   rt_syscall_handle(sf);
 
   HCore::kcout << "System Call with ID: "
-               << HCore::StringBuilder::FromInt("syscall{%}", sf->SID);
+               << HCore::StringBuilder::FromInt("syscall{%}", sf->R15);
 }
 
 extern "C" void idt_handle_gpf(HCore::UIntPtr rsp) {
@@ -79,3 +79,12 @@ extern "C" void idt_handle_generic(HCore::UIntPtr rsp) {
 
   HCore::ProcessManager::Shared().Leak().GetCurrent().Leak().Crash();
 }
+
+extern "C" HCore::UIntPtr rt_handle_interrupts(HCore::UIntPtr &rsp) {
+  HCore::HAL::rt_cli();
+
+  HCore::HAL::StackFramePtr sf = (HCore::HAL::StackFramePtr)rsp;
+
+  HCore::HAL::rt_sti();
+  return rsp;
+}
diff --git a/Private/HALKit/AMD64/CoreSyscallHandlerAMD64.cpp b/Private/HALKit/AMD64/CoreSyscallHandlerAMD64.cpp
index 119fe1b5..b41b8285 100644
--- a/Private/HALKit/AMD64/CoreSyscallHandlerAMD64.cpp
+++ b/Private/HALKit/AMD64/CoreSyscallHandlerAMD64.cpp
@@ -18,6 +18,6 @@ HCore::Array<void (*)(HCore::Int32 id, HCore::HAL::StackFrame *), kMaxSyscalls>
 // NOTE: don't trust the user.
 extern "C" void rt_syscall_handle(HCore::HAL::StackFrame *stack) {
   for (HCore::SizeT index = 0UL; index < kMaxSyscalls; ++index) {
-    (kSyscalls[index].Leak().Leak())(stack->SID, stack);
+    (kSyscalls[index].Leak().Leak())(stack->R15, stack);
   }
 }
diff --git a/Private/HALKit/AMD64/HalHardwareInit.cpp b/Private/HALKit/AMD64/HalHardwareInit.cpp
index b509b284..bc002e3d 100644
--- a/Private/HALKit/AMD64/HalHardwareInit.cpp
+++ b/Private/HALKit/AMD64/HalHardwareInit.cpp
@@ -11,9 +11,22 @@
 
 // bugs = 0
 
+extern "C" HCore::VoidPtr __EXEC_IVT;
+
+static HCore::HAL::Register64* kIdtRegister;
+static HCore::HAL::Register64* kGdtRegister;
+
 namespace HCore {
 bool ke_init_hal() {
-  // TODO: Hardware Specific stuff.
+  kIdtRegister = nullptr;
+  kGdtRegister = nullptr;
+
+  kIdtRegister = new HCore::HAL::Register64();
+  kIdtRegister->Base = (UIntPtr)__EXEC_IVT;
+  kIdtRegister->Limit = sizeof(HAL::Register64) * 256;
+
+  HAL::IDTLoader idt;
+  idt.Load(*kIdtRegister);
 
   return true;
 }
diff --git a/Private/HALKit/AMD64/HalInterruptRouting.asm b/Private/HALKit/AMD64/HalInterruptRouting.asm
index 417f9f59..36be9de4 100644
--- a/Private/HALKit/AMD64/HalInterruptRouting.asm
+++ b/Private/HALKit/AMD64/HalInterruptRouting.asm
@@ -10,3 +10,117 @@
 ;; */
 
 [bits 64]
+
+%macro IntDecl 1
+    dq HCoreInterrupt%1
+%endmacro
+
+%macro IntExp 1
+HCoreInterrupt%1:
+    push %1
+    jmp ke_handle_irq
+%endmacro
+
+%macro IntNormal 1
+HCoreInterrupt%1:
+    push  0
+    push  %1
+    jmp ke_handle_irq
+%endmacro
+
+; This file handles the core interrupt table
+; Last edited 31/01/24
+
+extern rt_handle_interrupts
+global rt_install_idt
+global __EXEC_IVT
+
+section .text
+
+ke_handle_irq:
+    cld
+
+    push rax
+    push rbx
+    push rcx
+    push rdx
+    push rsi
+    push rdi
+    push rbp
+    push r8
+    push r9
+    push r10
+    push r11
+    push r12
+    push r13
+    push r14
+    push r15
+
+    mov rdi, rsp
+    call rt_handle_interrupts
+
+    pop r15
+    pop r14
+    pop r13
+    pop r12
+    pop r11
+    pop r10
+    pop r9
+    pop r8
+    pop rbp
+    pop rdi
+    pop rsi
+    pop rdx
+    pop rcx
+    pop rbx
+    pop rax
+
+    ret
+
+section .data
+
+    IntNormal 0
+    IntNormal 1
+    IntNormal 2
+    IntNormal 3
+    IntNormal 4
+    IntNormal 5
+    IntNormal 6
+    IntNormal 7
+    IntExp   8
+    IntNormal 9
+    IntExp   10
+    IntExp   11
+    IntExp   12
+    IntExp   13
+    IntExp   14
+    IntNormal 15
+    IntNormal 16
+    IntExp 17
+    IntNormal 18
+    IntNormal 19
+    IntNormal 20
+    IntNormal 21
+    IntNormal 22
+    IntNormal 23
+    IntNormal 24
+    IntNormal 25
+    IntNormal 26
+    IntNormal 27
+    IntNormal 28
+    IntNormal 29
+    IntExp   30
+    IntNormal 31
+
+    %assign i 32
+    %rep 224
+        IntNormal i
+    %assign i i+1
+    %endrep
+
+__EXEC_IVT:
+    %assign i 0
+    %rep 256
+        IntDecl i
+    %assign i i+1
+    %endrep
diff --git a/Private/HALKit/AMD64/Processor.hpp b/Private/HALKit/AMD64/Processor.hpp
index 5d841e32..9b73216b 100644
--- a/Private/HALKit/AMD64/Processor.hpp
+++ b/Private/HALKit/AMD64/Processor.hpp
@@ -62,8 +62,7 @@ struct __attribute__((packed)) StackFrame {
   Reg R12;
   Reg R13;
   Reg R14;
-  Reg R15;  // Reserved: Multi Processor manager (Hal)
-  Reg SID;  // Reserved: system call id (Hal)
+  Reg R15;
 };
 
 typedef StackFrame *StackFramePtr;
diff --git a/Private/HALKit/AMD64/SMPCoreManager.asm b/Private/HALKit/AMD64/SMPCoreManager.asm
index 2560df98..de7d8356 100644
--- a/Private/HALKit/AMD64/SMPCoreManager.asm
+++ b/Private/HALKit/AMD64/SMPCoreManager.asm
@@ -10,16 +10,22 @@
 [bits 64]
 
 [global rt_do_context_switch]
-[extern rt_debug_fence]
 
 rt_do_context_switch:
-    mov rsi, [rt_do_context_switch_unprotected]
-    call rt_debug_fence
-
-    iret
-
-rt_do_context_switch_unprotected:
 	mov [rdi+0], rax
 	mov [rdi+8], rbx
 	mov [rdi+16], rcx
+	mov [rdi+24], rdx
+	mov [rdi+32], rsi
+	mov [rdi+40], rdi
+	mov [rdi+48], rbp
+	mov [rdi+56], rsp
+	mov [rdi+64], r8
+	mov [rdi+72], r9
+	mov [rdi+80], r10
+	mov [rdi+88], r11
+	mov [rdi+96], r12
+	mov [rdi+104], r13
+	mov [rdi+112], r14
+	mov [rdi+120], r15
 	ret