Merge pull request #13 from amlel-el-mahrouss/dev

dev: Last AHCI patches.

3 files changed, 94 insertions, 219 deletions

diff --git a/dev/kernel/HALKit/AMD64/HalPagingMgrAMD64.cc b/dev/kernel/HALKit/AMD64/HalPagingMgrAMD64.cc
index 6a9a89b7..040b6fd9 100644
--- a/dev/kernel/HALKit/AMD64/HalPagingMgrAMD64.cc
+++ b/dev/kernel/HALKit/AMD64/HalPagingMgrAMD64.cc
@@ -12,86 +12,54 @@
 
 namespace Kernel::HAL
 {
-	typedef UInt32 PageTableIndex;
-
 	/***********************************************************************************/
-	/// \brief Page store type.
+	/// @brief Gets a physical address from a virtual address.
+	/// @param virt a valid virtual address.
+	/// @return Physical address.
 	/***********************************************************************************/
-	struct PageStore final
-	{
-		struct
-		{
-			PDE*	fPde{nullptr};
-			PTE*	fPte{nullptr};
-			VoidPtr fPAddr{nullptr};
-		} fInternalStore;
-
-		Bool fStoreOp{No}; // Store operation is in progress.
-
-		bool IsValidPage(PTE* pte)
-		{
-			return pte && pte->Present;
-		}
-
-		bool IsWRPage(PTE* pte)
-		{
-			return pte && pte->Wr;
-		}
-
-		bool IsUserPage(PTE* pte)
-		{
-			return pte && pte->User;
-		}
-
-		static PageStore& The()
-		{
-			static PageStore the;
-			return the;
-		}
-	};
-
-	/// @brief Go over the Page structure and find the address of *virtual_address*
-
-	UIntPtr hal_get_phys_address(VoidPtr virtual_address)
+	UIntPtr hal_get_phys_address(VoidPtr virt)
 	{
-		// Constants for table index bits
-		const UInt64 kPmlIndexMask = 0x1FFULL; // Mask for PML4, PDPT, PD, PT index (9 bits)
-		const UInt64 kPtIndexMask  = 0xFFFULL; // Mask for page table index (12 bits)
+		const UInt64 vaddr			 = (UInt64)virt;
+		const UInt64 kMask9Bits		 = 0x1FFULL;
+		const UInt64 kPageOffsetMask = 0xFFFULL;
 
-		UInt64 cr3 = (UInt64)hal_read_cr3();
+		UInt64 cr3 = (UInt64)hal_read_cr3() & ~kPageOffsetMask;
 
-		PageStore& page_store = PageStore::The();
+		// Level 4
+		auto   pml4	 = reinterpret_cast<UInt64*>(cr3);
+		UInt64 pml4e = pml4[(vaddr >> 39) & kMask9Bits];
 
-		// Extract the indices from the virtual address
-		UInt64 pml4_index = ((UIntPtr)virtual_address >> 39) & kPmlIndexMask;
-		UInt64 pdpt_index = ((UIntPtr)virtual_address >> 30) & kPmlIndexMask;
-		UInt64 pd_index	  = ((UIntPtr)virtual_address >> 21) & kPmlIndexMask;
-		UInt64 pt_index	  = ((UIntPtr)virtual_address >> 12) & kPmlIndexMask;
+		if (!(pml4e & 1))
+			return 0;
 
-		page_store.fStoreOp = Yes;
+		// Level 3
+		auto   pdpt	 = reinterpret_cast<UInt64*>(pml4e & ~kPageOffsetMask);
+		UInt64 pdpte = pdpt[(vaddr >> 30) & kMask9Bits];
 
-		const auto kPmlEntrySize = 8;
+		if (!(pdpte & 1))
+			return 0;
 
-		// Read the PML4 entry from memory
-		UInt64 pml4_base  = cr3 & ~kPtIndexMask;					  // CR3 points to the PML4 table base, mask off lower bits
-		UInt64 pml4_entry = (pml4_base + pml4_index * kPmlEntrySize); // Each entry is 8 bytes
+		// Level 2
+		auto   pd  = reinterpret_cast<UInt64*>(pdpte & ~kPageOffsetMask);
+		UInt64 pde = pd[(vaddr >> 21) & kMask9Bits];
 
-		// Read the PDPT entry
-		UInt64 pdpt_base  = pml4_entry & ~kPtIndexMask; // Get the PDPT base physical address
-		UInt64 pdpt_entry = (pdpt_base + pdpt_index * kPmlEntrySize);
+		if (!(pde & 1))
+			return 0;
 
-		// Read the PD entry
-		UInt64 pd_base	= pdpt_entry & ~kPtIndexMask; // Get the Page Directory base physical address
-		UInt64 pd_entry = (pd_base + pd_index * kPmlEntrySize);
+		// 1 GiB page support
+		if (pde & (1 << 7))
+		{
+			return (pde & ~((1ULL << 30) - 1)) | (vaddr & ((1ULL << 30) - 1));
+		}
 
-		// Read the PT entry
-		UInt64 pt_base	= pd_entry & ~kPtIndexMask; // Get the Page Table base physical address
-		UInt64 pt_entry = (pt_base + pt_index * kPmlEntrySize);
+		// Level 1
+		auto   pt  = reinterpret_cast<UInt64*>(pde & ~kPageOffsetMask);
+		UInt64 pte = pt[(vaddr >> 12) & kMask9Bits];
 
-		// Lastly, grab the pte entry.
-		NE_PDE* pde_struct = reinterpret_cast<NE_PDE*>(pt_base);
+		if (!(pte & 1))
+			return 0;
 
-		return pde_struct->fEntries[pt_entry]->PhysicalAddress;
+		return (pte & ~kPageOffsetMask) | (vaddr & kPageOffsetMask);
 	}
 
 	/***********************************************************************************/
@@ -117,88 +85,49 @@ namespace Kernel::HAL
 	/***********************************************************************************/
 	EXTERN_C Int32 mm_map_page(VoidPtr virtual_address, VoidPtr physical_address, UInt32 flags)
 	{
-		// Constants for table index bits
-		const UInt64 kPmlIndexMask = 0x1FFULL; // Mask for PML4, PDPT, PD, PT index (9 bits)
-		const UInt64 kPtIndexMask  = 0xFFFULL; // Mask for page table index (12 bits)
+		const UInt64	 vaddr	   = (UInt64)virtual_address;
+		constexpr UInt64 kMask9	   = 0x1FF;
+		constexpr UInt64 kPageMask = 0xFFF;
 
-		UInt64 cr3 = (UInt64)hal_read_cr3();
+		UInt64 cr3 = (UIntPtr)hal_read_cr3() & ~kPageMask;
 
-		PageStore& page_store = PageStore::The();
+		auto   pml4	 = reinterpret_cast<UInt64*>(cr3);
+		UInt64 pml4e = pml4[(vaddr >> 39) & kMask9];
 
-		// Extract the indices from the virtual address
-		UInt64 pml4_index = ((UIntPtr)virtual_address >> 39) & kPmlIndexMask;
-		UInt64 pdpt_index = ((UIntPtr)virtual_address >> 30) & kPmlIndexMask;
-		UInt64 pd_index	  = ((UIntPtr)virtual_address >> 21) & kPmlIndexMask;
-		UInt64 pt_index	  = ((UIntPtr)virtual_address >> 12) & kPmlIndexMask;
-
-		page_store.fStoreOp = Yes;
-
-		const auto kPmlEntrySize = 8;
-
-		// Read the PML4 entry from memory
-		UInt64 pml4_base  = cr3 & ~kPtIndexMask;					  // CR3 points to the PML4 table base, mask off lower bits
-		UInt64 pml4_entry = (pml4_base + pml4_index * kPmlEntrySize); // Each entry is 8 bytes
+		if (!(pml4e & 1))
+			return 1;
 
-		// Read the PDPT entry
-		UInt64 pdpt_base  = pml4_entry & ~kPtIndexMask; // Get the PDPT base physical address
-		UInt64 pdpt_entry = (pdpt_base + pdpt_index * kPmlEntrySize);
+		auto   pdpt	 = reinterpret_cast<UInt64*>(pml4e & ~kPageMask);
+		UInt64 pdpte = pdpt[(vaddr >> 30) & kMask9];
 
-		// Read the PD entry
-		UInt64 pd_base	= pdpt_entry & ~kPtIndexMask; // Get the Page Directory base physical address
-		UInt64 pd_entry = (pd_base + pd_index * kPmlEntrySize);
+		if (!(pdpte & 1))
+			return 1;
 
-		// Read the PT entry
-		UInt64 pt_base	= pd_entry & ~kPtIndexMask; // Get the Page Table base physical address
-		UInt64 pt_entry = (pt_base + pt_index * kPmlEntrySize);
+		auto   pd  = reinterpret_cast<UInt64*>(pdpte & ~kPageMask);
+		UInt64 pde = pd[(vaddr >> 21) & kMask9];
 
-		// Lastly, grab the pte entry.
-		NE_PDE* pde_struct = reinterpret_cast<NE_PDE*>(pt_base);
+		if (!(pde & 1))
+			return 1;
 
-		return mmi_map_page_table_entry(reinterpret_cast<UIntPtr>(virtual_address), (UInt32)(UInt64)physical_address, flags, pde_struct->fEntries[pt_entry], pde_struct);
-	}
+		auto	pt	= reinterpret_cast<UInt64*>(pde & ~kPageMask);
+		UInt64& pte = pt[(vaddr >> 12) & kMask9];
 
-	/***********************************************************************************/
-	/// @brief Maps flags for a specific pte.
-	/// @internal Internal function.
-	/***********************************************************************************/
-	STATIC Int32 mmi_map_page_table_entry(UIntPtr virtual_address, UInt32 physical_address, UInt32 flags, NE_PTE* pt_entry, NE_PDE* pd_entry)
-	{
-		if (!pt_entry)
-			return 1;
+		// Set the new PTE
+		pte = (reinterpret_cast<UInt64>(physical_address) & ~0xFFFULL) | 0x01ULL; // Present
 
-		pt_entry->Present = true;
+		if (flags & ~kMMFlagsPresent)
+			pte &= ~(0x01ULL); // Not Present
 
 		if (flags & kMMFlagsWr)
-			pt_entry->Wr = true;
-		else if (flags & ~kMMFlagsWr)
-			pt_entry->Wr = false;
-
-		if (flags & kMMFlagsNX)
-			pt_entry->ExecDisable = true;
-		else if (flags & ~kMMFlagsNX)
-			pt_entry->ExecDisable = false;
+			pte |= 1 << 1; // Writable
 
 		if (flags & kMMFlagsUser)
-			pt_entry->User = true;
-		else if (flags & ~kMMFlagsUser)
-			pt_entry->User = false;
-
-		pt_entry->PhysicalAddress = physical_address;
-
-		hal_invl_tlb(reinterpret_cast<VoidPtr>(virtual_address));
+			pte |= 1 << 2; // User
 
-		mmi_page_status(pt_entry);
-
-		PageStore& page_store = PageStore::The();
-
-		// Update Internal store.
-
-		page_store.fInternalStore.fPde	 = pd_entry;
-		page_store.fInternalStore.fPte	 = pt_entry;
-		page_store.fInternalStore.fPAddr = (VoidPtr)(UIntPtr)physical_address;
-
-		page_store.fStoreOp = No;
+		if (flags & kMMFlagsNX)
+			pte |= 1ULL << 63; // NX
 
+		hal_invl_tlb(virtual_address);
 		return 0;
 	}
 } // namespace Kernel::HAL
diff --git a/dev/kernel/HALKit/AMD64/PCI/Device.cc b/dev/kernel/HALKit/AMD64/PCI/Device.cc
index 9c27cb10..ced473ed 100644
--- a/dev/kernel/HALKit/AMD64/PCI/Device.cc
+++ b/dev/kernel/HALKit/AMD64/PCI/Device.cc
@@ -7,14 +7,15 @@
 #include <ArchKit/ArchKit.h>
 #include <KernelKit/PCI/Device.h>
 
-#define PCI_BAR_IO		 0x01
-#define PCI_BAR_LOWMEM	 0x02
-#define PCI_BAR_64		 0x04
-#define PCI_BAR_PREFETCH 0x08
+#define PCI_BAR_IO		 (0x01)
+#define PCI_BAR_LOWMEM	 (0x02)
+#define PCI_BAR_64		 (0x04)
+#define PCI_BAR_PREFETCH (0x08)
+#define PCI_ENABLE_BIT	 (0x80000000)
 
-Kernel::UInt NE_PCIReadRaw(Kernel::UInt bar, Kernel::UShort bus, Kernel::UShort dev, Kernel::UShort fun)
+static Kernel::UInt NE_PCIReadRaw(Kernel::UInt bar, Kernel::UShort bus, Kernel::UShort dev, Kernel::UShort fun)
 {
-	Kernel::UInt target = 0x80000000 | ((Kernel::UInt)bus << 16) |
+	Kernel::UInt target = PCI_ENABLE_BIT | ((Kernel::UInt)bus << 16) |
 						  ((Kernel::UInt)dev << 11) | ((Kernel::UInt)fun << 8) |
 						  (bar & 0xFC);
 
@@ -26,7 +27,7 @@ Kernel::UInt NE_PCIReadRaw(Kernel::UInt bar, Kernel::UShort bus, Kernel::UShort
 	return Kernel::HAL::rt_in32((Kernel::UShort)Kernel::PCI::PciConfigKind::ConfigData);
 }
 
-void NE_PCISetCfgTarget(Kernel::UInt bar, Kernel::UShort bus, Kernel::UShort dev, Kernel::UShort fun)
+static Kernel::Void NE_PCISetCfgTarget(Kernel::UInt bar, Kernel::UShort bus, Kernel::UShort dev, Kernel::UShort fun)
 {
 	Kernel::UInt target = 0x80000000 | ((Kernel::UInt)bus << 16) |
 						  ((Kernel::UInt)dev << 11) | ((Kernel::UInt)fun << 8) |
@@ -70,20 +71,26 @@ namespace Kernel::PCI
 		NE_PCISetCfgTarget(bar & 0xFC, fBus, fDevice, fFunction);
 
 		if (sz == 4)
-			HAL::rt_out32((UShort)PciConfigKind::ConfigData, (UInt)data);
+		{
+			HAL::rt_out32((UShort)PciConfigKind::ConfigAddress, (UInt)data);
+		}
 		else if (sz == 2)
 		{
 			UInt temp = HAL::rt_in32((UShort)PciConfigKind::ConfigData);
+
 			temp &= ~(0xFFFF << ((bar & 2) * 8));
 			temp |= (data & 0xFFFF) << ((bar & 2) * 8);
-			HAL::rt_out32((UShort)PciConfigKind::ConfigData, temp);
+
+			HAL::rt_out32((UShort)PciConfigKind::ConfigAddress, temp);
 		}
 		else if (sz == 1)
 		{
 			UInt temp = HAL::rt_in32((UShort)PciConfigKind::ConfigData);
+
 			temp &= ~(0xFF << ((bar & 3) * 8));
 			temp |= (data & 0xFF) << ((bar & 3) * 8);
-			HAL::rt_out32((UShort)PciConfigKind::ConfigData, temp);
+
+			HAL::rt_out32((UShort)PciConfigKind::ConfigAddress, temp);
 		}
 	}
 
diff --git a/dev/kernel/HALKit/AMD64/Storage/AHCI+Generic.cc b/dev/kernel/HALKit/AMD64/Storage/AHCI+Generic.cc
index 3336e20e..41aabca2 100644
--- a/dev/kernel/HALKit/AMD64/Storage/AHCI+Generic.cc
+++ b/dev/kernel/HALKit/AMD64/Storage/AHCI+Generic.cc
@@ -15,7 +15,6 @@
  *
  */
 
-#include "NewKit/Defines.h"
 #include <KernelKit/DeviceMgr.h>
 #include <KernelKit/DriveMgr.h>
 #include <KernelKit/ProcessScheduler.h>
@@ -70,7 +69,7 @@ STATIC Void drv_compute_disk_ahci() noexcept;
 namespace AHCI::Detail
 {
 	template <typename RetType>
-	RetType* ahci_align_address(RetType* address, Int32 alignement)
+	STATIC RetType* ahci_align_address(RetType* address, Int32 alignement)
 	{
 		if (!address)
 			return nullptr;
@@ -91,7 +90,7 @@ STATIC Void drv_compute_disk_ahci() noexcept
 	const UInt16 kSzIdent = 256;
 
 	/// Push it to the stack
-	UInt16* identify_data ATTRIBUTE(aligned(kib_cast(1))) = AHCI::Detail::ahci_align_address<UInt16>(new UInt16[kSzIdent], kib_cast(1));
+	UInt16* identify_data = AHCI::Detail::ahci_align_address<UInt16>(new UInt16[kSzIdent], kib_cast(1));
 
 	/// Send AHCI command for identification.
 	drv_std_input_output_ahci<NO, YES, YES>(0, (UInt8*)identify_data, kAHCISectorSize, kSzIdent);
@@ -148,6 +147,10 @@ STATIC Void drv_std_input_output_ahci(UInt64 lba, UInt8* buffer, SizeT sector_sz
 		return;
 	}
 
+	if (size_buffer > mib_cast(4) ||
+		sector_sz > kAHCISectorSize)
+		return;
+
 	if (!Write)
 	{
 		// Zero-memory the buffer field.
@@ -168,9 +171,10 @@ STATIC Void drv_std_input_output_ahci(UInt64 lba, UInt8* buffer, SizeT sector_sz
 
 	command_header->Cfl	  = sizeof(FisRegH2D) / sizeof(UInt32);
 	command_header->Write = Write;
-	command_header->Prdtl = (UInt16)((size_buffer + kMaxPRDSize - 1) / kMaxPRDSize);
+	command_header->Prdtl = 1;
 
-	volatile HbaCmdTbl* command_table = (volatile HbaCmdTbl*)((VoidPtr)((UInt64)command_header->Ctba));
+	auto ctba_phys	   = ((UInt64)command_header->Ctbau << 32) | command_header->Ctba;
+	auto command_table = reinterpret_cast<volatile HbaCmdTbl*>(ctba_phys);
 
 	rt_set_memory((HbaCmdTbl*)command_table, 0, sizeof(HbaCmdTbl) + (command_header->Prdtl - 1) * sizeof(HbaPrdtEntry));
 
@@ -178,28 +182,14 @@ STATIC Void drv_std_input_output_ahci(UInt64 lba, UInt8* buffer, SizeT sector_sz
 
 	UIntPtr buffer_phys		= HAL::hal_get_phys_address(buffer);
 	SizeT	bytes_remaining = size_buffer;
-	SizeT	prdt_count		= command_header->Prdtl;
 
-	for (UInt16 i = 0; i < prdt_count; ++i)
-	{
-		UInt32 chunk = bytes_remaining / prdt_count;
-
-		if (chunk == 0)
-			break;
-
-		command_table->Prdt[i].Dba	= (UInt32)(buffer_phys & 0xFFFFFFFF);
-		command_table->Prdt[i].Dbau = (UInt32)(buffer_phys >> 32);
-		command_table->Prdt[i].Dbc	= chunk - 1;
-		command_table->Prdt[i].Ie	= 1;
-
-		buffer_phys += chunk;
-		bytes_remaining -= chunk;
-	}
+	command_table->Prdt[0].Dba	= (UInt32)(buffer_phys & 0xFFFFFFFF);
+	command_table->Prdt[0].Dbau = (UInt32)(buffer_phys >> 32);
+	command_table->Prdt[0].Dbc	= bytes_remaining - 1;
+	command_table->Prdt[0].Ie	= 1;
 
 	volatile FisRegH2D* h2d_fis = (volatile FisRegH2D*)(&command_table->Cfis[0]);
 
-	rt_set_memory((FisRegH2D*)h2d_fis, 0, sizeof(FisRegH2D));
-
 	h2d_fis->FisType   = kFISTypeRegH2D;
 	h2d_fis->CmdOrCtrl = CommandOrCTRL;
 	h2d_fis->Command   = (Identify ? (kAHCICmdIdentify) : (Write ? kAHCICmdWriteDmaEx : kAHCICmdReadDmaEx));
@@ -217,29 +207,12 @@ STATIC Void drv_std_input_output_ahci(UInt64 lba, UInt8* buffer, SizeT sector_sz
 	h2d_fis->CountLow  = (size_buffer)&0xFF;
 	h2d_fis->CountHigh = (size_buffer >> 8) & 0xFF;
 
-	while (kSATAHba->Ports[kSATAIndex].Tfd & (kSATASRBsy | kSATASRDrq))
-	{
-		;
-	}
-
 	kSATAHba->Ports[kSATAIndex].Ci = (1 << slot);
 
-	while (YES)
+	for (Int32 i = 0; i < 1000000; ++i)
 	{
 		if (!(kSATAHba->Ports[kSATAIndex].Ci & (1 << slot)))
 			break;
-
-		if (kSATAHba->Is & kHBAErrTaskFile)
-		{
-			err_global_get() = kErrorDiskIsCorrupted;
-			return;
-		}
-	}
-
-	/// we should wait again, just in case.
-	while (kSATAHba->Ports[kSATAIndex].Tfd & (kSATASRBsy | kSATASRDrq))
-	{
-		;
 	}
 
 	if (kSATAHba->Is & kHBAErrTaskFile)
@@ -287,40 +260,6 @@ STATIC BOOL ahci_enable_and_probe()
 		break;
 	}
 
-	// Command engine stopped, remap the AHCI port.
-
-	auto port = &kSATAHba->Ports[kSATAIndex];
-
-	// Relocate Command List Base.
-
-	VoidPtr const kAHCIBasePtr	   = AHCI::Detail::ahci_align_address<Void>(mm_new_heap(kib_cast(64), YES, NO, 0), kib_cast(1));
-	UIntPtr const kAHCIBaseAddress = reinterpret_cast<UIntPtr>(kAHCIBasePtr);
-
-	port->Clb  = kAHCIBaseAddress + (kSATAIndex << 10);
-	port->Clbu = 0;
-
-	// clean it.
-	rt_set_memory(reinterpret_cast<VoidPtr>(port->Clb), 0, 1024);
-
-	// Relocate Frame Info Structure now.
-
-	port->Fb  = (UInt32)(UIntPtr)(UIntPtr*)AHCI::Detail::ahci_align_address<UInt32>((UInt32*)(kAHCIBaseAddress + (kSATAPortCnt << 10) + (kSATAIndex << 10)), kib_cast(1));
-	port->Fbu = 0;
-
-	// clean it.
-	rt_set_memory(reinterpret_cast<VoidPtr>(port->Fb), 0, 256);
-
-	volatile HbaCmdHeader* cmd_hdr = reinterpret_cast<volatile HbaCmdHeader*>(port->Clb);
-
-	for (Int32 i = 0; i < kSATAPortCnt; i++)
-	{
-		cmd_hdr[i].Prdtl = 8;
-		cmd_hdr[i].Ctba	 = (UInt32)(UIntPtr)(UIntPtr*)AHCI::Detail::ahci_align_address<UInt32>((UInt32*)(kAHCIBaseAddress + (40 << 10) + (kSATAPortCnt << 10) + (kSATAIndex << 10)), kib_cast(1));
-		cmd_hdr[i].Ctbau = 0;
-
-		rt_set_memory(reinterpret_cast<VoidPtr>(cmd_hdr[i].Ctba), 0, 256);
-	}
-
 	// Now we are ready.
 
 	kSATAHba->Ports[kSATAIndex].Cmd |= kHBAPxCmdFre;
@@ -491,9 +430,9 @@ namespace Kernel
 	UInt16 sk_init_ahci_device(BOOL atapi)
 	{
 		UInt16 pi = 0;
-		drv_std_init_ahci(pi, atapi);
 
-		kSATAPortsImplemented = pi;
+		if (drv_std_init_ahci(pi, atapi))
+			kSATAPortsImplemented = pi;
 
 		return pi;
 	}