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-rw-r--r--Kernel/HALKit/POWER/HalContextSwitchPowerPC.s2
-rw-r--r--Kernel/HALKit/POWER/HalHardware.cxx4
-rw-r--r--Kernel/HALKit/POWER/HalHart.cxx4
-rw-r--r--Kernel/HALKit/POWER/HalSerialPort.cxx6
-rw-r--r--Kernel/HALKit/POWER/HalStartSequence.s2
-rw-r--r--Kernel/HALKit/POWER/HalThread.cxx4
-rw-r--r--Kernel/HALKit/POWER/HalVirtualMemory.cxx33
-rw-r--r--Kernel/HALKit/POWER/Hart.hxx8
-rw-r--r--Kernel/HALKit/POWER/MBCI/HalMBCIHost.cxx4
-rw-r--r--Kernel/HALKit/POWER/Processor.hpp55
-rw-r--r--Kernel/HALKit/POWER/Processor.hxx56
-rw-r--r--Kernel/HALKit/POWER/ppc-cpu.h130
-rw-r--r--Kernel/HALKit/POWER/ppc-mmu.h12
13 files changed, 159 insertions, 161 deletions
diff --git a/Kernel/HALKit/POWER/HalContextSwitchPowerPC.s b/Kernel/HALKit/POWER/HalContextSwitchPowerPC.s
index 14d805db..e14efb6b 100644
--- a/Kernel/HALKit/POWER/HalContextSwitchPowerPC.s
+++ b/Kernel/HALKit/POWER/HalContextSwitchPowerPC.s
@@ -1,6 +1,6 @@
/* -------------------------------------------
- Copyright Zeta Electronics Corporation
+ Copyright ZKA Technologies
------------------------------------------- */
diff --git a/Kernel/HALKit/POWER/HalHardware.cxx b/Kernel/HALKit/POWER/HalHardware.cxx
index 15407eb3..a057355e 100644
--- a/Kernel/HALKit/POWER/HalHardware.cxx
+++ b/Kernel/HALKit/POWER/HalHardware.cxx
@@ -1,10 +1,10 @@
/* -------------------------------------------
- Copyright Zeta Electronics Corporation
+ Copyright ZKA Technologies
------------------------------------------- */
-#include <HALKit/POWER/Processor.hpp>
+#include <HALKit/POWER/Processor.hxx>
#include <KernelKit/DebugOutput.hpp>
namespace Kernel
diff --git a/Kernel/HALKit/POWER/HalHart.cxx b/Kernel/HALKit/POWER/HalHart.cxx
index 614828cb..5ff12218 100644
--- a/Kernel/HALKit/POWER/HalHart.cxx
+++ b/Kernel/HALKit/POWER/HalHart.cxx
@@ -1,10 +1,10 @@
/* -------------------------------------------
- Copyright Zeta Electronics Corporation
+ Copyright ZKA Technologies
------------------------------------------- */
-#include <HALKit/POWER/Processor.hpp>
+#include <HALKit/POWER/Processor.hxx>
#include <KernelKit/DebugOutput.hpp>
#include <HALKit/POWER/Hart.hxx>
diff --git a/Kernel/HALKit/POWER/HalSerialPort.cxx b/Kernel/HALKit/POWER/HalSerialPort.cxx
index abddd291..86b43bb7 100644
--- a/Kernel/HALKit/POWER/HalSerialPort.cxx
+++ b/Kernel/HALKit/POWER/HalSerialPort.cxx
@@ -1,10 +1,10 @@
/* -------------------------------------------
- Copyright Zeta Electronics Corporation
+ Copyright ZKA Technologies
------------------------------------------- */
-#include <HALKit/POWER/Processor.hpp>
+#include <HALKit/POWER/Processor.hxx>
#include <KernelKit/DebugOutput.hpp>
using namespace Kernel;
@@ -17,7 +17,7 @@ void ke_io_write(const Char* bytes)
return;
SizeT index = 0;
- SizeT len = rt_string_len(bytes, 256);
+ SizeT len = rt_string_len(bytes, 255);
while (index < len)
{
diff --git a/Kernel/HALKit/POWER/HalStartSequence.s b/Kernel/HALKit/POWER/HalStartSequence.s
index 07cec350..a2741103 100644
--- a/Kernel/HALKit/POWER/HalStartSequence.s
+++ b/Kernel/HALKit/POWER/HalStartSequence.s
@@ -1,6 +1,6 @@
/* -------------------------------------------
- Copyright Zeta Electronics Corporation
+ Copyright ZKA Technologies
------------------------------------------- */
diff --git a/Kernel/HALKit/POWER/HalThread.cxx b/Kernel/HALKit/POWER/HalThread.cxx
index 18d84d4f..b3be23c4 100644
--- a/Kernel/HALKit/POWER/HalThread.cxx
+++ b/Kernel/HALKit/POWER/HalThread.cxx
@@ -1,10 +1,10 @@
/* -------------------------------------------
- Copyright Zeta Electronics Corporation
+ Copyright ZKA Technologies
------------------------------------------- */
-#include <HALKit/POWER/Processor.hpp>
+#include <HALKit/POWER/Processor.hxx>
#include <KernelKit/DebugOutput.hpp>
EXTERN_C Kernel::HAL::StackFramePtr rt_get_current_context()
diff --git a/Kernel/HALKit/POWER/HalVirtualMemory.cxx b/Kernel/HALKit/POWER/HalVirtualMemory.cxx
index eb04a43d..039bf509 100644
--- a/Kernel/HALKit/POWER/HalVirtualMemory.cxx
+++ b/Kernel/HALKit/POWER/HalVirtualMemory.cxx
@@ -1,26 +1,20 @@
/* -------------------------------------------
- Copyright Zeta Electronics Corporation
+ Copyright ZKA Technologies
------------------------------------------- */
#include <HALKit/POWER/ppc-cpu.h>
#include <HALKit/POWER/ppc-mmu.h>
-#include <HALKit/POWER/Processor.hpp>
+#include <HALKit/POWER/Processor.hxx>
#include <KernelKit/DebugOutput.hpp>
-/// @note refer to our SoC documentation.
+/// @note refer to the SoC documentation.
using namespace Kernel;
-/// @brief Write directly to the specific TLB.
-/// @param mas0
-/// @param mas1
-/// @param mas2
-/// @param mas3
-/// @param mas7
-static void hal_write_tlb(uint32_t mas0, uint32_t mas1, uint32_t mas2, uint32_t mas3, uint32_t mas7)
+Void hal_write_tlb(UInt32 mas0, UInt32 mas1, UInt32 mas2, UInt32 mas3, UInt32 mas7)
{
mtspr(MAS0, mas0);
mtspr(MAS1, mas1);
@@ -31,23 +25,26 @@ static void hal_write_tlb(uint32_t mas0, uint32_t mas1, uint32_t mas2, uint32_t
hal_flush_tlb();
}
-void hal_set_tlb(uint8_t tlb, uint32_t epn, uint64_t rpn, uint8_t perms, uint8_t wimge, uint8_t ts, uint8_t esel, uint8_t tsize, uint8_t iprot)
+Bool hal_set_tlb(UInt8 tlb, UInt32 epn, UInt64 rpn, UInt8 perms, UInt8 wimge, UInt8 ts, UInt8 esel, UInt8 tsize, UInt8 iprot)
{
if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1 && (tsize & 1))
{
// this mmu-version does not allow odd tsize values
- return;
+ return false;
}
- uint32_t mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
- uint32_t mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
- uint32_t mas2 = FSL_BOOKE_MAS2(epn, wimge);
- uint32_t mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
- uint32_t mas7 = FSL_BOOKE_MAS7(rpn);
+
+ UInt32 mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
+ UInt32 mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
+ UInt32 mas2 = FSL_BOOKE_MAS2(epn, wimge);
+ UInt32 mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
+ UInt32 mas7 = FSL_BOOKE_MAS7(rpn);
hal_write_tlb(mas0, mas1, mas2, mas3, mas7);
+
+ return true;
}
-/// @brief Flush system TLB.
+/// @brief Flush TLB
EXTERN_C void hal_flush_tlb()
{
asm volatile("isync;tlbwe;msync;isync");
diff --git a/Kernel/HALKit/POWER/Hart.hxx b/Kernel/HALKit/POWER/Hart.hxx
index 8f466098..e887ce4a 100644
--- a/Kernel/HALKit/POWER/Hart.hxx
+++ b/Kernel/HALKit/POWER/Hart.hxx
@@ -1,6 +1,6 @@
/* -------------------------------------------
- Copyright Zeta Electronics Corporation
+ Copyright ZKA Technologies
File: Hart.hxx
Purpose: POWER hardware threads.
@@ -22,9 +22,9 @@ typedef Kernel::Int32 PPCHartType;
typedef struct HalHardwareThread
{
Kernel::UIntPtr fStartAddress;
- Kernel::UInt8 fPrivleged : 1;
- Kernel::UInt32 fPageFlags;
- PPCHartType fIdentNumber;
+ Kernel::UInt8 fPrivleged : 1;
+ Kernel::UInt32 fPageFlags;
+ PPCHartType fIdentNumber;
} HalHardwareThread;
/// @brief Set PC to specific hart.
diff --git a/Kernel/HALKit/POWER/MBCI/HalMBCIHost.cxx b/Kernel/HALKit/POWER/MBCI/HalMBCIHost.cxx
index 8a24506a..93cf86ae 100644
--- a/Kernel/HALKit/POWER/MBCI/HalMBCIHost.cxx
+++ b/Kernel/HALKit/POWER/MBCI/HalMBCIHost.cxx
@@ -1,8 +1,8 @@
/* -------------------------------------------
- Copyright Zeta Electronics Corporation
+ Copyright ZKA Technologies
------------------------------------------- */
-#include <HALKit/POWER/Processor.hpp>
+#include <HALKit/POWER/Processor.hxx>
#include <KernelKit/DebugOutput.hpp>
diff --git a/Kernel/HALKit/POWER/Processor.hpp b/Kernel/HALKit/POWER/Processor.hpp
deleted file mode 100644
index 5ff7eef3..00000000
--- a/Kernel/HALKit/POWER/Processor.hpp
+++ /dev/null
@@ -1,55 +0,0 @@
-/* -------------------------------------------
-
- Copyright Zeta Electronics Corporation
-
- Purpose: POWER processor header.
-
-------------------------------------------- */
-
-#pragma once
-
-#include <NewKit/Defines.hpp>
-#include <NewKit/Utils.hpp>
-
-#define kHalPPCAlignment __attribute__((aligned(4)))
-
-namespace Kernel::HAL
-{
- typedef UIntPtr Reg;
-
- struct kHalPPCAlignment StackFrame
- {
- Reg R0;
- Reg R1;
- Reg R2;
- Reg R3;
- Reg R4;
- Reg R5;
- Reg R6;
- Reg R7;
- Reg R8;
- Reg PC;
- Reg SP;
- };
-
- typedef StackFrame* StackFramePtr;
-
- inline void rt_halt()
- {
- while (1)
- {
- asm volatile("mr 0, 0"); // no oop.
- }
- }
-
- inline void rt_cli()
- {
- asm volatile("mr 0, 0"); // no oop
- }
-} // namespace Kernel::HAL
-
-EXTERN_C void int_handle_math(Kernel::UIntPtr sp);
-EXTERN_C void int_handle_pf(Kernel::UIntPtr sp);
-
-/// @brief Flush system TLB.
-EXTERN_C void hal_flush_tlb();
diff --git a/Kernel/HALKit/POWER/Processor.hxx b/Kernel/HALKit/POWER/Processor.hxx
new file mode 100644
index 00000000..b2186aa7
--- /dev/null
+++ b/Kernel/HALKit/POWER/Processor.hxx
@@ -0,0 +1,56 @@
+/* -------------------------------------------
+
+ Copyright ZKA Technologies
+
+ Purpose: POWER processor header.
+
+------------------------------------------- */
+
+#pragma once
+
+#include <NewKit/Defines.hpp>
+#include <NewKit/Utils.hpp>
+
+#define NoOp() asm volatile("mr 0, 0")
+#define kHalPPCAlignment __attribute__((aligned(4)))
+
+namespace Kernel::HAL
+{
+ typedef UIntPtr Reg;
+
+ /// @brief Stack frame (as retrieved from assembly.)
+ struct PACKED StackFrame final
+ {
+ Reg IntNum, Exception;
+ Reg A0, A2, BP, SP, A3, A4, A5, A6;
+ Reg R8, R9, R10, R11, R12, R13, R14, R15;
+ Reg Gs, Fs;
+ };
+
+ typedef StackFrame* StackFramePtr;
+
+ inline void rt_halt()
+ {
+ while (true)
+ {
+ NoOp(); // no oop.
+ }
+ }
+
+ inline void rt_cli()
+ {
+ NoOp(); // no oop
+ }
+} // namespace Kernel::HAL
+
+EXTERN_C Kernel::Void int_handle_math(Kernel::UIntPtr sp);
+EXTERN_C Kernel::Void int_handle_pf(Kernel::UIntPtr sp);
+
+/// @brief Set TLB.
+Kernel::Bool hal_set_tlb(Kernel::UInt8 tlb, Kernel::UInt32 epn, Kernel::UInt64 rpn, Kernel::UInt8 perms, Kernel::UInt8 wimge, Kernel::UInt8 ts, Kernel::UInt8 esel, Kernel::UInt8 tsize, Kernel::UInt8 iprot);
+
+/// @brief Write TLB.
+Kernel::Void hal_write_tlb(Kernel::UInt32 mas0, Kernel::UInt32 mas1, Kernel::UInt32 mas2, Kernel::UInt32 mas3, Kernel::UInt32 mas7);
+
+/// @brief Flush TLB.
+EXTERN_C Kernel::Void hal_flush_tlb();
diff --git a/Kernel/HALKit/POWER/ppc-cpu.h b/Kernel/HALKit/POWER/ppc-cpu.h
index 3855b85c..46979e5f 100644
--- a/Kernel/HALKit/POWER/ppc-cpu.h
+++ b/Kernel/HALKit/POWER/ppc-cpu.h
@@ -141,36 +141,36 @@ struct pt_regs
#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
#define DBCR_EDM 0x80000000
#define DBCR_IDM 0x40000000
-#define DBCR_RST(x) (((x)&0x3) << 28)
+#define DBCR_RST(x) (((x) & 0x3) << 28)
#define DBCR_RST_NONE 0
#define DBCR_RST_CORE 1
#define DBCR_RST_CHIP 2
#define DBCR_RST_SYSTEM 3
-#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
-#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
-#define DBCR_EDE 0x02000000 /* Exception Debug Event */
-#define DBCR_TDE 0x01000000 /* TRAP Debug Event */
-#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
-#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
-#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
-#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
-#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
-#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
-#define DBCR_D1S(x) (((x)&0x3) << 12) /* Data Adrr. Compare 1 Size */
+#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
+#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
+#define DBCR_EDE 0x02000000 /* Exception Debug Event */
+#define DBCR_TDE 0x01000000 /* TRAP Debug Event */
+#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
+#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
+#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
+#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
+#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
+#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
+#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
#define DAC_BYTE 0
#define DAC_HALF 1
#define DAC_WORD 2
#define DAC_QUAD 3
-#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
-#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
-#define DBCR_D2S(x) (((x)&0x3) << 8) /* Data Addr. Compare 2 Size */
-#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
-#define DBCR_SED 0x00000020 /* Second Exception Debug Event */
-#define DBCR_STD 0x00000010 /* Second Trap Debug Event */
-#define DBCR_SIA 0x00000008 /* Second IAC Enable */
-#define DBCR_SDA 0x00000004 /* Second DAC Enable */
-#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
-#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
+#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
+#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
+#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
+#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
+#define DBCR_SED 0x00000020 /* Second Exception Debug Event */
+#define DBCR_STD 0x00000010 /* Second Trap Debug Event */
+#define DBCR_SIA 0x00000008 /* Second IAC Enable */
+#define DBCR_SDA 0x00000004 /* Second DAC Enable */
+#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
+#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
#ifndef CONFIG_BOOKE
#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
#else
@@ -395,27 +395,27 @@ struct pt_regs
#define TCR_WP(x) (((64 - x) & 0x3) << 30) | \
(((64 - x) & 0x3c) << 15) /* WDT Period 2^x clocks*/
#else
-#define TCR_WP(x) (((x)&0x3) << 30) /* WDT Period */
-#define WP_2_17 0 /* 2^17 clocks */
-#define WP_2_21 1 /* 2^21 clocks */
-#define WP_2_25 2 /* 2^25 clocks */
-#define WP_2_29 3 /* 2^29 clocks */
-#endif /* CONFIG_E500 */
-#define TCR_WRC(x) (((x)&0x3) << 28) /* WDT Reset Control */
-#define WRC_NONE 0 /* No reset will occur */
-#define WRC_CORE 1 /* Core reset will occur */
-#define WRC_CHIP 2 /* Chip reset will occur */
-#define WRC_SYSTEM 3 /* System reset will occur */
-#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
-#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
-#define TCR_FP(x) (((x)&0x3) << 24) /* FIT Period */
-#define FP_2_9 0 /* 2^9 clocks */
-#define FP_2_13 1 /* 2^13 clocks */
-#define FP_2_17 2 /* 2^17 clocks */
-#define FP_2_21 3 /* 2^21 clocks */
-#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
-#define TCR_ARE 0x00400000 /* Auto Reload Enable */
-#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
+#define TCR_WP(x) (((x) & 0x3) << 30) /* WDT Period */
+#define WP_2_17 0 /* 2^17 clocks */
+#define WP_2_21 1 /* 2^21 clocks */
+#define WP_2_25 2 /* 2^25 clocks */
+#define WP_2_29 3 /* 2^29 clocks */
+#endif /* CONFIG_E500 */
+#define TCR_WRC(x) (((x) & 0x3) << 28) /* WDT Reset Control */
+#define WRC_NONE 0 /* No reset will occur */
+#define WRC_CORE 1 /* Core reset will occur */
+#define WRC_CHIP 2 /* Chip reset will occur */
+#define WRC_SYSTEM 3 /* System reset will occur */
+#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
+#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
+#define TCR_FP(x) (((x) & 0x3) << 24) /* FIT Period */
+#define FP_2_9 0 /* 2^9 clocks */
+#define FP_2_13 1 /* 2^13 clocks */
+#define FP_2_17 2 /* 2^17 clocks */
+#define FP_2_21 3 /* 2^21 clocks */
+#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
+#define TCR_ARE 0x00400000 /* Auto Reload Enable */
+#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
#define THRM1_TIN (1 << 0)
#define THRM1_TIV (1 << 1)
#define THRM1_THRES (0x7f << 2)
@@ -429,26 +429,26 @@ struct pt_regs
#ifndef CONFIG_BOOKE
#define SPRN_TSR 0x3D8 /* Timer Status Register */
#else
-#define SPRN_TSR 0x150 /* Book E Timer Status Register */
-#endif /* CONFIG_BOOKE */
-#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
-#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
-#define TSR_WRS(x) (((x)&0x3) << 28) /* WDT Reset Status */
-#define WRS_NONE 0 /* No WDT reset occurred */
-#define WRS_CORE 1 /* WDT forced core reset */
-#define WRS_CHIP 2 /* WDT forced chip reset */
-#define WRS_SYSTEM 3 /* WDT forced system reset */
-#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
-#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
-#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
-#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
-#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
-#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
-#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
-#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
-#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
-#define SPRN_XER 0x001 /* Fixed Point Exception Register */
-#define SPRN_ZPR 0x3B0 /* Zone Protection Register */
+#define SPRN_TSR 0x150 /* Book E Timer Status Register */
+#endif /* CONFIG_BOOKE */
+#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
+#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
+#define TSR_WRS(x) (((x) & 0x3) << 28) /* WDT Reset Status */
+#define WRS_NONE 0 /* No WDT reset occurred */
+#define WRS_CORE 1 /* WDT forced core reset */
+#define WRS_CHIP 2 /* WDT forced chip reset */
+#define WRS_SYSTEM 3 /* WDT forced system reset */
+#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
+#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
+#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
+#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
+#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
+#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
+#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
+#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
+#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
+#define SPRN_XER 0x001 /* Fixed Point Exception Register */
+#define SPRN_ZPR 0x3B0 /* Zone Protection Register */
/* Book E definitions */
#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
@@ -853,7 +853,7 @@ struct pt_regs
#define IOCR_PTD 0x00000400
#define IOCR_ARE 0x00000080
#define IOCR_DRC 0x00000020
-#define IOCR_RDM(x) (((x)&0x3) << 3)
+#define IOCR_RDM(x) (((x) & 0x3) << 3)
#define IOCR_TCS 0x00000004
#define IOCR_SCS 0x00000002
#define IOCR_SPC 0x00000001
@@ -1252,7 +1252,7 @@ int fsl_qoriq_dsp_core_to_cluster(unsigned int core);
#if defined(CONFIG_MPC83xx)
#define CPU_TYPE_ENTRY(x) \
{ \
-#x, SPR_##x \
+ #x, SPR_##x \
}
#endif
#endif
diff --git a/Kernel/HALKit/POWER/ppc-mmu.h b/Kernel/HALKit/POWER/ppc-mmu.h
index 8546b0fb..8e4b3595 100644
--- a/Kernel/HALKit/POWER/ppc-mmu.h
+++ b/Kernel/HALKit/POWER/ppc-mmu.h
@@ -411,7 +411,7 @@ extern void print_bats(void);
#define MAS0_TLBSEL(x) (((x) << 28) & MAS0_TLBSEL_MSK)
#define MAS0_ESEL_MSK 0x0FFF0000
#define MAS0_ESEL(x) (((x) << 16) & MAS0_ESEL_MSK)
-#define MAS0_NV(x) ((x)&0x00000FFF)
+#define MAS0_NV(x) ((x) & 0x00000FFF)
#define MAS1_VALID 0x80000000
#define MAS1_IPROT 0x40000000
@@ -468,9 +468,9 @@ extern void print_bats(void);
(((ts) << 12) & MAS1_TS) | \
(MAS1_TSIZE(tsize)))
#define FSL_BOOKE_MAS2(epn, wimge) \
- (((epn)&MAS3_RPN) | (wimge))
+ (((epn) & MAS3_RPN) | (wimge))
#define FSL_BOOKE_MAS3(rpn, user, perms) \
- (((rpn)&MAS3_RPN) | (user) | (perms))
+ (((rpn) & MAS3_RPN) | (user) | (perms))
#define FSL_BOOKE_MAS7(rpn) \
(((uint64_t)(rpn)) >> 32)
@@ -638,10 +638,10 @@ extern int num_tlb_entries;
/* Some handy macros */
-#define EPN(e) ((e)&0xfffffc00)
+#define EPN(e) ((e) & 0xfffffc00)
#define TLB0(epn, sz) ((EPN((epn)) | (sz) | TLB_VALID))
-#define TLB1(rpn, erpn) (((rpn)&0xfffffc00) | (erpn))
-#define TLB2(a) ((a)&0x00000fbf)
+#define TLB1(rpn, erpn) (((rpn) & 0xfffffc00) | (erpn))
+#define TLB2(a) ((a) & 0x00000fbf)
#define tlbtab_start \
mflr r1; \
generated by cgit v1.2.3 (git 2.39.1) at 2026-04-06 12:51:40 +0000