diff options
Diffstat (limited to 'Kernel')
| -rw-r--r-- | Kernel/HALKit/AMD64/HalAPIC.cxx | 36 | ||||
| -rw-r--r-- | Kernel/HALKit/AMD64/HalBoot.asm (renamed from Kernel/HALKit/AMD64/HalNewBoot.asm) | 0 | ||||
| -rw-r--r-- | Kernel/HALKit/AMD64/HalCoreInterruptHandlerAMD64.cxx (renamed from Kernel/HALKit/AMD64/HalCoreInterruptHandlerAMD64.cpp) | 0 | ||||
| -rw-r--r-- | Kernel/HALKit/AMD64/HalCoreMultiProcessingAMD64.cxx (renamed from Kernel/HALKit/AMD64/HalCoreMultiProcessingAMD64.cpp) | 25 | ||||
| -rw-r--r-- | Kernel/HALKit/AMD64/HalInterruptAPI.asm | 2 | ||||
| -rw-r--r-- | Kernel/HALKit/AMD64/Hypervisor.hpp | 1 | ||||
| -rw-r--r-- | Kernel/HALKit/AMD64/Processor.hpp | 85 | ||||
| -rw-r--r-- | Kernel/NewKit/Macros.hpp | 2 | ||||
| -rw-r--r-- | Kernel/amd64-efi.make | 2 |
9 files changed, 102 insertions, 51 deletions
diff --git a/Kernel/HALKit/AMD64/HalAPIC.cxx b/Kernel/HALKit/AMD64/HalAPIC.cxx new file mode 100644 index 00000000..a148acf9 --- /dev/null +++ b/Kernel/HALKit/AMD64/HalAPIC.cxx @@ -0,0 +1,36 @@ +/* ------------------------------------------- + + Copyright Zeta Electronics Corporation + +------------------------------------------- */ + +#include <Modules/ACPI/ACPIFactoryInterface.hxx> +#include <HALKit/AMD64/Processor.hpp> + +namespace Kernel::HAL +{ + /// @brief Read from APIC controller. + /// @param reg register. + UInt32 APICController::Read(UInt32 reg) noexcept + { + MUST_PASS(this->fApic); + + UInt32 volatile* ioapic = (UInt32 volatile*)this->fApic; + ioapic[0] = (reg & 0xff); + + return ioapic[4]; + } + + /// @brief Write to APIC controller. + /// @param reg register. + /// @param value value. + Void APICController::Write(UInt32 reg, UInt32 value) noexcept + { + MUST_PASS(this->fApic); + + UInt32 volatile* ioapic = (UInt32 volatile*)this->fApic; + + ioapic[0] = (reg & 0xFF); + ioapic[4] = value; + } +} // namespace Kernel::HAL diff --git a/Kernel/HALKit/AMD64/HalNewBoot.asm b/Kernel/HALKit/AMD64/HalBoot.asm index 5f0342a3..5f0342a3 100644 --- a/Kernel/HALKit/AMD64/HalNewBoot.asm +++ b/Kernel/HALKit/AMD64/HalBoot.asm diff --git a/Kernel/HALKit/AMD64/HalCoreInterruptHandlerAMD64.cpp b/Kernel/HALKit/AMD64/HalCoreInterruptHandlerAMD64.cxx index f41ee55e..f41ee55e 100644 --- a/Kernel/HALKit/AMD64/HalCoreInterruptHandlerAMD64.cpp +++ b/Kernel/HALKit/AMD64/HalCoreInterruptHandlerAMD64.cxx diff --git a/Kernel/HALKit/AMD64/HalCoreMultiProcessingAMD64.cpp b/Kernel/HALKit/AMD64/HalCoreMultiProcessingAMD64.cxx index 8f619b4f..cb7b1eeb 100644 --- a/Kernel/HALKit/AMD64/HalCoreMultiProcessingAMD64.cpp +++ b/Kernel/HALKit/AMD64/HalCoreMultiProcessingAMD64.cxx @@ -162,11 +162,6 @@ namespace Kernel::HAL STATIC HAL::StackFramePtr cFramePtr = nullptr; STATIC Int32 cSMPInterrupt = 34; - EXTERN_C Void hal_apic_acknowledge_cont(Void) - { - kcout << "newoskrnl: Acknowledged.\r"; - } - /// @brief Current context getter. /// @retval StackFramePtr the current context. EXTERN_C StackFramePtr _hal_leak_current_context(Void) @@ -176,7 +171,6 @@ namespace Kernel::HAL EXTERN_C Void hal_apic_acknowledge(Void) { - hal_apic_acknowledge_cont(); } EXTERN_C Void _hal_switch_context(HAL::StackFramePtr stackFrame) @@ -198,7 +192,7 @@ namespace Kernel::HAL STATIC auto cAPICAddress = 0x0FEC00000; - STATIC void cpu_set_apic_base(UIntPtr apic) + STATIC Void cpu_set_apic_base(UIntPtr apic) { UInt32 edx = 0; UInt32 eax = (apic & 0xfffff0000) | kAPIC_BASE_MSR_ENABLE; @@ -208,7 +202,7 @@ namespace Kernel::HAL hal_set_msr(kAPIC_BASE_MSR, eax, edx); } - STATIC UIntPtr cpu_get_apic_base() + STATIC UIntPtr cpu_get_apic_base(Void) { UInt32 eax, edx; @@ -228,9 +222,6 @@ namespace Kernel::HAL { MadtType* madt = reinterpret_cast<MadtType*>(kApicMadt); - const auto cMaxProbableCores = madt->Length / sizeof(MadtType::MadtAddress); // the amount of cores we want. - constexpr auto cStartAt = 0; // start here to avoid boot core. - cpu_set_apic_base(cpu_get_apic_base()); // set SVR register to bit 8 to start recieve interrupts. @@ -239,18 +230,6 @@ namespace Kernel::HAL flagsSet |= 0x100; Kernel::ke_dma_write(cAPICAddress, 0xF0, flagsSet | 0x100); - - for (SizeT coreAt = cStartAt; coreAt < cMaxProbableCores; ++coreAt) - { - MadtType::MadtAddress& madtRecord = madt->MadtRecords[coreAt]; - - kApicMadtAddresses[kApicMadtAddressesCount].fAddress = madtRecord.Address; - kApicMadtAddresses[kApicMadtAddressesCount].fKind = madt->MadtRecords[coreAt].RecordType; - - kcout << "newoskrnl: register ipi...\r"; - - ++kApicMadtAddressesCount; - } } else { diff --git a/Kernel/HALKit/AMD64/HalInterruptAPI.asm b/Kernel/HALKit/AMD64/HalInterruptAPI.asm index 4e9ace6f..7c483d95 100644 --- a/Kernel/HALKit/AMD64/HalInterruptAPI.asm +++ b/Kernel/HALKit/AMD64/HalInterruptAPI.asm @@ -132,7 +132,7 @@ __NEW_INT_34: mov rax, 0 ;; tell there local apic that we're done. - mov [cAPICAddress + 0xB0], rax ; send end of interrupt. + mov qword [cAPICAddress + 0xB0], rax ; send end of interrupt. iretq diff --git a/Kernel/HALKit/AMD64/Hypervisor.hpp b/Kernel/HALKit/AMD64/Hypervisor.hpp index 1ab69ef4..fd7b70f2 100644 --- a/Kernel/HALKit/AMD64/Hypervisor.hpp +++ b/Kernel/HALKit/AMD64/Hypervisor.hpp @@ -21,6 +21,5 @@ namespace Kernel ENUM_STRING(ParallelsAlt, " lrpepyh vr "); ENUM_STRING(Bhyve, "bhyve bhyve "); ENUM_STRING(Qnx, " QNXQVMBSQG "); - END_STRING_ENUM() } // namespace Kernel diff --git a/Kernel/HALKit/AMD64/Processor.hpp b/Kernel/HALKit/AMD64/Processor.hpp index ff7045c2..8ec0b6f6 100644 --- a/Kernel/HALKit/AMD64/Processor.hpp +++ b/Kernel/HALKit/AMD64/Processor.hpp @@ -19,7 +19,10 @@ #include <FirmwareKit/Handover.hxx> #include <HALKit/AMD64/HalPageAlloc.hpp> +EXTERN_C +{ #include <cpuid.h> +} #ifdef kCPUBackendName #undef kCPUBackendName @@ -73,16 +76,17 @@ namespace Kernel::HAL { UInt16 pml4_index = (virt_addr >> 39) & 0x1FF; - if (!pde->Pte[pml4_index].Present) + if (pde && !pde->Pte[pml4_index].Present) { pde->Pte[pml4_index].Present = true; - kcout << "PM is present now.\r"; pde->Pte[pml4_index].PhysicalAddress = phys_addr; pde->Pte[pml4_index].Rw = flags & eFlagsRw; pde->Pte[pml4_index].User = flags & eFlagsUser; pde->Pte[pml4_index].ExecDisable = flags & eFlagsExecDisable; + kcout << "PTE is present now.\r"; + return 0; } else @@ -92,13 +96,13 @@ namespace Kernel::HAL kcout << "PhysicalAddress: " << hex_number(pde->Pte[pml4_index].PhysicalAddress); kcout << "\r"; - kcout << "User: " << (pde->Pte[pml4_index].User ? "YES" : "NO") << "\r"; - kcout << "RW: " << (pde->Pte[pml4_index].Rw ? "YES" : "NO") << "\r"; + kcout << "User: " << (pde->Pte[pml4_index].User ? "true" : "false") << "\r"; + kcout << "RW: " << (pde->Pte[pml4_index].Rw ? "true" : "false") << "\r"; - return 1; + return 0; } - return 0; + return 1; } /// @brief Map address to PDE. @@ -106,7 +110,7 @@ namespace Kernel::HAL /// @param phys_addr /// @param virt_addr /// @param flags - inline void ke_unmap_address(PDE* pde, UIntPtr phys_addr, UIntPtr virt_addr, UInt32 flags) + inline Void ke_unmap_address(PDE* pde, UIntPtr phys_addr, UIntPtr virt_addr, UInt32 flags) { UInt16 pml4_index = (virt_addr >> 39) & 0x1FF; @@ -202,11 +206,12 @@ namespace Kernel::HAL class SegmentDescriptorComparator final { public: - bool IsValid(SegmentDescriptor& seg) + Bool IsValid(SegmentDescriptor& seg) { return seg.Base > seg.Limit; } - bool Equals(SegmentDescriptor& seg, SegmentDescriptor& segRight) + + Bool Equals(SegmentDescriptor& seg, SegmentDescriptor& segRight) { return seg.Base == segRight.Base && seg.Limit == segRight.Limit; } @@ -217,21 +222,24 @@ namespace Kernel::HAL class GDTLoader final { public: - static void Load(RegisterGDT& gdt); - static void Load(Ref<RegisterGDT>& gdt); + static Void Load(RegisterGDT& gdt); + static Void Load(Ref<RegisterGDT>& gdt); }; class IDTLoader final { public: - static void Load(Register64& idt); - static void Load(Ref<Register64>& idt); + static Void Load(Register64& idt); + static Void Load(Ref<Register64>& idt); }; Void hal_system_get_cores(VoidPtr rsdPtr); Void hal_send_start_ipi(UInt32 apicId, UInt8 vector, UInt32 targetAddress); Void hal_send_end_ipi(UInt32 apicId, UInt8 vector, UInt32 targetAddress); + /// @brief Do a cpuid to check if MSR exists on CPU. + /// @retval true it does exists. + /// @retval false it doesn't. inline Bool hal_has_msr() noexcept { static UInt32 eax, unused, edx; // eax, edx @@ -242,13 +250,24 @@ namespace Kernel::HAL return edx & (1 << 5); } + /// @brief Get Model-specific register. + /// @param msr MSR + /// @param lo low byte + /// @param hi high byte inline Void hal_get_msr(UInt32 msr, UInt32* lo, UInt32* hi) noexcept { + if (!lo || !hi) + return; + asm volatile("rdmsr" : "=a"(*lo), "=d"(*hi) : "c"(msr)); } + /// @brief Set Model-specific register. + /// @param msr MSR + /// @param lo low byte + /// @param hi high byte inline Void hal_set_msr(UInt32 msr, UInt32 lo, UInt32 hi) noexcept { asm volatile("wrmsr" @@ -256,14 +275,12 @@ namespace Kernel::HAL : "a"(lo), "d"(hi), "c"(msr)); } - /// @brief Processor specific structures. + /// @brief Processor specific namespace. namespace Detail { - EXTERN_C void _ke_power_on_self_test(void); - /** - @brief Global descriptor table entry, either null, code or data. -*/ + @brief Global descriptor table entry, either null, code or data. + */ struct PACKED NewOSGDTRecord final { @@ -285,15 +302,35 @@ namespace Kernel::HAL NewOSGDTRecord UserData; }; } // namespace Detail + + class APICController + { + public: + explicit APICController(VoidPtr base) + : fApic(base) + { + } + + ~APICController() = default; + + NEWOS_COPY_DEFAULT(APICController); + + public: + UInt32 Read(UInt32 reg) noexcept; + Void Write(UInt32 reg, UInt32 value) noexcept; + + private: + VoidPtr fApic{nullptr}; + }; } // namespace Kernel::HAL -EXTERN_C void idt_handle_generic(Kernel::UIntPtr rsp); -EXTERN_C void idt_handle_gpf(Kernel::UIntPtr rsp); -EXTERN_C void idt_handle_math(Kernel::UIntPtr rsp); -EXTERN_C void idt_handle_pf(Kernel::UIntPtr rsp); +EXTERN_C Kernel::Void idt_handle_generic(Kernel::UIntPtr rsp); +EXTERN_C Kernel::Void idt_handle_gpf(Kernel::UIntPtr rsp); +EXTERN_C Kernel::Void idt_handle_math(Kernel::UIntPtr rsp); +EXTERN_C Kernel::Void idt_handle_pf(Kernel::UIntPtr rsp); -EXTERN_C void hal_load_idt(Kernel::HAL::Register64 ptr); -EXTERN_C void hal_load_gdt(Kernel::HAL::RegisterGDT ptr); +EXTERN_C Kernel::Void hal_load_idt(Kernel::HAL::Register64 ptr); +EXTERN_C Kernel::Void hal_load_gdt(Kernel::HAL::RegisterGDT ptr); /// @brief Maximum size of the IDT. #define kKernelIdtSize 0x100 diff --git a/Kernel/NewKit/Macros.hpp b/Kernel/NewKit/Macros.hpp index 913ad7cf..b45d5b04 100644 --- a/Kernel/NewKit/Macros.hpp +++ b/Kernel/NewKit/Macros.hpp @@ -79,7 +79,7 @@ #endif #ifndef ENUM_STRING -#define ENUM_STRING(NAME, VAL) inline constexpr const char* NAME = VAL +#define ENUM_STRING(NAME, VAL) inline constexpr const char* e##NAME = VAL #endif #ifndef END_STRING_ENUM diff --git a/Kernel/amd64-efi.make b/Kernel/amd64-efi.make index b25685e2..83b4fd3d 100644 --- a/Kernel/amd64-efi.make +++ b/Kernel/amd64-efi.make @@ -59,7 +59,7 @@ newos-amd64-epm: clean $(wildcard HALKit/AMD64/*.s) $(ASM) $(ASMFLAGS) HALKit/AMD64/HalInterruptAPI.asm $(ASM) $(ASMFLAGS) HALKit/AMD64/HalSMPCoreManager.asm - $(ASM) $(ASMFLAGS) HALKit/AMD64/HalNewBoot.asm + $(ASM) $(ASMFLAGS) HALKit/AMD64/HalBoot.asm $(ASM) $(ASMFLAGS) HALKit/AMD64/HalInstallTIB.asm $(MOVEALL) |