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-rw-r--r--KernelKit/PCI/Database.hpp38
-rw-r--r--KernelKit/PCI/Device.hpp84
-rw-r--r--KernelKit/PCI/Dma.hpp82
-rw-r--r--KernelKit/PCI/Dma.inl23
-rw-r--r--KernelKit/PCI/Express.hpp12
-rw-r--r--KernelKit/PCI/IO.hpp77
-rw-r--r--KernelKit/PCI/Iterator.hpp36
-rw-r--r--KernelKit/PCI/PCI.hpp56
8 files changed, 408 insertions, 0 deletions
diff --git a/KernelKit/PCI/Database.hpp b/KernelKit/PCI/Database.hpp
new file mode 100644
index 00000000..b709ac66
--- /dev/null
+++ b/KernelKit/PCI/Database.hpp
@@ -0,0 +1,38 @@
+/*
+ * ========================================================
+ *
+ * hCore
+ * Copyright XPX Corp, all rights reserved.
+ *
+ * ========================================================
+ */
+#pragma once
+
+#include <KernelKit/PCI/Device.hpp>
+#include <NewKit/Defines.hpp>
+
+namespace hCore {
+ namespace Types {
+ // https://wiki.osdev.org/PCI
+ enum class PciDeviceKind : UChar {
+ MassStorageController = 0x1,
+ NetworkController = 0x2,
+ DisplayController = 0x3,
+ MultimediaController = 0x4,
+ MemoryController = 0x5,
+ Bridge = 0x6,
+ CommunicationController = 0x7,
+ GenericSystemPeripheral = 0x8,
+ InputDeviceController = 0x9,
+ DockingStation = 0xa,
+ Processor = 0xb,
+ SerialBusController = 0xc,
+ WirelessController = 0xd,
+ IntelligentController = 0xe,
+ SatelliteCommunicationsController = 0xf,
+ CoProcessor = 0x40,
+ Unassgined = 0xf,
+ Invalid = Unassgined,
+ };
+ } // namespace Types
+} // namespace hCore
diff --git a/KernelKit/PCI/Device.hpp b/KernelKit/PCI/Device.hpp
new file mode 100644
index 00000000..9c89e1b5
--- /dev/null
+++ b/KernelKit/PCI/Device.hpp
@@ -0,0 +1,84 @@
+/*
+ * ========================================================
+ *
+ * hCore
+ * Copyright XPX Corp, all rights reserved.
+ *
+ * ========================================================
+ */
+#pragma once
+
+#include <NewKit/Defines.hpp>
+
+namespace hCore::PCI
+{
+ enum class PciConfigKind : UShort
+ {
+ ConfigAddress = 0xCF8,
+ ConfigData = 0xCFC,
+ Invalid = 0xFFF
+ };
+
+ class Device final
+ {
+ public:
+ Device() = default;
+
+ public:
+ explicit Device(UShort bus, UShort device, UShort function, UShort bar);
+
+ Device &operator=(const Device &) = default;
+
+ Device(const Device &) = default;
+
+ ~Device();
+
+ public:
+ UInt Read(UInt bar, Size szData);
+ void Write(UInt bar, UIntPtr data, Size szData);
+
+ public:
+ operator bool();
+
+ public:
+ template<typename T>
+ UInt Read(UInt bar)
+ {
+ static_assert(sizeof(T) <= 4, "64-bit PCI addressing is unsupported");
+ return Read(bar, sizeof(T));
+ }
+
+ template<typename T>
+ void Write(UInt bar, UIntPtr data)
+ {
+ static_assert(sizeof(T) <= 4, "64-bit PCI addressing is unsupported");
+ Write(bar, data, sizeof(T));
+ }
+
+ public:
+ UShort DeviceId();
+ UShort VendorId();
+ UShort InterfaceId();
+ UChar Class();
+ UChar Subclass();
+ UChar ProgIf();
+ UChar HeaderType();
+
+ public:
+ void EnableMmio();
+ void BecomeBusMaster(); // for PCI-DMA, PC-DMA does not need that.
+
+ UShort Vendor();
+
+ private:
+ UShort m_Bus;
+ UShort m_Device;
+ UShort m_Function;
+ UShort m_Bar;
+
+ };
+} // namespace hCore::PCI
+
+
+extern "C" void LumiaPCISetCfgTarget(hCore::UInt bar);
+extern "C" hCore::UInt LumiaPCIReadRaw(hCore::UInt bar);
diff --git a/KernelKit/PCI/Dma.hpp b/KernelKit/PCI/Dma.hpp
new file mode 100644
index 00000000..518b6141
--- /dev/null
+++ b/KernelKit/PCI/Dma.hpp
@@ -0,0 +1,82 @@
+/*
+ * ========================================================
+ *
+ * hCore
+ * Copyright XPX Corp, all rights reserved.
+ *
+ * ========================================================
+ */
+
+#pragma once
+
+#include <KernelKit/Device.hpp>
+#include <KernelKit/PCI/Device.hpp>
+#include <NewKit/Array.hpp>
+#include <NewKit/OwnPtr.hpp>
+#include <NewKit/Ref.hpp>
+
+namespace hCore
+{
+ enum class DmaKind
+ {
+ PCI, // Bus mastering is required to be turned on. Basiaclly a request
+ // control system. 64-Bit access depends on the PAE bit and the device
+ // (if Double Address Cycle is available)
+ ISA, // Four DMA channels 0-3; 8 bit transfers and only a megabyte of RAM.
+ Invalid,
+ };
+
+ class DMAWrapper final
+ {
+ public:
+ DMAWrapper() = delete;
+
+ public:
+ DMAWrapper(nullPtr) = delete;
+ DMAWrapper(voidPtr Ptr, DmaKind Kind = DmaKind::PCI) : m_Address(Ptr), m_Kind(Kind) {}
+
+ public:
+ DMAWrapper &operator=(voidPtr Ptr);
+
+ public:
+ DMAWrapper &operator=(const DMAWrapper &) = default;
+ DMAWrapper(const DMAWrapper &) = default;
+
+ public:
+ ~DMAWrapper() = default;
+
+ template<class T>
+ T *operator->();
+
+ template<class T>
+ T *Get(const UIntPtr off = 0);
+
+ public:
+ operator bool();
+ bool operator!();
+
+ public:
+ bool Write(const UIntPtr &bit, const UIntPtr &offset);
+ UIntPtr Read(const UIntPtr &offset);
+ Boolean Check(UIntPtr offset) const;
+
+ public:
+ UIntPtr operator[](const UIntPtr &offset);
+
+ private:
+ voidPtr m_Address{nullptr};
+ DmaKind m_Kind{DmaKind::Invalid};
+
+ private:
+ friend class DMAFactory;
+ };
+
+ class DMAFactory final
+ {
+ public:
+ static OwnPtr<IOBuf<Char*>> Construct(OwnPtr <DMAWrapper> &dma);
+
+ };
+} // namespace hCore
+
+#include <KernelKit/PCI/Dma.inl>
diff --git a/KernelKit/PCI/Dma.inl b/KernelKit/PCI/Dma.inl
new file mode 100644
index 00000000..c99d3ae3
--- /dev/null
+++ b/KernelKit/PCI/Dma.inl
@@ -0,0 +1,23 @@
+/*
+ * ========================================================
+ *
+ * hCore
+ * Copyright Mahrouss Logic, all rights reserved.
+ *
+ * ========================================================
+ */
+
+namespace hCore
+{
+ template<class T>
+ T* DMAWrapper::operator->()
+ {
+ return m_Address;
+ }
+
+ template<class T>
+ T* DMAWrapper::Get(const UIntPtr offset)
+ {
+ return reinterpret_cast<T*>((UIntPtr) m_Address + offset);
+ }
+}
diff --git a/KernelKit/PCI/Express.hpp b/KernelKit/PCI/Express.hpp
new file mode 100644
index 00000000..d53d636a
--- /dev/null
+++ b/KernelKit/PCI/Express.hpp
@@ -0,0 +1,12 @@
+/*
+ * ========================================================
+ *
+ * hCore
+ * Copyright XPX Corp, all rights reserved.
+ *
+ * ========================================================
+ */
+
+#pragma once
+
+#include <NewKit/Defines.hpp> \ No newline at end of file
diff --git a/KernelKit/PCI/IO.hpp b/KernelKit/PCI/IO.hpp
new file mode 100644
index 00000000..95f8f9db
--- /dev/null
+++ b/KernelKit/PCI/IO.hpp
@@ -0,0 +1,77 @@
+/*
+ * ========================================================
+ *
+ * hCore
+ * Copyright XPX Corp, all rights reserved.
+ *
+ * ========================================================
+ */
+
+#pragma once
+
+#include <NewKit/Defines.hpp>
+
+#include <ArchKit/Arch.hpp>
+#include <NewKit/Array.hpp>
+#include <NewKit/Ref.hpp>
+
+namespace hCore
+{
+template<SizeT Sz>
+class IOArray final
+{
+ public:
+ IOArray() = delete;
+
+ IOArray(nullPtr) = delete;
+
+ explicit IOArray(Array <UShort, Sz> &ports) : m_Ports(ports) {}
+ ~IOArray() {}
+
+ IOArray &operator=(const IOArray &) = default;
+
+ IOArray(const IOArray &) = default;
+
+ operator bool() {
+ return !m_Ports.Empty();
+ }
+
+ public:
+ template<typename T>
+ T In(SizeT index) {
+ switch (sizeof(T)) {
+#ifdef __x86_64__
+ case 4:
+ return HAL::in32(m_Ports[index].Leak());
+ case 2:
+ return HAL::in16(m_Ports[index].Leak());
+ case 1:
+ return HAL::in8(m_Ports[index].Leak());
+#endif
+ default:
+ return 0xFFFF;
+ }
+ }
+
+ template<typename T>
+ void Out(SizeT index, T value) {
+ switch (sizeof(T)) {
+#ifdef __x86_64__
+ case 4:
+ HAL::out32(m_Ports[index].Leak(), value);
+ case 2:
+ HAL::out16(m_Ports[index].Leak(), value);
+ case 1:
+ HAL::out8(m_Ports[index].Leak(), value);
+#endif
+ default:
+ break;
+ }
+ }
+
+ private:
+ Array <UShort, Sz> m_Ports;
+};
+
+using IOArray16 = IOArray<16>;
+} // namespace hCore
diff --git a/KernelKit/PCI/Iterator.hpp b/KernelKit/PCI/Iterator.hpp
new file mode 100644
index 00000000..70fbe59a
--- /dev/null
+++ b/KernelKit/PCI/Iterator.hpp
@@ -0,0 +1,36 @@
+#ifndef __PCI_ITERATOR_HPP__
+#define __PCI_ITERATOR_HPP__
+
+#include <KernelKit/PCI/Database.hpp>
+#include <KernelKit/PCI/Device.hpp>
+#include <NewKit/Array.hpp>
+#include <NewKit/Defines.hpp>
+#include <NewKit/Ref.hpp>
+
+#define ME_BUS_COUNT (256)
+#define ME_DEVICE_COUNT (33)
+#define ME_FUNCTION_COUNT (8)
+
+namespace hCore::PCI {
+ class Iterator final {
+ public:
+ Iterator() = delete;
+
+ public:
+ explicit Iterator(const Types::PciDeviceKind &deviceType);
+
+ Iterator &operator=(const Iterator &) = default;
+
+ Iterator(const Iterator &) = default;
+
+ ~Iterator();
+
+ public:
+ Ref<PCI::Device> operator[](const Size &sz);
+
+ private:
+ Array<PCI::Device, ME_BUS_COUNT> m_Devices;
+ };
+} // namespace hCore::PCI
+
+#endif // __PCI_ITERATOR_HPP__
diff --git a/KernelKit/PCI/PCI.hpp b/KernelKit/PCI/PCI.hpp
new file mode 100644
index 00000000..c5533684
--- /dev/null
+++ b/KernelKit/PCI/PCI.hpp
@@ -0,0 +1,56 @@
+/*
+ * ========================================================
+ *
+ * hCore
+ * Copyright XPX Corp, all rights reserved.
+ *
+ * ========================================================
+ */
+#pragma once
+
+#include <NewKit/Defines.hpp>
+
+#define PCI_CONFIG_ADDRESS (0xCF8)
+#define PCI_CONFIG_DATA (0xCFC)
+
+#define PCI_DEVICE_COUNT (32)
+#define PCI_FUNC_COUNT (8)
+#define PCI_BUS_COUNT (255)
+
+namespace hCore::PCI {
+// model
+ struct DeviceHeader {
+ UInt16 VendorId;
+ UInt16 DeviceId;
+ UInt8 Command;
+ UInt8 Status;
+ UInt8 RevisionId;
+ UInt8 ProgIf;
+ UInt8 SubClass;
+ UInt8 Class;
+ UInt8 CacheLineSz;
+ UInt8 LatencyTimer;
+ UInt8 HeaderType;
+ UInt8 Bist;
+ UInt8 Bus;
+ UInt8 Device;
+ UInt8 Function;
+ };
+
+ namespace Detail {
+ class BAR {
+ public:
+ UIntPtr BAR;
+ SizeT Size;
+ };
+ } // namespace Detail
+
+ class BAR {
+ public:
+ Detail::BAR BAR1;
+ Detail::BAR BAR2;
+ Detail::BAR BAR3;
+ Detail::BAR BAR4;
+ Detail::BAR BAR5;
+ };
+} // namespace hCore::PCI
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