diff options
Diffstat (limited to 'Private/Builtins')
23 files changed, 791 insertions, 0 deletions
diff --git a/Private/Builtins/.gitkeep b/Private/Builtins/.gitkeep new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/Private/Builtins/.gitkeep diff --git a/Private/Builtins/ACPI/.gitkeep b/Private/Builtins/ACPI/.gitkeep new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/Private/Builtins/ACPI/.gitkeep diff --git a/Private/Builtins/ACPI/ACPI.hpp b/Private/Builtins/ACPI/ACPI.hpp new file mode 100644 index 00000000..1a4329fc --- /dev/null +++ b/Private/Builtins/ACPI/ACPI.hpp @@ -0,0 +1,67 @@ +/* ------------------------------------------- + + Copyright Mahrouss Logic + +------------------------------------------- */ + +#ifndef __ACPI__ +#define __ACPI__ + +/** + https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html + https://wiki.osdev.org/RSDT +*/ + +#include <NewKit/Defines.hpp> + +namespace HCore { +class SDT { + public: + Char Signature[4]; + UInt32 Length; + UInt8 Revision; + Char Checksum; + Char OemId[6]; + Char OemTableId[8]; + UInt32 OemRev; + UInt32 CreatorID; + UInt32 CreatorRevision; +}; + +class RSDP : public SDT { + public: + UInt32 RsdtAddress; + UIntPtr XsdtAddress; + UInt8 ExtendedChecksum; + UInt8 Reserved0[3]; +}; + +class ConfigHeader { + public: + UInt64 BaseAddress; + UInt16 PciSegGroup; + UInt8 StartBus; + UInt8 EndBus; + UInt32 Reserved; +}; + +enum class AddressSpace : UInt8 { + SystemMemory = 0, + SystemIO = 1, + Pci = 2, + Controller = 3, + SmBus = 4, + Invalid = 0xFF, +}; + +class Address { + public: + AddressSpace AddressSpaceId; + UInt8 RegisterBitWidth; + UInt8 RegisterBitOffset; + UInt8 Reserved; + UIntPtr Address; +}; +} // namespace HCore + +#endif // !__ACPI__ diff --git a/Private/Builtins/ACPI/ACPIManager.hxx b/Private/Builtins/ACPI/ACPIManager.hxx new file mode 100644 index 00000000..1fa5e714 --- /dev/null +++ b/Private/Builtins/ACPI/ACPIManager.hxx @@ -0,0 +1,44 @@ +/* ------------------------------------------- + + Copyright Mahrouss Logic + +------------------------------------------- */ + +#ifndef __ACPI_MANAGER__ +#define __ACPI_MANAGER__ + +#include <Builtins/ACPI/ACPI.hpp> +#include <KernelKit/DebugOutput.hpp> +#include <NewKit/Defines.hpp> +#include <NewKit/Ref.hpp> + +namespace HCore { +class ACPIManager final { + public: + explicit ACPIManager(voidPtr rsdPtr); + ~ACPIManager() = default; + + ACPIManager &operator=(const ACPIManager &) = default; + ACPIManager(const ACPIManager &) = default; + + public: + void Shutdown(); // shutdown + void Reset(); // soft-reboot + + ErrorOr<voidPtr> Find(const char *signature); + + bool Checksum(const char *checksum, SSizeT len); // watch for collides! + + public: + ErrorOr<voidPtr> operator[](const char *signature) { + return this->Find(signature); + } + + private: + VoidPtr m_Rsdp; // pointer to root descriptor. + SSizeT m_Entries; // number of entries, -1 tells that no invalid entries were + // found. +}; +} // namespace HCore + +#endif // !__ACPI_MANAGER__ diff --git a/Private/Builtins/ACPI/compile_flags.txt b/Private/Builtins/ACPI/compile_flags.txt new file mode 100644 index 00000000..1bc51142 --- /dev/null +++ b/Private/Builtins/ACPI/compile_flags.txt @@ -0,0 +1,4 @@ +-I./ +-I../ +-I../../ +-std=c++20 diff --git a/Private/Builtins/AHCI/.gitkeep b/Private/Builtins/AHCI/.gitkeep new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/Private/Builtins/AHCI/.gitkeep diff --git a/Private/Builtins/AHCI/API.hxx b/Private/Builtins/AHCI/API.hxx new file mode 100644 index 00000000..90e68bad --- /dev/null +++ b/Private/Builtins/AHCI/API.hxx @@ -0,0 +1,24 @@ +/* ------------------------------------------- + + Copyright Mahrouss Logic + + File: API.hxx + Purpose: AHCI API. + + Revision History: + + 03/17/24: Added file (amlel) + +------------------------------------------- */ + +#pragma once + +#include <AHCI/Defines.hxx> +#include <NewKit/Defines.hpp> +#include <ObjectKit/Object.hxx> + +#define kObjectAHCINamespace "AHCI_DRV\\" + +namespace HCore::Builtins { +inline Boolean ke_get_ahci_handle(ObjectPtr* ppAhciObject); +} // namespace HCore::Builtins
\ No newline at end of file diff --git a/Private/Builtins/AHCI/Defines.hxx b/Private/Builtins/AHCI/Defines.hxx new file mode 100644 index 00000000..c1d3c063 --- /dev/null +++ b/Private/Builtins/AHCI/Defines.hxx @@ -0,0 +1,316 @@ +/* ------------------------------------------- + + Copyright Mahrouss Logic + + File: Defines.hxx + Purpose: AHCI header. + + Revision History: + + 03/02/24: Added file (amlel) + +------------------------------------------- */ + +#pragma once + +#include <NewKit/Defines.hpp> + +// Forward declarations of structs. + +struct HbaPort; +struct FisData; +struct FisRegD2H; +struct FisRegH2D; + +// Enum types + +typedef enum { + FIS_TYPE_REG_H2D = 0x27, // Register FIS - host to device + FIS_TYPE_REG_D2H = 0x34, // Register FIS - device to host + FIS_TYPE_DMA_ACT = 0x39, // DMA activate FIS - device to host + FIS_TYPE_DMA_SETUP = 0x41, // DMA setup FIS - bidirectional + FIS_TYPE_DATA = 0x46, // Data FIS - bidirectional + FIS_TYPE_BIST = 0x58, // BIST activate FIS - bidirectional + FIS_TYPE_PIO_SETUP = 0x5F, // PIO setup FIS - device to host + FIS_TYPE_DEV_BITS = 0xA1, // Set device bits FIS - device to host +} AHCI_FIS_TYPE; + +typedef enum { + AHCI_ATA_CMD_IDENTIFY = 0xEC, + AHCI_ATA_CMD_READ_DMA = 0xC8, + AHCI_ATA_CMD_READ_DMA_EX = 0x25, + AHCI_ATA_CMD_WRITE_DMA = 0xCA, + AHCI_ATA_CMD_WRITE_DMA_EX = 0x35 +} AHCI_FIS_COMMAND; + +typedef struct FisRegH2D final { + // DWORD 0 + HCore::UInt8 fisType; // FIS_TYPE_REG_H2D + + HCore::UInt8 portMul : 4; // Port multiplier + HCore::UInt8 reserved0 : 3; // Reserved + HCore::UInt8 cmdOrCtrl : 1; // 1: Command, 0: Control + + HCore::UInt8 command; // Command register + HCore::UInt8 featurel; // Feature register, 7:0 + + // DWORD 1 + HCore::UInt8 lba0; // LBA low register, 7:0 + HCore::UInt8 lba1; // LBA mid register, 15:8 + HCore::UInt8 lba2; // LBA high register, 23:16 + HCore::UInt8 device; // Device register + + // DWORD 2 + HCore::UInt8 lba3; // LBA register, 31:24 + HCore::UInt8 lba4; // LBA register, 39:32 + HCore::UInt8 lba5; // LBA register, 47:40 + HCore::UInt8 featureHigh; // Feature register, 15:8 + + // DWORD 3 + HCore::UInt8 countLow; // Count register, 7:0 + HCore::UInt8 countHigh; // Count register, 15:8 + HCore::UInt8 icc; // Isochronous command completion + HCore::UInt8 control; // Control register + + // DWORD 4 + HCore::UInt8 reserved1[4]; // Reserved +} FisRegH2D; + +typedef struct FisRegD2H final { + // DWORD 0 + HCore::UInt8 fisType; // FIS_TYPE_REG_D2H + + HCore::UInt8 portMul : 4; // Port multiplier + HCore::UInt8 reserved0 : 2; // Reserved + HCore::UInt8 interruptBit : 1; // Interrupt bit + HCore::UInt8 reserved1 : 1; // Reserved + + HCore::UInt8 status; // Status register + HCore::UInt8 error; // Error register + + // DWORD 1 + HCore::UInt8 lba0; // LBA low register, 7:0 + HCore::UInt8 lba1; // LBA mid register, 15:8 + HCore::UInt8 lba2; // LBA high register, 23:16 + HCore::UInt8 device; // Device register + + // DWORD 2 + HCore::UInt8 lba3; // LBA register, 31:24 + HCore::UInt8 lba4; // LBA register, 39:32 + HCore::UInt8 lba5; // LBA register, 47:40 + HCore::UInt8 rsv2; // Reserved + + // DWORD 3 + HCore::UInt8 countLow; // Count register, 7:0 + HCore::UInt8 countHigh; // Count register, 15:8 + HCore::UInt8 rsv3[2]; // Reserved + + // DWORD 4 + HCore::UInt8 rsv4[4]; // Reserved +} FisRegD2H; + +typedef struct FisData final { + // DWORD 0 + HCore::UInt8 fisType; // FIS_TYPE_DATA + + HCore::UInt8 portMul : 4; // Port multiplier + HCore::UInt8 reserved0 : 4; // Reserved + + HCore::UInt8 reserved1[2]; // Reserved + + // DWORD 1 ~ N + HCore::UInt32 data[1]; // Payload +} FisData; + +typedef struct FisPioSetup final { + // DWORD 0 + HCore::UInt8 fisType; // FIS_TYPE_PIO_SETUP + + HCore::UInt8 portMul : 4; // Port multiplier + HCore::UInt8 reserved0 : 1; // Reserved + HCore::UInt8 d : 1; // Data transfer direction, 1 - device to host + HCore::UInt8 interruptBit : 1; // Interrupt bit + HCore::UInt8 reserved1 : 1; + + HCore::UInt8 status; // Status register + HCore::UInt8 error; // Error register + + // DWORD 1 + HCore::UInt8 lba0; // LBA low register, 7:0 + HCore::UInt8 lba1; // LBA mid register, 15:8 + HCore::UInt8 lba2; // LBA high register, 23:16 + HCore::UInt8 device; // Device register + + // DWORD 2 + HCore::UInt8 lba3; // LBA register, 31:24 + HCore::UInt8 lba4; // LBA register, 39:32 + HCore::UInt8 lba5; // LBA register, 47:40 + HCore::UInt8 rsv2; // Reserved + + // DWORD 3 + HCore::UInt8 countLow; // Count register, 7:0 + HCore::UInt8 countHigh; // Count register, 15:8 + HCore::UInt8 rsv3; // Reserved + HCore::UInt8 eStatus; // New value of status register + + // DWORD 4 + HCore::UInt16 tc; // Transfer count + HCore::UInt8 rsv4[2]; // Reserved +} FisPioSetup; + +typedef struct FisDmaSetup final { + // DWORD 0 + HCore::UInt8 fisType; // FIS_TYPE_DMA_SETUP + + HCore::UInt8 portMul : 4; // Port multiplier + HCore::UInt8 reserved0 : 1; // Reserved + HCore::UInt8 dtd : 1; // Data transfer direction, 1 - device to host + HCore::UInt8 interruptBit : 1; // Interrupt bit + HCore::UInt8 + autoEnable : 1; // Auto-activate. Specifies if DMA Activate FIS is needed + + HCore::UInt8 reserved1[2]; // Reserved + + // DWORD 1&2 + HCore::UInt64 dmaBufferId; // DMA Buffer Identifier. Used to Identify DMA buffer in + // host memory. SATA Spec says host specific and not in + // Spec. Trying AHCI spec might work. + + // DWORD 3 + HCore::UInt32 rsvd; // More reserved + + // DWORD 4 + HCore::UInt32 dmabufOffset; // Byte offset into buffer. First 2 bits must be 0 + + // DWORD 5 + HCore::UInt32 transferCount; // Number of bytes to transfer. Bit 0 must be 0 + + // DWORD 6 + HCore::UInt32 reserved3; // Reserved +} FisDmaSetup; + +typedef struct FisDevBits final { + // DWORD 0 + HCore::UInt8 fisType; // FIS_TYPE_DMA_SETUP (A1h) + + HCore::UInt8 reserved0 : 5; // Reserved + HCore::UInt8 r0 : 1; + HCore::UInt8 interruptBit : 1; + HCore::UInt8 n : 1; + + HCore::UInt8 statusLow : 3; + HCore::UInt8 r1 : 1; + HCore::UInt8 statusHigh : 3; + + HCore::UInt8 r2 : 1; + HCore::UInt8 error; + + // DWORD 1 + HCore::UInt32 act; +} FisDevBits; + +/// \brief Enable AHCI device bit in GHC register. +#ifndef kAhciGHC_AE +#define kAhciGHC_AE (31) +#endif //! ifndef kAhciGHC_AE + +typedef struct HbaPort final { + HCore::UInt32 clb; // 0x00, command list base address, 1K-byte aligned + HCore::UInt32 clbu; // 0x04, command list base address upper 32 bits + HCore::UInt32 fb; // 0x08, FIS base address, 256-byte aligned + HCore::UInt32 fbu; // 0x0C, FIS base address upper 32 bits + HCore::UInt32 is; // 0x10, interrupt status + HCore::UInt32 ie; // 0x14, interrupt enable + HCore::UInt32 cmd; // 0x18, command and status + HCore::UInt32 reserved0; // 0x1C, Reserved + HCore::UInt32 tfd; // 0x20, task file data + HCore::UInt32 sig; // 0x24, signature + HCore::UInt32 ssts; // 0x28, SATA status (SCR0:SStatus) + HCore::UInt32 sctl; // 0x2C, SATA control (SCR2:SControl) + HCore::UInt32 serr; // 0x30, SATA error (SCR1:SError) + HCore::UInt32 sact; // 0x34, SATA active (SCR3:SActive) + HCore::UInt32 ci; // 0x38, command issue + HCore::UInt32 sntf; // 0x20, SATA notification (SCR4:SNotification) + HCore::UInt32 fbs; // 0x40, FIS-based switch control + HCore::UInt32 reserved1[11]; // 0x44 ~ 0x6F, Reserved + HCore::UInt32 vendor[4]; // 0x70 ~ 0x7F, vendor specific +} HbaPort; + +typedef struct HbaMem final { + // 0x00 - 0x2B, Generic Host Control + HCore::UInt32 cap; // 0x00, Host capability + HCore::UInt32 ghc; // 0x04, Global host control + HCore::UInt32 is; // 0x08, Interrupt status + HCore::UInt32 pi; // 0x0C, Port implemented + HCore::UInt32 vs; // 0x10, Version + HCore::UInt32 ccc_ctl; // 0x14, Command completion coalescing control + HCore::UInt32 ccc_pts; // 0x18, Command completion coalescing ports + HCore::UInt32 em_loc; // 0x1C, Enclosure management location + HCore::UInt32 em_ctl; // 0x20, Enclosure management control + HCore::UInt32 cap2; // 0x24, Host capabilities extended + HCore::UInt32 bohc; // 0x28, BIOS/OS handoff control and status + + HCore::UInt16 rsv; + HCore::UInt32 resv2; + + HbaPort ports[1]; // 1 ~ 32 +} HbaMem; + +typedef struct HbaCmdHeader final { + // DW0 + HCore::UInt8 cfl : 5; // Command FIS length in DWORDS, 2 ~ 16 + HCore::UInt8 atapi : 1; // ATAPI + HCore::UInt8 write : 1; // Write, 1: H2D, 0: D2H + HCore::UInt8 prefetchable : 1; // Prefetchable + + HCore::UInt8 reset : 1; // Reset + HCore::UInt8 BIST : 1; // BIST + HCore::UInt8 clear : 1; // Clear busy upon R_OK + HCore::UInt8 reserved0 : 1; // Reserved + HCore::UInt8 pmp : 4; // Port multiplier port + + HCore::UInt16 prdtl; // Physical region descriptor table length in entries + volatile HCore::UInt32 prdbc; // Physical region descriptor byte count transferred + + HCore::UInt32 ctba; // Command table descriptor base address + HCore::UInt32 ctbau; // Command table descriptor base address upper 32 bits + + HCore::UInt32 reserved1[4]; // Reserved +} HbaCmdHeader; + +typedef struct HbaFis final { + // 0x00 + FisDmaSetup dsfis; // DMA Setup FIS + HCore::UInt8 pad0[4]; + // 0x20 + FisPioSetup psfis; // PIO Setup FIS + HCore::UInt8 pad1[12]; + // 0x40 + FisRegD2H rfis; // Register – Device to Host FIS + HCore::UInt8 pad2[4]; + // 0x58 + FisDevBits sdbfis; // Set Device Bit FIS + // 0x60 + HCore::UInt8 ufis[64]; + // 0xA0 + HCore::UInt8 rsv[0x100 - 0xA0]; +} HbaFis; + +typedef struct HbaPrdtEntry final { + HCore::UInt32 dba; // Data base address + HCore::UInt32 dbau; // Data base address upper 32 bits + HCore::UInt32 reserved0; // Reserved + // DW3 + HCore::UInt32 dbc : 22; // Byte count, 4M max + HCore::UInt32 reserved1 : 9; // Reserved + HCore::UInt32 interruptBit : 1; // Interrupt on completion +} HbaPrdtEntry; + +typedef struct HbaCmdTbl final { + HCore::UInt8 cfis[64]; // Command FIS + HCore::UInt8 acmd[16]; // ATAPI command, 12 or 16 bytes + HCore::UInt8 rsv[48]; // Reserved + HbaPrdtEntry prdtEntries[1]; // Physical region descriptor table entries, 0 ~ 65535 +} HbaCmdTbl; + +/* EOF */ diff --git a/Private/Builtins/AHCI/compile_flags.txt b/Private/Builtins/AHCI/compile_flags.txt new file mode 100644 index 00000000..1bc51142 --- /dev/null +++ b/Private/Builtins/AHCI/compile_flags.txt @@ -0,0 +1,4 @@ +-I./ +-I../ +-I../../ +-std=c++20 diff --git a/Private/Builtins/ATA/Defines.hxx b/Private/Builtins/ATA/Defines.hxx new file mode 100644 index 00000000..a4a212bd --- /dev/null +++ b/Private/Builtins/ATA/Defines.hxx @@ -0,0 +1,120 @@ +/* ------------------------------------------- + + Copyright Mahrouss Logic + + File: Defines.hxx + Purpose: ATA header. + + Revision History: + + 03/02/24: Added file (amlel) + +------------------------------------------- */ + +#pragma once + +#include <CompilerKit/CompilerKit.hxx> +#include <NewKit/Defines.hpp> + +using namespace HCore; + +// Status register +#define ATA_SR_BSY 0x80 +#define ATA_SR_DRDY 0x40 +#define ATA_SR_DF 0x20 +#define ATA_SR_DSC 0x10 +#define ATA_SR_DRQ 0x08 +#define ATA_SR_CORR 0x04 +#define ATA_SR_IDX 0x02 +#define ATA_SR_ERR 0x01 + +// Error register +#define ATA_ER_BBK 0x80 +#define ATA_ER_UNC 0x40 +#define ATA_ER_MC 0x20 +#define ATA_ER_IDNF 0x10 +#define ATA_ER_MCR 0x08 +#define ATA_ER_ABRT 0x04 +#define ATA_ER_TK0NF 0x02 +#define ATA_ER_AMNF 0x01 + +#define ATA_CMD_READ_PIO 0x20 +#define ATA_CMD_READ_PIO_EXT 0x24 +#define ATA_CMD_READ_DMA 0xC8 +#define ATA_CMD_READ_DMA_EXT 0x25 +#define ATA_CMD_WRITE_PIO 0x30 +#define ATA_CMD_WRITE_PIO_EXT 0x34 +#define ATA_CMD_WRITE_DMA 0xCA +#define ATA_CMD_WRITE_DMA_EXT 0x35 +#define ATA_CMD_CACHE_FLUSH 0xE7 +#define ATA_CMD_CACHE_FLUSH_EXT 0xEA +#define ATA_CMD_PACKET 0xA0 +#define ATA_CMD_IDENTIFY_PACKET 0xA1 +#define ATA_CMD_IDENTIFY 0xEC + +#define ATA_IDENT_DEVICE_TYPE 0 +#define ATA_IDENT_CYLINDERS 2 +#define ATA_IDENT_HEADS 6 +#define ATA_IDENT_SECTORS 12 +#define ATA_IDENT_SERIAL 20 +#define ATA_IDENT_MODEL 54 +#define ATA_IDENT_CAPABILITIES 98 +#define ATA_IDENT_FIELDVALID 106 +#define ATA_IDENT_MAX_LBA 120 +#define ATA_IDENT_COMMANDSETS 164 +#define ATA_IDENT_MAX_LBA_EXT 200 + +#define ATA_MASTER 0x00 +#define ATA_SLAVE 0x01 + +// Register +#define ATA_REG_DATA 0x00 +#define ATA_REG_ERROR 0x01 +#define ATA_REG_FEATURES 0x01 +#define ATA_REG_SEC_COUNT0 0x02 +#define ATA_REG_LBA0 0x03 +#define ATA_REG_LBA1 0x04 +#define ATA_REG_LBA2 0x05 +#define ATA_REG_HDDEVSEL 0x06 +#define ATA_REG_COMMAND 0x07 +#define ATA_REG_STATUS 0x07 +#define ATA_REG_SEC_COUNT1 0x08 +#define ATA_REG_LBA3 0x09 +#define ATA_REG_LBA4 0x0A +#define ATA_REG_LBA5 0x0B +#define ATA_REG_CONTROL 0x0C +#define ATA_REG_ALT_STATUS 0x0C +#define ATA_REG_DEV_ADDRESS 0x0D + +#define ATA_REG_NEIN 0x01 + +#define ATA_PRIMARY_IO 0x1F0 +#define ATA_SECONDARY_IO 0x170 +#define ATA_PRIMARY_DCR_AS 0x3F6 +#define ATA_SECONDARY_DCR_AS 0x376 + +// Irq +#define ATA_PRIMARY_IRQ 14 +#define ATA_SECONDARY_IRQ 15 + +// Channels +#define ATA_PRIMARY 0x00 +#define ATA_SECONDARY 0x01 + +#define ATA_CYL_LOW 4 +#define ATA_CYL_HIGH 5 + +// IO Direction +#define ATA_READ 0x00 +#define ATA_WRITE 0x013 + +#define ATA_PRIMARY_SEL 0xA0 +#define ATA_SECONDARY_SEL 0xB0 + +// ATA Helpers +#define ATA_ADDRESS1(x) (x + 3) +#define ATA_ADDRESS2(x) (x + 4) +#define ATA_ADDRESS3(x) (x + 5) +#define ATA_COMMAND(x) (x + 7) + +#define kATASectorSize 4096 diff --git a/Private/Builtins/ATA/compile_flags.txt b/Private/Builtins/ATA/compile_flags.txt new file mode 100644 index 00000000..1bc51142 --- /dev/null +++ b/Private/Builtins/ATA/compile_flags.txt @@ -0,0 +1,4 @@ +-I./ +-I../ +-I../../ +-std=c++20 diff --git a/Private/Builtins/Ethernet/.gitkeep b/Private/Builtins/Ethernet/.gitkeep new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/Private/Builtins/Ethernet/.gitkeep diff --git a/Private/Builtins/Ethernet/compile_flags.txt b/Private/Builtins/Ethernet/compile_flags.txt new file mode 100644 index 00000000..545816fc --- /dev/null +++ b/Private/Builtins/Ethernet/compile_flags.txt @@ -0,0 +1,4 @@ +-I./ +-I../ +-I../../Private +-std=c++20 diff --git a/Private/Builtins/HPET/.gitkeep b/Private/Builtins/HPET/.gitkeep new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/Private/Builtins/HPET/.gitkeep diff --git a/Private/Builtins/NVME/.gitkeep b/Private/Builtins/NVME/.gitkeep new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/Private/Builtins/NVME/.gitkeep diff --git a/Private/Builtins/NVME/compile_flags.txt b/Private/Builtins/NVME/compile_flags.txt new file mode 100644 index 00000000..1bc51142 --- /dev/null +++ b/Private/Builtins/NVME/compile_flags.txt @@ -0,0 +1,4 @@ +-I./ +-I../ +-I../../ +-std=c++20 diff --git a/Private/Builtins/PS2/PS2MouseInterface.hxx b/Private/Builtins/PS2/PS2MouseInterface.hxx new file mode 100644 index 00000000..682151e9 --- /dev/null +++ b/Private/Builtins/PS2/PS2MouseInterface.hxx @@ -0,0 +1,109 @@ +/* ------------------------------------------- + + Copyright Mahrouss Logic + + File: PS2MouseInterface.hxx + Purpose: PS/2 mouse. + + Revision History: + + 03/02/24: Added file (amlel) + +------------------------------------------- */ + +#pragma once + +#include <ArchKit/ArchKit.hpp> +#include <CompilerKit/CompilerKit.hxx> +#include <NewKit/Defines.hpp> + +namespace HCore { +/// @brief PS/2 Mouse driver interface +class PS2MouseInterface final { + public: + explicit PS2MouseInterface() = default; + ~PS2MouseInterface() = default; + + HCORE_COPY_DEFAULT(PS2MouseInterface); + + public: + Void Init() noexcept { + HCore::kcout << "HCoreKrnl.exe: Enabling PS/2 mouse...\r\n"; + + this->Write(0xFF); + + HAL::Out8(0x64, 0xA8); + + this->Wait(); + + HAL::Out8(0x64, 0x20); + + this->WaitInput(); + + UInt8 dataStatus = HAL::In8(0x60); + + dataStatus |= 0b10; + + this->Wait(); + + HAL::Out8(0x60, dataStatus); + + this->Write(0xF6); + auto f6Dat = this->Read(); + + this->Write(0xF4); + auto f4Dat = this->Read(); + + HCore::kcout << "HCoreKrnl.exe: PS/2 mouse is OK: " << hex_number(f6Dat); + HCore::kcout << ", " << hex_number(f4Dat) << end_line(); + } + + private: + Bool WaitInput() noexcept { + UInt64 timeout = 100000; + + while (timeout) { + if ((HAL::In8(0x64) & 0x1)) { + HCore::kcout << "HCoreKrnl.exe: Wait: OK\r\n"; + return true; + } + + --timeout; + } // wait until we can read + + HCore::kcout << "HCoreKrnl.exe: Wait: Timeout\r\n"; + // return the ack bit. + return false; + } + + Bool Wait() noexcept { + UInt64 timeout = 100000; + + while (timeout) { + if ((HAL::In8(0x64) & 0b10) == 0) { + HCore::kcout << "HCoreKrnl.exe: Wait: OK\r\n"; + return true; + } + + --timeout; + } // wait until we can read + + HCore::kcout << "HCoreKrnl.exe: Wait: Timeout\r\n"; + // return the ack bit. + return false; + } + + Void Write(UInt8 val) { + this->Wait(); + HAL::Out8(0x64, 0xD4); + this->Wait(); + + HAL::Out8(0x60, val); + } + + UInt8 Read() { + this->WaitInput(); + return HAL::In8(0x60); + } +}; +} // namespace HCore diff --git a/Private/Builtins/README.TXT b/Private/Builtins/README.TXT new file mode 100644 index 00000000..ce39f472 --- /dev/null +++ b/Private/Builtins/README.TXT @@ -0,0 +1,16 @@ +============== +HCore Builtins +============== + +=============== +What are these? +=============== + +These are HCore builtins device drivers. + +=========== +Maintainers +=========== + +ACPIManager: Amlal EL Mahrouss +AHCI: Amlal EL Mahrouss
\ No newline at end of file diff --git a/Private/Builtins/WiFi/.gitkeep b/Private/Builtins/WiFi/.gitkeep new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/Private/Builtins/WiFi/.gitkeep diff --git a/Private/Builtins/WiFi/compile_flags.txt b/Private/Builtins/WiFi/compile_flags.txt new file mode 100644 index 00000000..1bc51142 --- /dev/null +++ b/Private/Builtins/WiFi/compile_flags.txt @@ -0,0 +1,4 @@ +-I./ +-I../ +-I../../ +-std=c++20 diff --git a/Private/Builtins/XHCI/.gitkeep b/Private/Builtins/XHCI/.gitkeep new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/Private/Builtins/XHCI/.gitkeep diff --git a/Private/Builtins/XHCI/Defines.hxx b/Private/Builtins/XHCI/Defines.hxx new file mode 100644 index 00000000..32eb8cca --- /dev/null +++ b/Private/Builtins/XHCI/Defines.hxx @@ -0,0 +1,67 @@ +/* ------------------------------------------- + + Copyright Mahrouss Logic + + File: Defines.hxx + Purpose: XHCI (and backwards) header. + + Revision History: + + 01/02/24: Added file (amlel) + 03/02/24: Update filename to Defines.hxx (amlel) + +------------------------------------------- */ + +#pragma once + +#include <NewKit/Defines.hpp> + +using namespace HCore; + +#define kUSBCommand (UInt16)0x0 +#define kUSBStatus (UInt16)0x2 +#define kUSBInterruptEnable (UInt16)0x4 +#define kUSBFrameNum (UInt16)0x6 +#define kUSBFrameListBaseAddress (UInt16)0x8 +#define kUSBFrameModifyStart (UInt16)0xC +#define kUSBPort1StatusCtrl (UInt16)0x10 +#define kUSBPort2StatusCtrl (UInt16)0x12 + +typedef struct USBCommandRegister final { + UInt8 mReserved[8]; // Reserved + UInt8 + mMaxPacket; // 0 = Max packet size 32 bits 1 = Max packet size 64 bits + UInt8 mConfigure; + UInt8 mSoftwareDebug; + UInt8 mGlobalResume; + UInt8 mGlobalSuspend; + UInt8 mHostCtrlReset; + UInt8 mRun; // 1 = Controller execute frame list entries +} USBCommandRegister; + +typedef struct USBStatusRegister final { + UInt8 mReserved[8]; // Reserved + UInt8 mHalted; // 1 = bit 0 in CMD is zero 0 = bit 0 in CMD is 1 + UInt8 mProcessError; + UInt8 mSystemError; + UInt8 mResumeDetected; + UInt8 mErrorInterrupt; + UInt8 mInterrupt; +} USBStatusRegister; + +typedef struct USBInterruptEnableRegister final { + UInt8 mReserved[4]; // Reserved + UInt8 mShortPacket; // 1=Enable interrupt 0=Disable interrupt + UInt8 mComplete; // 1=Enable interrupt 0=Disable interrupt + UInt8 mResume; // 1=Enable interrupt 0=Disable interrupt + UInt8 mTimeoutCRC; // 1=Enable interrupt 0=Disable interrupt +} USBInterruptEnableRegister; + +/* + Some terminology: + + Frame Number: Number of processed entry of the Frame List. + Frame List Base Address: + 32-bit physical adress of Frame List. Remember that first 12 bytes are + always 0. The Frame List must contain 1024 entries. +*/ diff --git a/Private/Builtins/XHCI/compile_flags.txt b/Private/Builtins/XHCI/compile_flags.txt new file mode 100644 index 00000000..1bc51142 --- /dev/null +++ b/Private/Builtins/XHCI/compile_flags.txt @@ -0,0 +1,4 @@ +-I./ +-I../ +-I../../ +-std=c++20 |