From d108de7b8ad0f92bdc9f3951e762c09c762fd174 Mon Sep 17 00:00:00 2001 From: Amlal El Mahrouss Date: Wed, 10 Jul 2024 10:14:07 +0200 Subject: MHR-36: Expose POWER64 VMS and common StackFrame across platforms. And code refactors. Signed-off-by: Amlal El Mahrouss --- Kernel/ArchKit/ArchKit.hpp | 6 +- Kernel/HALKit/64x0/HalVirtualMemory.cxx | 2 +- Kernel/HALKit/AMD64/HalACPIFactoryInterface.cxx | 2 +- Kernel/HALKit/AMD64/HalAPIC.cxx | 2 +- .../HALKit/AMD64/HalCoreMultiProcessingAMD64.cxx | 2 +- Kernel/HALKit/AMD64/HalPageAlloc.hpp | 88 ------ Kernel/HALKit/AMD64/HalPageAlloc.hxx | 88 ++++++ Kernel/HALKit/AMD64/HalProcessor.cpp | 97 ------ Kernel/HALKit/AMD64/HalProcessor.cxx | 97 ++++++ Kernel/HALKit/AMD64/Processor.hpp | 342 -------------------- Kernel/HALKit/AMD64/Processor.hxx | 343 +++++++++++++++++++++ Kernel/HALKit/ARM64/HalPageAlloc.hpp | 108 ------- Kernel/HALKit/ARM64/HalPageAlloc.hxx | 108 +++++++ Kernel/HALKit/ARM64/Processor.hxx | 2 +- Kernel/HALKit/AXP/CoreSyscallHandlerDEC.cpp | 2 +- Kernel/HALKit/POWER/HalHardware.cxx | 2 +- Kernel/HALKit/POWER/HalHart.cxx | 2 +- Kernel/HALKit/POWER/HalSerialPort.cxx | 2 +- Kernel/HALKit/POWER/HalThread.cxx | 2 +- Kernel/HALKit/POWER/HalVirtualMemory.cxx | 31 +- Kernel/HALKit/POWER/MBCI/HalMBCIHost.cxx | 2 +- Kernel/HALKit/POWER/Processor.hpp | 55 ---- Kernel/HALKit/POWER/Processor.hxx | 60 ++++ Kernel/Sources/HalPageAlloc.cxx | 4 +- Kernel/Sources/PageManager.cxx | 4 +- Kernel/Sources/Pmm.cxx | 2 +- 26 files changed, 729 insertions(+), 726 deletions(-) delete mode 100644 Kernel/HALKit/AMD64/HalPageAlloc.hpp create mode 100644 Kernel/HALKit/AMD64/HalPageAlloc.hxx delete mode 100644 Kernel/HALKit/AMD64/HalProcessor.cpp create mode 100644 Kernel/HALKit/AMD64/HalProcessor.cxx delete mode 100644 Kernel/HALKit/AMD64/Processor.hpp create mode 100644 Kernel/HALKit/AMD64/Processor.hxx delete mode 100644 Kernel/HALKit/ARM64/HalPageAlloc.hpp create mode 100644 Kernel/HALKit/ARM64/HalPageAlloc.hxx delete mode 100644 Kernel/HALKit/POWER/Processor.hpp create mode 100644 Kernel/HALKit/POWER/Processor.hxx (limited to 'Kernel') diff --git a/Kernel/ArchKit/ArchKit.hpp b/Kernel/ArchKit/ArchKit.hpp index bf9bd8e5..f01d5f21 100644 --- a/Kernel/ArchKit/ArchKit.hpp +++ b/Kernel/ArchKit/ArchKit.hpp @@ -11,11 +11,11 @@ #include #ifdef __NEWOS_AMD64__ -#include +#include #include -#include +#include #elif defined(__NEWOS_POWER64__) -#include +#include #elif defined(__NEWOS_ARM64__) #include #else diff --git a/Kernel/HALKit/64x0/HalVirtualMemory.cxx b/Kernel/HALKit/64x0/HalVirtualMemory.cxx index f62f888f..03f9afc7 100644 --- a/Kernel/HALKit/64x0/HalVirtualMemory.cxx +++ b/Kernel/HALKit/64x0/HalVirtualMemory.cxx @@ -4,7 +4,7 @@ ------------------------------------------- */ -#include +#include #include using namespace Kernel; diff --git a/Kernel/HALKit/AMD64/HalACPIFactoryInterface.cxx b/Kernel/HALKit/AMD64/HalACPIFactoryInterface.cxx index ca6a7417..3fc8ae7a 100644 --- a/Kernel/HALKit/AMD64/HalACPIFactoryInterface.cxx +++ b/Kernel/HALKit/AMD64/HalACPIFactoryInterface.cxx @@ -5,7 +5,7 @@ ------------------------------------------- */ #include -#include +#include #include #include #include diff --git a/Kernel/HALKit/AMD64/HalAPIC.cxx b/Kernel/HALKit/AMD64/HalAPIC.cxx index a148acf9..22f6583e 100644 --- a/Kernel/HALKit/AMD64/HalAPIC.cxx +++ b/Kernel/HALKit/AMD64/HalAPIC.cxx @@ -5,7 +5,7 @@ ------------------------------------------- */ #include -#include +#include namespace Kernel::HAL { diff --git a/Kernel/HALKit/AMD64/HalCoreMultiProcessingAMD64.cxx b/Kernel/HALKit/AMD64/HalCoreMultiProcessingAMD64.cxx index cb7b1eeb..86bf635c 100644 --- a/Kernel/HALKit/AMD64/HalCoreMultiProcessingAMD64.cxx +++ b/Kernel/HALKit/AMD64/HalCoreMultiProcessingAMD64.cxx @@ -5,7 +5,7 @@ ------------------------------------------- */ #include -#include +#include #include #include #include diff --git a/Kernel/HALKit/AMD64/HalPageAlloc.hpp b/Kernel/HALKit/AMD64/HalPageAlloc.hpp deleted file mode 100644 index 8887b623..00000000 --- a/Kernel/HALKit/AMD64/HalPageAlloc.hpp +++ /dev/null @@ -1,88 +0,0 @@ -/* ------------------------------------------- - - Copyright Zeta Electronics Corporation - -------------------------------------------- */ - -#pragma once - -/** --------------------------------------------------- - - * THIS FILE CONTAINS CODE FOR X86_64 PAGING. - -------------------------------------------------------- */ - -#include - -#ifndef kPTEMax -#define kPTEMax (0x200) -#endif //! kPTEMax - -#ifndef kPTEAlign -#define kPTEAlign (0x1000) -#endif //! kPTEAlign - -#ifndef kPTESize -#define kPTESize (0x1000) -#endif // !kPTESize - -EXTERN_C void hal_flush_tlb(); -EXTERN_C void hal_write_cr3(Kernel::UIntPtr pde); -EXTERN_C void hal_write_cr0(Kernel::UIntPtr bit); - -EXTERN_C Kernel::UIntPtr hal_read_cr0(); // @brief CPU control register. -EXTERN_C Kernel::UIntPtr hal_read_cr2(); // @brief Fault address. -EXTERN_C Kernel::UIntPtr hal_read_cr3(); // @brief Page table. - -namespace Kernel::HAL -{ - struct PACKED PageTable64 final - { - bool Present : 1; - bool Rw : 1; - bool User : 1; - bool Wt : 1; - bool Cache : 1; - bool Accessed : 1; - Kernel::Int32 Reserved : 6; - Kernel::UInt64 PhysicalAddress : 36; - Kernel::Int32 Reserved1 : 15; - bool ExecDisable : 1; - }; - - namespace Detail - { - enum class ControlRegisterBits - { - ProtectedModeEnable = 0, - MonitorCoProcessor = 1, - Emulation = 2, - TaskSwitched = 3, - ExtensionType = 4, - NumericError = 5, - WriteProtect = 16, - AlignementMask = 18, - NotWriteThrough = 29, - CacheDisable = 30, - PageEnable = 31, - }; - - inline UInt8 control_register_cast(ControlRegisterBits reg) - { - return static_cast(reg); - } - } // namespace Detail - - struct PageDirectory64 final - { - PageTable64 ALIGN(kPTEAlign) Pte[kPTEMax]; - }; - - VoidPtr hal_alloc_page(Boolean rw, Boolean user, SizeT size); -} // namespace Kernel::HAL - -namespace Kernel -{ - typedef HAL::PageTable64 PTE; - typedef HAL::PageDirectory64 PDE; -} // namespace Kernel diff --git a/Kernel/HALKit/AMD64/HalPageAlloc.hxx b/Kernel/HALKit/AMD64/HalPageAlloc.hxx new file mode 100644 index 00000000..8887b623 --- /dev/null +++ b/Kernel/HALKit/AMD64/HalPageAlloc.hxx @@ -0,0 +1,88 @@ +/* ------------------------------------------- + + Copyright Zeta Electronics Corporation + +------------------------------------------- */ + +#pragma once + +/** --------------------------------------------------- + + * THIS FILE CONTAINS CODE FOR X86_64 PAGING. + +------------------------------------------------------- */ + +#include + +#ifndef kPTEMax +#define kPTEMax (0x200) +#endif //! kPTEMax + +#ifndef kPTEAlign +#define kPTEAlign (0x1000) +#endif //! kPTEAlign + +#ifndef kPTESize +#define kPTESize (0x1000) +#endif // !kPTESize + +EXTERN_C void hal_flush_tlb(); +EXTERN_C void hal_write_cr3(Kernel::UIntPtr pde); +EXTERN_C void hal_write_cr0(Kernel::UIntPtr bit); + +EXTERN_C Kernel::UIntPtr hal_read_cr0(); // @brief CPU control register. +EXTERN_C Kernel::UIntPtr hal_read_cr2(); // @brief Fault address. +EXTERN_C Kernel::UIntPtr hal_read_cr3(); // @brief Page table. + +namespace Kernel::HAL +{ + struct PACKED PageTable64 final + { + bool Present : 1; + bool Rw : 1; + bool User : 1; + bool Wt : 1; + bool Cache : 1; + bool Accessed : 1; + Kernel::Int32 Reserved : 6; + Kernel::UInt64 PhysicalAddress : 36; + Kernel::Int32 Reserved1 : 15; + bool ExecDisable : 1; + }; + + namespace Detail + { + enum class ControlRegisterBits + { + ProtectedModeEnable = 0, + MonitorCoProcessor = 1, + Emulation = 2, + TaskSwitched = 3, + ExtensionType = 4, + NumericError = 5, + WriteProtect = 16, + AlignementMask = 18, + NotWriteThrough = 29, + CacheDisable = 30, + PageEnable = 31, + }; + + inline UInt8 control_register_cast(ControlRegisterBits reg) + { + return static_cast(reg); + } + } // namespace Detail + + struct PageDirectory64 final + { + PageTable64 ALIGN(kPTEAlign) Pte[kPTEMax]; + }; + + VoidPtr hal_alloc_page(Boolean rw, Boolean user, SizeT size); +} // namespace Kernel::HAL + +namespace Kernel +{ + typedef HAL::PageTable64 PTE; + typedef HAL::PageDirectory64 PDE; +} // namespace Kernel diff --git a/Kernel/HALKit/AMD64/HalProcessor.cpp b/Kernel/HALKit/AMD64/HalProcessor.cpp deleted file mode 100644 index 01f3879a..00000000 --- a/Kernel/HALKit/AMD64/HalProcessor.cpp +++ /dev/null @@ -1,97 +0,0 @@ -/* ------------------------------------------- - - Copyright Zeta Electronics Corporation - -------------------------------------------- */ - -#include - -/** - * @file Processor.cpp - * @brief This file is about processor specific functions (in/out/cli/std...) - */ - -namespace Kernel::HAL -{ - void Out8(UInt16 port, UInt8 value) - { - asm volatile("outb %%al, %1" - : - : "a"(value), "Nd"(port) - : "memory"); - } - - void Out16(UInt16 port, UInt16 value) - { - asm volatile("outw %%ax, %1" - : - : "a"(value), "Nd"(port) - : "memory"); - } - - void Out32(UInt16 port, UInt32 value) - { - asm volatile("outl %%eax, %1" - : - : "a"(value), "Nd"(port) - : "memory"); - } - - UInt8 In8(UInt16 port) - { - UInt8 value = 0UL; - asm volatile("inb %1, %%al" - : "=a"(value) - : "Nd"(port) - : "memory"); - - return value; - } - - UInt16 In16(UInt16 port) - { - UInt16 value = 0UL; - asm volatile("inw %1, %%ax" - : "=a"(value) - : "Nd"(port) - : "memory"); - - return value; - } - - UInt32 In32(UInt16 port) - { - UInt32 value = 0UL; - asm volatile("inl %1, %%eax" - : "=a"(value) - : "Nd"(port) - : "memory"); - - return value; - } - - void rt_halt() - { - asm volatile("hlt"); - } - - void rt_cli() - { - asm volatile("cli"); - } - - void rt_sti() - { - asm volatile("sti"); - } - - void rt_cld() - { - asm volatile("cld"); - } - - void rt_std() - { - asm volatile("std"); - } -} // namespace Kernel::HAL diff --git a/Kernel/HALKit/AMD64/HalProcessor.cxx b/Kernel/HALKit/AMD64/HalProcessor.cxx new file mode 100644 index 00000000..e71e7108 --- /dev/null +++ b/Kernel/HALKit/AMD64/HalProcessor.cxx @@ -0,0 +1,97 @@ +/* ------------------------------------------- + + Copyright Zeta Electronics Corporation + +------------------------------------------- */ + +#include + +/** + * @file Processor.cpp + * @brief This file is about processor specific functions (in/out/cli/std...) + */ + +namespace Kernel::HAL +{ + void Out8(UInt16 port, UInt8 value) + { + asm volatile("outb %%al, %1" + : + : "a"(value), "Nd"(port) + : "memory"); + } + + void Out16(UInt16 port, UInt16 value) + { + asm volatile("outw %%ax, %1" + : + : "a"(value), "Nd"(port) + : "memory"); + } + + void Out32(UInt16 port, UInt32 value) + { + asm volatile("outl %%eax, %1" + : + : "a"(value), "Nd"(port) + : "memory"); + } + + UInt8 In8(UInt16 port) + { + UInt8 value = 0UL; + asm volatile("inb %1, %%al" + : "=a"(value) + : "Nd"(port) + : "memory"); + + return value; + } + + UInt16 In16(UInt16 port) + { + UInt16 value = 0UL; + asm volatile("inw %1, %%ax" + : "=a"(value) + : "Nd"(port) + : "memory"); + + return value; + } + + UInt32 In32(UInt16 port) + { + UInt32 value = 0UL; + asm volatile("inl %1, %%eax" + : "=a"(value) + : "Nd"(port) + : "memory"); + + return value; + } + + void rt_halt() + { + asm volatile("hlt"); + } + + void rt_cli() + { + asm volatile("cli"); + } + + void rt_sti() + { + asm volatile("sti"); + } + + void rt_cld() + { + asm volatile("cld"); + } + + void rt_std() + { + asm volatile("std"); + } +} // namespace Kernel::HAL diff --git a/Kernel/HALKit/AMD64/Processor.hpp b/Kernel/HALKit/AMD64/Processor.hpp deleted file mode 100644 index 8ec0b6f6..00000000 --- a/Kernel/HALKit/AMD64/Processor.hpp +++ /dev/null @@ -1,342 +0,0 @@ -/* ------------------------------------------- - - Copyright Zeta Electronics Corporation - - File: Prcoessor.hxx - Purpose: AMD64 processor abstraction. - - Revision History: - - 30/01/24: Added file (amlel) - -------------------------------------------- */ - -#pragma once - -#include -#include -#include -#include -#include - -EXTERN_C -{ -#include -} - -#ifdef kCPUBackendName -#undef kCPUBackendName -#endif // ifdef kCPUBackendName - -#define kCPUBackendName "AMD64" - -#define IsActiveLow(FLG) (FLG & 2) -#define IsLevelTriggered(FLG) (FLG & 8) - -#define kInterruptGate (0x8E) -#define kTrapGate (0xEF) -#define kTaskGate (0b10001100) -#define kGdtCodeSelector (0x08) -#define cHeapStartOffset (0x10000000) - -namespace Kernel -{ - namespace Detail::AMD64 - { - struct PACKED InterruptDescriptorAMD64 final - { - UInt16 OffsetLow; // offset bits 0..15 - UInt16 Selector; // a code segment selector in GDT or LDT - UInt8 - Ist; // bits 0..2 holds Interrupt Stack Table offset, rest of bits zero. - UInt8 TypeAttributes; // gate type, dpl, and p fields - UInt16 OffsetMid; // offset bits 16..31 - UInt32 OffsetHigh; // offset bits 32..63 - UInt32 Zero; // reserved - }; - } // namespace Detail::AMD64 -} // namespace Kernel - -namespace Kernel::HAL -{ - /// @brief Virtual memory flags. - enum - { - eFlagsUser, - eFlagsRw, - eFlagsExecDisable - }; - - /// @brief Map address to PDE. - /// @param pde a valid page directory. - /// @param phys_addr a valid phyiscal address. - /// @param virt_addr a valid virtual address. - /// @param flags the flags to put on the page. - inline Int32 ke_map_address(PDE* pde, UIntPtr phys_addr, UIntPtr virt_addr, UInt32 flags) - { - UInt16 pml4_index = (virt_addr >> 39) & 0x1FF; - - if (pde && !pde->Pte[pml4_index].Present) - { - pde->Pte[pml4_index].Present = true; - - pde->Pte[pml4_index].PhysicalAddress = phys_addr; - pde->Pte[pml4_index].Rw = flags & eFlagsRw; - pde->Pte[pml4_index].User = flags & eFlagsUser; - pde->Pte[pml4_index].ExecDisable = flags & eFlagsExecDisable; - - kcout << "PTE is present now.\r"; - - return 0; - } - else - { - kcout << "PM is already present.\r"; - - kcout << "PhysicalAddress: " << hex_number(pde->Pte[pml4_index].PhysicalAddress); - kcout << "\r"; - - kcout << "User: " << (pde->Pte[pml4_index].User ? "true" : "false") << "\r"; - kcout << "RW: " << (pde->Pte[pml4_index].Rw ? "true" : "false") << "\r"; - - return 0; - } - - return 1; - } - - /// @brief Map address to PDE. - /// @param pde - /// @param phys_addr - /// @param virt_addr - /// @param flags - inline Void ke_unmap_address(PDE* pde, UIntPtr phys_addr, UIntPtr virt_addr, UInt32 flags) - { - UInt16 pml4_index = (virt_addr >> 39) & 0x1FF; - - if (pde->Pte[pml4_index].Present) - { - pde->Pte[pml4_index].Present = false; - pde->Pte[pml4_index].PhysicalAddress = 0; - pde->Pte[pml4_index].Rw = 0; - pde->Pte[pml4_index].User = 0; - pde->Pte[pml4_index].ExecDisable = 0; - } - } - - EXTERN_C UChar In8(UInt16 port); - EXTERN_C UShort In16(UInt16 port); - EXTERN_C UInt In32(UInt16 port); - - EXTERN_C void Out16(UShort port, UShort byte); - EXTERN_C void Out8(UShort port, UChar byte); - EXTERN_C void Out32(UShort port, UInt byte); - - EXTERN_C void rt_wait_400ns(); - EXTERN_C void rt_halt(); - EXTERN_C void rt_cli(); - EXTERN_C void rt_sti(); - EXTERN_C void rt_cld(); - EXTERN_C void rt_std(); - - struct PACKED Register64 final - { - UShort Limit; - UIntPtr Base; - }; - - struct PACKED RegisterGDT final - { - UShort Limit; - UIntPtr Base; - }; - - using RawRegister = UInt64; - - using InterruptId = UShort; /* For each element in the IVT */ - using InterruptTrapKind = UIntPtr(UIntPtr sp); - - typedef UIntPtr Reg; - - struct PACKED StackFrame final - { - Reg IntNum, Exception; - Reg A0, A2, BP, SP, A3, A4, A5, A6; - Reg R8, R9, R10, R11, R12, R13, R14, R15; - Reg Gs, Fs; - }; - - typedef StackFrame* StackFramePtr; - - class InterruptDescriptor final - { - public: - UShort Offset; - UShort Selector; - UChar Ist; - UChar Atrributes; - - UShort SecondOffset; - UInt ThirdOffset; - UInt Zero; - - operator bool() - { - return Offset != 0xFFFF; - } - }; - - using InterruptDescriptorArray = Array; - - class SegmentDescriptor final - { - public: - UInt16 Base; - UInt8 BaseMiddle; - UInt8 BaseHigh; - - UShort Limit; - UChar Gran; - UChar AccessByte; - }; - - /*** - * @brief Segment Boolean operations - */ - class SegmentDescriptorComparator final - { - public: - Bool IsValid(SegmentDescriptor& seg) - { - return seg.Base > seg.Limit; - } - - Bool Equals(SegmentDescriptor& seg, SegmentDescriptor& segRight) - { - return seg.Base == segRight.Base && seg.Limit == segRight.Limit; - } - }; - - using SegmentArray = Array; - - class GDTLoader final - { - public: - static Void Load(RegisterGDT& gdt); - static Void Load(Ref& gdt); - }; - - class IDTLoader final - { - public: - static Void Load(Register64& idt); - static Void Load(Ref& idt); - }; - - Void hal_system_get_cores(VoidPtr rsdPtr); - Void hal_send_start_ipi(UInt32 apicId, UInt8 vector, UInt32 targetAddress); - Void hal_send_end_ipi(UInt32 apicId, UInt8 vector, UInt32 targetAddress); - - /// @brief Do a cpuid to check if MSR exists on CPU. - /// @retval true it does exists. - /// @retval false it doesn't. - inline Bool hal_has_msr() noexcept - { - static UInt32 eax, unused, edx; // eax, edx - - __get_cpuid(1, &eax, &unused, &unused, &edx); - - // edx returns the flag for MSR (which is 1 shifted to 5.) - return edx & (1 << 5); - } - - /// @brief Get Model-specific register. - /// @param msr MSR - /// @param lo low byte - /// @param hi high byte - inline Void hal_get_msr(UInt32 msr, UInt32* lo, UInt32* hi) noexcept - { - if (!lo || !hi) - return; - - asm volatile("rdmsr" - : "=a"(*lo), "=d"(*hi) - : "c"(msr)); - } - - /// @brief Set Model-specific register. - /// @param msr MSR - /// @param lo low byte - /// @param hi high byte - inline Void hal_set_msr(UInt32 msr, UInt32 lo, UInt32 hi) noexcept - { - asm volatile("wrmsr" - : - : "a"(lo), "d"(hi), "c"(msr)); - } - - /// @brief Processor specific namespace. - namespace Detail - { - /** - @brief Global descriptor table entry, either null, code or data. - */ - - struct PACKED NewOSGDTRecord final - { - UInt16 Limit0; - UInt16 Base0; - UInt8 Base1; - UInt8 AccessByte; - UInt8 Limit1_Flags; - UInt8 Base2; - }; - - struct PACKED ALIGN(0x1000) NewOSGDT final - { - NewOSGDTRecord Null; - NewOSGDTRecord KernCode; - NewOSGDTRecord KernData; - NewOSGDTRecord UserNull; - NewOSGDTRecord UserCode; - NewOSGDTRecord UserData; - }; - } // namespace Detail - - class APICController - { - public: - explicit APICController(VoidPtr base) - : fApic(base) - { - } - - ~APICController() = default; - - NEWOS_COPY_DEFAULT(APICController); - - public: - UInt32 Read(UInt32 reg) noexcept; - Void Write(UInt32 reg, UInt32 value) noexcept; - - private: - VoidPtr fApic{nullptr}; - }; -} // namespace Kernel::HAL - -EXTERN_C Kernel::Void idt_handle_generic(Kernel::UIntPtr rsp); -EXTERN_C Kernel::Void idt_handle_gpf(Kernel::UIntPtr rsp); -EXTERN_C Kernel::Void idt_handle_math(Kernel::UIntPtr rsp); -EXTERN_C Kernel::Void idt_handle_pf(Kernel::UIntPtr rsp); - -EXTERN_C Kernel::Void hal_load_idt(Kernel::HAL::Register64 ptr); -EXTERN_C Kernel::Void hal_load_gdt(Kernel::HAL::RegisterGDT ptr); - -/// @brief Maximum size of the IDT. -#define kKernelIdtSize 0x100 -#define kKernelInterruptId 0x32 - -inline Kernel::VoidPtr kKernelVirtualStart = (Kernel::VoidPtr)cHeapStartOffset; -inline Kernel::UIntPtr kKernelVirtualSize = 0UL; - -inline Kernel::VoidPtr kKernelPhysicalStart = nullptr; diff --git a/Kernel/HALKit/AMD64/Processor.hxx b/Kernel/HALKit/AMD64/Processor.hxx new file mode 100644 index 00000000..ecdd8dd0 --- /dev/null +++ b/Kernel/HALKit/AMD64/Processor.hxx @@ -0,0 +1,343 @@ +/* ------------------------------------------- + + Copyright Zeta Electronics Corporation + + File: Prcoessor.hxx + Purpose: AMD64 processor abstraction. + + Revision History: + + 30/01/24: Added file (amlel) + +------------------------------------------- */ + +#pragma once + +#include +#include +#include +#include +#include + +EXTERN_C +{ +#include +} + +#ifdef kCPUBackendName +#undef kCPUBackendName +#endif // ifdef kCPUBackendName + +#define kCPUBackendName "AMD64" + +#define IsActiveLow(FLG) (FLG & 2) +#define IsLevelTriggered(FLG) (FLG & 8) + +#define kInterruptGate (0x8E) +#define kTrapGate (0xEF) +#define kTaskGate (0b10001100) +#define kGdtCodeSelector (0x08) +#define cHeapStartOffset (0x10000000) + +namespace Kernel +{ + namespace Detail::AMD64 + { + struct PACKED InterruptDescriptorAMD64 final + { + UInt16 OffsetLow; // offset bits 0..15 + UInt16 Selector; // a code segment selector in GDT or LDT + UInt8 + Ist; // bits 0..2 holds Interrupt Stack Table offset, rest of bits zero. + UInt8 TypeAttributes; // gate type, dpl, and p fields + UInt16 OffsetMid; // offset bits 16..31 + UInt32 OffsetHigh; // offset bits 32..63 + UInt32 Zero; // reserved + }; + } // namespace Detail::AMD64 +} // namespace Kernel + +namespace Kernel::HAL +{ + /// @brief Virtual memory flags. + enum + { + eFlagsUser, + eFlagsRw, + eFlagsExecDisable + }; + + /// @brief Map address to PDE. + /// @param pde a valid page directory. + /// @param phys_addr a valid phyiscal address. + /// @param virt_addr a valid virtual address. + /// @param flags the flags to put on the page. + inline Int32 ke_map_address(PDE* pde, UIntPtr phys_addr, UIntPtr virt_addr, UInt32 flags) + { + UInt16 pml4_index = (virt_addr >> 39) & 0x1FF; + + if (pde && !pde->Pte[pml4_index].Present) + { + pde->Pte[pml4_index].Present = true; + + pde->Pte[pml4_index].PhysicalAddress = phys_addr; + pde->Pte[pml4_index].Rw = flags & eFlagsRw; + pde->Pte[pml4_index].User = flags & eFlagsUser; + pde->Pte[pml4_index].ExecDisable = flags & eFlagsExecDisable; + + kcout << "PTE is present now.\r"; + + return 0; + } + else + { + kcout << "PM is already present.\r"; + + kcout << "PhysicalAddress: " << hex_number(pde->Pte[pml4_index].PhysicalAddress); + kcout << "\r"; + + kcout << "User: " << (pde->Pte[pml4_index].User ? "true" : "false") << "\r"; + kcout << "RW: " << (pde->Pte[pml4_index].Rw ? "true" : "false") << "\r"; + + return 0; + } + + return 1; + } + + /// @brief Map address to PDE. + /// @param pde + /// @param phys_addr + /// @param virt_addr + /// @param flags + inline Void ke_unmap_address(PDE* pde, UIntPtr phys_addr, UIntPtr virt_addr, UInt32 flags) + { + UInt16 pml4_index = (virt_addr >> 39) & 0x1FF; + + if (pde->Pte[pml4_index].Present) + { + pde->Pte[pml4_index].Present = false; + pde->Pte[pml4_index].PhysicalAddress = 0; + pde->Pte[pml4_index].Rw = 0; + pde->Pte[pml4_index].User = 0; + pde->Pte[pml4_index].ExecDisable = 0; + } + } + + EXTERN_C UChar In8(UInt16 port); + EXTERN_C UShort In16(UInt16 port); + EXTERN_C UInt In32(UInt16 port); + + EXTERN_C void Out16(UShort port, UShort byte); + EXTERN_C void Out8(UShort port, UChar byte); + EXTERN_C void Out32(UShort port, UInt byte); + + EXTERN_C void rt_wait_400ns(); + EXTERN_C void rt_halt(); + EXTERN_C void rt_cli(); + EXTERN_C void rt_sti(); + EXTERN_C void rt_cld(); + EXTERN_C void rt_std(); + + struct PACKED Register64 final + { + UShort Limit; + UIntPtr Base; + }; + + struct PACKED RegisterGDT final + { + UShort Limit; + UIntPtr Base; + }; + + using RawRegister = UInt64; + + using InterruptId = UShort; /* For each element in the IVT */ + using InterruptTrapKind = UIntPtr(UIntPtr sp); + + typedef UIntPtr Reg; + + /// @brief Stack frame (as retrieved from assembly.) + struct PACKED StackFrame final + { + Reg IntNum, Exception; + Reg A0, A2, BP, SP, A3, A4, A5, A6; + Reg R8, R9, R10, R11, R12, R13, R14, R15; + Reg Gs, Fs; + }; + + typedef StackFrame* StackFramePtr; + + class InterruptDescriptor final + { + public: + UShort Offset; + UShort Selector; + UChar Ist; + UChar Atrributes; + + UShort SecondOffset; + UInt ThirdOffset; + UInt Zero; + + operator bool() + { + return Offset != 0xFFFF; + } + }; + + using InterruptDescriptorArray = Array; + + class SegmentDescriptor final + { + public: + UInt16 Base; + UInt8 BaseMiddle; + UInt8 BaseHigh; + + UShort Limit; + UChar Gran; + UChar AccessByte; + }; + + /*** + * @brief Segment Boolean operations + */ + class SegmentDescriptorComparator final + { + public: + Bool IsValid(SegmentDescriptor& seg) + { + return seg.Base > seg.Limit; + } + + Bool Equals(SegmentDescriptor& seg, SegmentDescriptor& segRight) + { + return seg.Base == segRight.Base && seg.Limit == segRight.Limit; + } + }; + + using SegmentArray = Array; + + class GDTLoader final + { + public: + static Void Load(RegisterGDT& gdt); + static Void Load(Ref& gdt); + }; + + class IDTLoader final + { + public: + static Void Load(Register64& idt); + static Void Load(Ref& idt); + }; + + Void hal_system_get_cores(VoidPtr rsdPtr); + Void hal_send_start_ipi(UInt32 apicId, UInt8 vector, UInt32 targetAddress); + Void hal_send_end_ipi(UInt32 apicId, UInt8 vector, UInt32 targetAddress); + + /// @brief Do a cpuid to check if MSR exists on CPU. + /// @retval true it does exists. + /// @retval false it doesn't. + inline Bool hal_has_msr() noexcept + { + static UInt32 eax, unused, edx; // eax, edx + + __get_cpuid(1, &eax, &unused, &unused, &edx); + + // edx returns the flag for MSR (which is 1 shifted to 5.) + return edx & (1 << 5); + } + + /// @brief Get Model-specific register. + /// @param msr MSR + /// @param lo low byte + /// @param hi high byte + inline Void hal_get_msr(UInt32 msr, UInt32* lo, UInt32* hi) noexcept + { + if (!lo || !hi) + return; + + asm volatile("rdmsr" + : "=a"(*lo), "=d"(*hi) + : "c"(msr)); + } + + /// @brief Set Model-specific register. + /// @param msr MSR + /// @param lo low byte + /// @param hi high byte + inline Void hal_set_msr(UInt32 msr, UInt32 lo, UInt32 hi) noexcept + { + asm volatile("wrmsr" + : + : "a"(lo), "d"(hi), "c"(msr)); + } + + /// @brief Processor specific namespace. + namespace Detail + { + /** + @brief Global descriptor table entry, either null, code or data. + */ + + struct PACKED NewOSGDTRecord final + { + UInt16 Limit0; + UInt16 Base0; + UInt8 Base1; + UInt8 AccessByte; + UInt8 Limit1_Flags; + UInt8 Base2; + }; + + struct PACKED ALIGN(0x1000) NewOSGDT final + { + NewOSGDTRecord Null; + NewOSGDTRecord KernCode; + NewOSGDTRecord KernData; + NewOSGDTRecord UserNull; + NewOSGDTRecord UserCode; + NewOSGDTRecord UserData; + }; + } // namespace Detail + + class APICController + { + public: + explicit APICController(VoidPtr base) + : fApic(base) + { + } + + ~APICController() = default; + + NEWOS_COPY_DEFAULT(APICController); + + public: + UInt32 Read(UInt32 reg) noexcept; + Void Write(UInt32 reg, UInt32 value) noexcept; + + private: + VoidPtr fApic{nullptr}; + }; +} // namespace Kernel::HAL + +EXTERN_C Kernel::Void idt_handle_generic(Kernel::UIntPtr rsp); +EXTERN_C Kernel::Void idt_handle_gpf(Kernel::UIntPtr rsp); +EXTERN_C Kernel::Void idt_handle_math(Kernel::UIntPtr rsp); +EXTERN_C Kernel::Void idt_handle_pf(Kernel::UIntPtr rsp); + +EXTERN_C Kernel::Void hal_load_idt(Kernel::HAL::Register64 ptr); +EXTERN_C Kernel::Void hal_load_gdt(Kernel::HAL::RegisterGDT ptr); + +/// @brief Maximum size of the IDT. +#define kKernelIdtSize 0x100 +#define kKernelInterruptId 0x32 + +inline Kernel::VoidPtr kKernelVirtualStart = (Kernel::VoidPtr)cHeapStartOffset; +inline Kernel::UIntPtr kKernelVirtualSize = 0UL; + +inline Kernel::VoidPtr kKernelPhysicalStart = nullptr; diff --git a/Kernel/HALKit/ARM64/HalPageAlloc.hpp b/Kernel/HALKit/ARM64/HalPageAlloc.hpp deleted file mode 100644 index 8286b5cd..00000000 --- a/Kernel/HALKit/ARM64/HalPageAlloc.hpp +++ /dev/null @@ -1,108 +0,0 @@ -/* ------------------------------------------- - - Copyright Zeta Electronics Corporation - -------------------------------------------- */ - -#pragma once - -/** --------------------------------------------------- - - * THIS FILE CONTAINS CODE FOR ARMV8 PAGING. - -------------------------------------------------------- */ - -#include - -#ifndef kPTEMax -#define kPTEMax (0x200) -#endif //! kPTEMax - -#ifndef kPTEAlign -#define kPTEAlign (0x1000) -#endif //! kPTEAlign - -#ifndef kPTESize -#define kPTESize (0x1000) -#endif // !kPTESize - -//! short format address range - -#define c16KBPage 0b000 -#define c8KBPage 0b001 -#define c4KBPage 0b010 -#define c2KBPage 0b011 -#define c1KBPage 0b100 -#define c512BPage 0b101 -#define c256BPage 0b110 -#define c128BPage 0b111 - -/// Long format address range - -#define cPageMAll \ - { \ - 0b000, 0b000 \ - } -#define cPageMToMax(M) \ - { \ - M, 0b000 \ - } -#define cPageMaxToM(M) \ - { \ - 0b000, M \ - } -#define cPageMToN(M, N) \ - { \ - M, N \ - } - -namespace Kernel::HAL -{ - struct PACKED LongDescLevel3 final - { - Boolean Present : 1; - Boolean Rw : 1; - UInt16 Lpat : 9; - UInt32 Address : 27; - UInt32 Sbzp : 12; - UInt32 UPat : 11; - }; - - namespace Detail - { - enum class ControlRegisterBits - { - ProtectedModeEnable = 0, - MonitorCoProcessor = 1, - Emulation = 2, - TaskSwitched = 3, - ExtensionType = 4, - NumericError = 5, - WriteProtect = 16, - AlignementMask = 18, - NotWriteThrough = 29, - CacheDisable = 30, - PageEnable = 31, - }; - - inline UInt8 control_register_cast(ControlRegisterBits reg) - { - return static_cast(reg); - } - } // namespace Detail - - struct PageDirectory64 final - { - LongDescLevel3 ALIGN(kPTEAlign) Pte[kPTEMax]; - }; - - VoidPtr hal_alloc_page(Boolean rw, Boolean user, SizeT size); -} // namespace Kernel::HAL - -namespace Kernel -{ - typedef HAL::LongDescLevel3 PTE; - typedef HAL::PageDirectory64 PDE; -} // namespace Kernel - -EXTERN_C void hal_flush_tlb(); diff --git a/Kernel/HALKit/ARM64/HalPageAlloc.hxx b/Kernel/HALKit/ARM64/HalPageAlloc.hxx new file mode 100644 index 00000000..8286b5cd --- /dev/null +++ b/Kernel/HALKit/ARM64/HalPageAlloc.hxx @@ -0,0 +1,108 @@ +/* ------------------------------------------- + + Copyright Zeta Electronics Corporation + +------------------------------------------- */ + +#pragma once + +/** --------------------------------------------------- + + * THIS FILE CONTAINS CODE FOR ARMV8 PAGING. + +------------------------------------------------------- */ + +#include + +#ifndef kPTEMax +#define kPTEMax (0x200) +#endif //! kPTEMax + +#ifndef kPTEAlign +#define kPTEAlign (0x1000) +#endif //! kPTEAlign + +#ifndef kPTESize +#define kPTESize (0x1000) +#endif // !kPTESize + +//! short format address range + +#define c16KBPage 0b000 +#define c8KBPage 0b001 +#define c4KBPage 0b010 +#define c2KBPage 0b011 +#define c1KBPage 0b100 +#define c512BPage 0b101 +#define c256BPage 0b110 +#define c128BPage 0b111 + +/// Long format address range + +#define cPageMAll \ + { \ + 0b000, 0b000 \ + } +#define cPageMToMax(M) \ + { \ + M, 0b000 \ + } +#define cPageMaxToM(M) \ + { \ + 0b000, M \ + } +#define cPageMToN(M, N) \ + { \ + M, N \ + } + +namespace Kernel::HAL +{ + struct PACKED LongDescLevel3 final + { + Boolean Present : 1; + Boolean Rw : 1; + UInt16 Lpat : 9; + UInt32 Address : 27; + UInt32 Sbzp : 12; + UInt32 UPat : 11; + }; + + namespace Detail + { + enum class ControlRegisterBits + { + ProtectedModeEnable = 0, + MonitorCoProcessor = 1, + Emulation = 2, + TaskSwitched = 3, + ExtensionType = 4, + NumericError = 5, + WriteProtect = 16, + AlignementMask = 18, + NotWriteThrough = 29, + CacheDisable = 30, + PageEnable = 31, + }; + + inline UInt8 control_register_cast(ControlRegisterBits reg) + { + return static_cast(reg); + } + } // namespace Detail + + struct PageDirectory64 final + { + LongDescLevel3 ALIGN(kPTEAlign) Pte[kPTEMax]; + }; + + VoidPtr hal_alloc_page(Boolean rw, Boolean user, SizeT size); +} // namespace Kernel::HAL + +namespace Kernel +{ + typedef HAL::LongDescLevel3 PTE; + typedef HAL::PageDirectory64 PDE; +} // namespace Kernel + +EXTERN_C void hal_flush_tlb(); diff --git a/Kernel/HALKit/ARM64/Processor.hxx b/Kernel/HALKit/ARM64/Processor.hxx index fcffe065..c7ceae7d 100644 --- a/Kernel/HALKit/ARM64/Processor.hxx +++ b/Kernel/HALKit/ARM64/Processor.hxx @@ -53,4 +53,4 @@ inline Kernel::UIntPtr kKernelVirtualSize = 0UL; inline Kernel::VoidPtr kKernelPhysicalStart = nullptr; -#include +#include diff --git a/Kernel/HALKit/AXP/CoreSyscallHandlerDEC.cpp b/Kernel/HALKit/AXP/CoreSyscallHandlerDEC.cpp index 4469eee9..2cfe6e70 100644 --- a/Kernel/HALKit/AXP/CoreSyscallHandlerDEC.cpp +++ b/Kernel/HALKit/AXP/CoreSyscallHandlerDEC.cpp @@ -5,7 +5,7 @@ ------------------------------------------- */ #include -#include +#include /// @brief Internal call for syscall, to work with C++. /// @param stack diff --git a/Kernel/HALKit/POWER/HalHardware.cxx b/Kernel/HALKit/POWER/HalHardware.cxx index 15407eb3..f8f40ff1 100644 --- a/Kernel/HALKit/POWER/HalHardware.cxx +++ b/Kernel/HALKit/POWER/HalHardware.cxx @@ -4,7 +4,7 @@ ------------------------------------------- */ -#include +#include #include namespace Kernel diff --git a/Kernel/HALKit/POWER/HalHart.cxx b/Kernel/HALKit/POWER/HalHart.cxx index 614828cb..38babb12 100644 --- a/Kernel/HALKit/POWER/HalHart.cxx +++ b/Kernel/HALKit/POWER/HalHart.cxx @@ -4,7 +4,7 @@ ------------------------------------------- */ -#include +#include #include #include diff --git a/Kernel/HALKit/POWER/HalSerialPort.cxx b/Kernel/HALKit/POWER/HalSerialPort.cxx index abddd291..6a802a72 100644 --- a/Kernel/HALKit/POWER/HalSerialPort.cxx +++ b/Kernel/HALKit/POWER/HalSerialPort.cxx @@ -4,7 +4,7 @@ ------------------------------------------- */ -#include +#include #include using namespace Kernel; diff --git a/Kernel/HALKit/POWER/HalThread.cxx b/Kernel/HALKit/POWER/HalThread.cxx index 18d84d4f..3e0ab088 100644 --- a/Kernel/HALKit/POWER/HalThread.cxx +++ b/Kernel/HALKit/POWER/HalThread.cxx @@ -4,7 +4,7 @@ ------------------------------------------- */ -#include +#include #include EXTERN_C Kernel::HAL::StackFramePtr rt_get_current_context() diff --git a/Kernel/HALKit/POWER/HalVirtualMemory.cxx b/Kernel/HALKit/POWER/HalVirtualMemory.cxx index eb04a43d..d068a374 100644 --- a/Kernel/HALKit/POWER/HalVirtualMemory.cxx +++ b/Kernel/HALKit/POWER/HalVirtualMemory.cxx @@ -7,20 +7,14 @@ #include #include -#include +#include #include -/// @note refer to our SoC documentation. +/// @note refer to the SoC documentation. using namespace Kernel; -/// @brief Write directly to the specific TLB. -/// @param mas0 -/// @param mas1 -/// @param mas2 -/// @param mas3 -/// @param mas7 -static void hal_write_tlb(uint32_t mas0, uint32_t mas1, uint32_t mas2, uint32_t mas3, uint32_t mas7) +Void hal_write_tlb(UInt32 mas0, UInt32 mas1, UInt32 mas2, UInt32 mas3, UInt32 mas7) { mtspr(MAS0, mas0); mtspr(MAS1, mas1); @@ -31,23 +25,26 @@ static void hal_write_tlb(uint32_t mas0, uint32_t mas1, uint32_t mas2, uint32_t hal_flush_tlb(); } -void hal_set_tlb(uint8_t tlb, uint32_t epn, uint64_t rpn, uint8_t perms, uint8_t wimge, uint8_t ts, uint8_t esel, uint8_t tsize, uint8_t iprot) +Bool hal_set_tlb(UInt8 tlb, UInt32 epn, UInt64 rpn, UInt8 perms, UInt8 wimge, UInt8 ts, UInt8 esel, UInt8 tsize, UInt8 iprot) { if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1 && (tsize & 1)) { // this mmu-version does not allow odd tsize values - return; + return false; } - uint32_t mas0 = FSL_BOOKE_MAS0(tlb, esel, 0); - uint32_t mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize); - uint32_t mas2 = FSL_BOOKE_MAS2(epn, wimge); - uint32_t mas3 = FSL_BOOKE_MAS3(rpn, 0, perms); - uint32_t mas7 = FSL_BOOKE_MAS7(rpn); + + UInt32 mas0 = FSL_BOOKE_MAS0(tlb, esel, 0); + UInt32 mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize); + UInt32 mas2 = FSL_BOOKE_MAS2(epn, wimge); + UInt32 mas3 = FSL_BOOKE_MAS3(rpn, 0, perms); + UInt32 mas7 = FSL_BOOKE_MAS7(rpn); hal_write_tlb(mas0, mas1, mas2, mas3, mas7); + + return true; } -/// @brief Flush system TLB. +/// @brief Flush TLB EXTERN_C void hal_flush_tlb() { asm volatile("isync;tlbwe;msync;isync"); diff --git a/Kernel/HALKit/POWER/MBCI/HalMBCIHost.cxx b/Kernel/HALKit/POWER/MBCI/HalMBCIHost.cxx index 8a24506a..03f5a387 100644 --- a/Kernel/HALKit/POWER/MBCI/HalMBCIHost.cxx +++ b/Kernel/HALKit/POWER/MBCI/HalMBCIHost.cxx @@ -4,5 +4,5 @@ ------------------------------------------- */ -#include +#include #include diff --git a/Kernel/HALKit/POWER/Processor.hpp b/Kernel/HALKit/POWER/Processor.hpp deleted file mode 100644 index 5ff7eef3..00000000 --- a/Kernel/HALKit/POWER/Processor.hpp +++ /dev/null @@ -1,55 +0,0 @@ -/* ------------------------------------------- - - Copyright Zeta Electronics Corporation - - Purpose: POWER processor header. - -------------------------------------------- */ - -#pragma once - -#include -#include - -#define kHalPPCAlignment __attribute__((aligned(4))) - -namespace Kernel::HAL -{ - typedef UIntPtr Reg; - - struct kHalPPCAlignment StackFrame - { - Reg R0; - Reg R1; - Reg R2; - Reg R3; - Reg R4; - Reg R5; - Reg R6; - Reg R7; - Reg R8; - Reg PC; - Reg SP; - }; - - typedef StackFrame* StackFramePtr; - - inline void rt_halt() - { - while (1) - { - asm volatile("mr 0, 0"); // no oop. - } - } - - inline void rt_cli() - { - asm volatile("mr 0, 0"); // no oop - } -} // namespace Kernel::HAL - -EXTERN_C void int_handle_math(Kernel::UIntPtr sp); -EXTERN_C void int_handle_pf(Kernel::UIntPtr sp); - -/// @brief Flush system TLB. -EXTERN_C void hal_flush_tlb(); diff --git a/Kernel/HALKit/POWER/Processor.hxx b/Kernel/HALKit/POWER/Processor.hxx new file mode 100644 index 00000000..26f739d3 --- /dev/null +++ b/Kernel/HALKit/POWER/Processor.hxx @@ -0,0 +1,60 @@ +/* ------------------------------------------- + + Copyright Zeta Electronics Corporation + + Purpose: POWER processor header. + +------------------------------------------- */ + +#pragma once + +#include +#include + +#define NoOp() asm volatile("mr 0, 0") +#define kHalPPCAlignment __attribute__((aligned(4))) + +namespace Kernel::HAL +{ + typedef UIntPtr Reg; + + /// @brief Stack frame (as retrieved from assembly.) + struct PACKED StackFrame final + { + Reg IntNum, Exception; + Reg A0, A2, BP, SP, A3, A4, A5, A6; + Reg R8, R9, R10, R11, R12, R13, R14, R15; + Reg Gs, Fs; + }; + + typedef StackFrame* StackFramePtr; + + inline void rt_halt() + { + while (true) + { + NoOp(); // no oop. + } + } + + inline void rt_cli() + { + NoOp(); // no oop + } +} // namespace Kernel::HAL + +EXTERN_C Kernel::Void int_handle_math(Kernel::UIntPtr sp); +EXTERN_C Kernel::Void int_handle_pf(Kernel::UIntPtr sp); + +/// @brief Set TLB. +Kernel::Bool hal_set_tlb(Kernel::UInt8 tlb, Kernel::UInt32 epn, + Kernel::UInt64 rpn, Kernel::UInt8 perms, + Kernel::UInt8 wimge, Kernel::UInt8 ts, + Kernel::UInt8 esel, Kernel::UInt8 tsize, Kernel::UInt8 iprot); + +/// @brief Write TLB. +Kernel::Void hal_write_tlb(Kernel::UInt32 mas0, Kernel::UInt32 mas1, + Kernel::UInt32 mas2, Kernel::UInt32 mas3, Kernel::UInt32 mas7); + +/// @brief Flush TLB. +EXTERN_C Kernel::Void hal_flush_tlb(); diff --git a/Kernel/Sources/HalPageAlloc.cxx b/Kernel/Sources/HalPageAlloc.cxx index 0339745b..c3831ee1 100644 --- a/Kernel/Sources/HalPageAlloc.cxx +++ b/Kernel/Sources/HalPageAlloc.cxx @@ -7,9 +7,9 @@ #include #ifdef __NEWOS_AMD64__ -#include +#include #elif defined(__NEWOS_ARM64__) -#include +#include #endif #include diff --git a/Kernel/Sources/PageManager.cxx b/Kernel/Sources/PageManager.cxx index 35693310..451e2041 100644 --- a/Kernel/Sources/PageManager.cxx +++ b/Kernel/Sources/PageManager.cxx @@ -8,9 +8,9 @@ #include #ifdef __NEWOS_AMD64__ -#include +#include #elif defined(__NEWOS_ARM64__) -#include +#include #endif // ifdef __NEWOS_AMD64__ || defined(__NEWOS_ARM64__) //! null deref will throw (Page Zero detected, aborting app!) diff --git a/Kernel/Sources/Pmm.cxx b/Kernel/Sources/Pmm.cxx index 22813206..19e32327 100644 --- a/Kernel/Sources/Pmm.cxx +++ b/Kernel/Sources/Pmm.cxx @@ -12,7 +12,7 @@ #endif #if defined(__NEWOS_AMD64__) -#include +#include #endif namespace Kernel -- cgit v1.2.3