From 1ab61e6bb20dd39f85fca30c1d0a83db12fea9d6 Mon Sep 17 00:00:00 2001 From: Amlal El Mahrouss Date: Wed, 28 Feb 2024 17:48:25 +0100 Subject: HCoreKrnl: Fix IDT, will get the rt_handle_interrupts right, and not corrupt the registers, see below. - New register layout in Stackframe. - Thinking about a way to wrap this handler into a valid win64 call. Signed-off-by: Amlal El Mahrouss --- Private/HALKit/AMD64/HalDescriptorLoader.cpp | 29 ++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) (limited to 'Private/HALKit/AMD64/HalDescriptorLoader.cpp') diff --git a/Private/HALKit/AMD64/HalDescriptorLoader.cpp b/Private/HALKit/AMD64/HalDescriptorLoader.cpp index 53218c17..3c84f151 100644 --- a/Private/HALKit/AMD64/HalDescriptorLoader.cpp +++ b/Private/HALKit/AMD64/HalDescriptorLoader.cpp @@ -10,9 +10,9 @@ #include namespace HCore::HAL { -STATIC Register64 kRegGdt; +STATIC RegisterGDT kRegGdt; -void GDTLoader::Load(Register64 &gdt) { +void GDTLoader::Load(RegisterGDT &gdt) { kRegGdt.Base = gdt.Base; kRegGdt.Limit = gdt.Limit; @@ -21,6 +21,9 @@ void GDTLoader::Load(Register64 &gdt) { STATIC HAL::Register64 kRegIdt; +STATIC ::HCore::Detail::AMD64::InterruptDescriptorAMD64 + kInterruptVectorTable[kKernelIdtSize]; + void IDTLoader::Load(Register64 &idt) { UInt8 a1, a2; @@ -48,32 +51,30 @@ void IDTLoader::Load(Register64 &idt) { HAL::rt_wait_400ns(); HAL::Out8(0xA1, a2); - volatile ::HCore::UIntPtr *baseIdt = (::HCore::UIntPtr *)idt.Base; + volatile ::HCore::UIntPtr **baseIdt = (volatile ::HCore::UIntPtr **)idt.Base; MUST_PASS(baseIdt[0]); - ::HCore::Detail::AMD64::InterruptDescriptorAMD64 *kInterruptVectorTable = - new ::HCore::Detail::AMD64::InterruptDescriptorAMD64[kKernelIdtSize]; - - for (auto i = 0; i < kKernelIdtSize; i++) { + for (UInt16 i = 0; i < 32; i++) { kInterruptVectorTable[i].Selector = kGdtCodeSelector; kInterruptVectorTable[i].Ist = 0x0; kInterruptVectorTable[i].TypeAttributes = kInterruptGate; - kInterruptVectorTable[i].OffsetLow = (baseIdt[i] & 0xFF); - kInterruptVectorTable[i].OffsetMid = ((baseIdt[i] & 0xFFFF) >> 16); - kInterruptVectorTable[i].OffsetHigh = ((baseIdt[i] & 0xFFFFFFFF) >> 32); + kInterruptVectorTable[i].OffsetLow = ((UIntPtr)baseIdt[i] & 0xFFFF); + kInterruptVectorTable[i].OffsetMid = (((UIntPtr)baseIdt[i] >> 16) & 0xFFFF); + kInterruptVectorTable[i].OffsetHigh = + (((UIntPtr)baseIdt[i] >> 32) & 0xFFFFFFFF); kInterruptVectorTable[i].Zero = 0x0; } - kRegIdt.Base = (UIntPtr)&kInterruptVectorTable[0]; + kRegIdt.Base = (UIntPtr)kInterruptVectorTable; kRegIdt.Limit = sizeof(::HCore::Detail::AMD64::InterruptDescriptorAMD64) * - kKernelIdtSize - - 1; + kKernelIdtSize - + 1; rt_load_idt(kRegIdt); } -void GDTLoader::Load(Ref &gdt) { GDTLoader::Load(gdt.Leak()); } +void GDTLoader::Load(Ref &gdt) { GDTLoader::Load(gdt.Leak()); } void IDTLoader::Load(Ref &idt) { IDTLoader::Load(idt.Leak()); } } // namespace HCore::HAL -- cgit v1.2.3