From f95d8bf159d10b5a9521dcaa0bc37aa0e9dfc02b Mon Sep 17 00:00:00 2001 From: Amlal El Mahrouss Date: Sun, 5 May 2024 21:10:18 +0200 Subject: MHR-23: Add run_format.sh, kernel patches. Signed-off-by: Amlal El Mahrouss --- Private/KernelKit/PCI/Database.hpp | 51 ++++++++------- Private/KernelKit/PCI/Device.hpp | 130 ++++++++++++++++++------------------- Private/KernelKit/PCI/Dma.hpp | 124 ++++++++++++++++++----------------- Private/KernelKit/PCI/IO.hpp | 54 ++++++++------- Private/KernelKit/PCI/Iterator.hpp | 34 +++++----- Private/KernelKit/PCI/PCI.hpp | 85 ++++++++++++------------ 6 files changed, 251 insertions(+), 227 deletions(-) (limited to 'Private/KernelKit/PCI') diff --git a/Private/KernelKit/PCI/Database.hpp b/Private/KernelKit/PCI/Database.hpp index b79f7b57..cf8b737f 100644 --- a/Private/KernelKit/PCI/Database.hpp +++ b/Private/KernelKit/PCI/Database.hpp @@ -8,28 +8,31 @@ #include #include -namespace NewOS { - namespace Types { - // https://wiki.osdev.org/PCI - enum class PciDeviceKind : UChar { - MassStorageController = 0x1, - NetworkController = 0x2, - DisplayController = 0x3, - MultimediaController = 0x4, - MemoryController = 0x5, - Bridge = 0x6, - CommunicationController = 0x7, - GenericSystemPeripheral = 0x8, - InputDeviceController = 0x9, - DockingStation = 0xa, - Processor = 0xb, - SerialBusController = 0xc, - WirelessController = 0xd, - IntelligentController = 0xe, - SatelliteCommunicationsController = 0xf, - CoProcessor = 0x40, - Unassgined = 0xf, - Invalid = Unassgined, - }; - } // namespace Types +namespace NewOS +{ + namespace Types + { + // https://wiki.osdev.org/PCI + enum class PciDeviceKind : UChar + { + MassStorageController = 0x1, + NetworkController = 0x2, + DisplayController = 0x3, + MultimediaController = 0x4, + MemoryController = 0x5, + Bridge = 0x6, + CommunicationController = 0x7, + GenericSystemPeripheral = 0x8, + InputDeviceController = 0x9, + DockingStation = 0xa, + Processor = 0xb, + SerialBusController = 0xc, + WirelessController = 0xd, + IntelligentController = 0xe, + SatelliteCommunicationsController = 0xf, + CoProcessor = 0x40, + Unassgined = 0xf, + Invalid = Unassgined, + }; + } // namespace Types } // namespace NewOS diff --git a/Private/KernelKit/PCI/Device.hpp b/Private/KernelKit/PCI/Device.hpp index ea11e327..e34a12b0 100644 --- a/Private/KernelKit/PCI/Device.hpp +++ b/Private/KernelKit/PCI/Device.hpp @@ -9,73 +9,71 @@ namespace NewOS::PCI { - enum class PciConfigKind : UShort - { - ConfigAddress = 0xCF8, - ConfigData = 0xCFC, - Invalid = 0xFFF - }; - - class Device final - { - public: - Device() = default; - - public: - explicit Device(UShort bus, UShort device, UShort function, UShort bar); - - Device &operator=(const Device &) = default; - - Device(const Device &) = default; - - ~Device(); - - public: - UInt Read(UInt bar, Size szData); - void Write(UInt bar, UIntPtr data, Size szData); - - public: - operator bool(); - - public: - template - UInt Read(UInt bar) - { - static_assert(sizeof(T) <= 4, "64-bit PCI addressing is unsupported"); - return Read(bar, sizeof(T)); - } - - template - void Write(UInt bar, UIntPtr data) - { - static_assert(sizeof(T) <= 4, "64-bit PCI addressing is unsupported"); - Write(bar, data, sizeof(T)); - } - - public: - UShort DeviceId(); - UShort VendorId(); - UShort InterfaceId(); - UChar Class(); - UChar Subclass(); - UChar ProgIf(); - UChar HeaderType(); - - public: - void EnableMmio(); - void BecomeBusMaster(); // for PCI-DMA, PC-DMA does not need that. - - UShort Vendor(); - - private: - UShort fBus; - UShort fDevice; - UShort fFunction; - UShort fBar; - - }; + enum class PciConfigKind : UShort + { + ConfigAddress = 0xCF8, + ConfigData = 0xCFC, + Invalid = 0xFFF + }; + + class Device final + { + public: + Device() = default; + + public: + explicit Device(UShort bus, UShort device, UShort function, UShort bar); + + Device& operator=(const Device&) = default; + + Device(const Device&) = default; + + ~Device(); + + public: + UInt Read(UInt bar, Size szData); + void Write(UInt bar, UIntPtr data, Size szData); + + public: + operator bool(); + + public: + template + UInt Read(UInt bar) + { + static_assert(sizeof(T) <= 4, "64-bit PCI addressing is unsupported"); + return Read(bar, sizeof(T)); + } + + template + void Write(UInt bar, UIntPtr data) + { + static_assert(sizeof(T) <= 4, "64-bit PCI addressing is unsupported"); + Write(bar, data, sizeof(T)); + } + + public: + UShort DeviceId(); + UShort VendorId(); + UShort InterfaceId(); + UChar Class(); + UChar Subclass(); + UChar ProgIf(); + UChar HeaderType(); + + public: + void EnableMmio(); + void BecomeBusMaster(); // for PCI-DMA, PC-DMA does not need that. + + UShort Vendor(); + + private: + UShort fBus; + UShort fDevice; + UShort fFunction; + UShort fBar; + }; } // namespace NewOS::PCI - EXTERN_C void NewOSPCISetCfgTarget(NewOS::UInt bar); EXTERN_C NewOS::UInt NewOSPCIReadRaw(NewOS::UInt bar); diff --git a/Private/KernelKit/PCI/Dma.hpp b/Private/KernelKit/PCI/Dma.hpp index 392aeee3..bdfc52cf 100644 --- a/Private/KernelKit/PCI/Dma.hpp +++ b/Private/KernelKit/PCI/Dma.hpp @@ -12,64 +12,70 @@ #include #include -namespace NewOS { -enum class DmaKind { - PCI, // Bus mastering is required to be turned on. Basiaclly a request - // control system. 64-Bit access depends on the PAE bit and the device - // (if Double Address Cycle is available) - ISA, // Four DMA channels 0-3; 8 bit transfers and only a megabyte of RAM. - Invalid, -}; - -class DMAWrapper final { - public: - explicit DMAWrapper() = delete; - - public: - explicit DMAWrapper(nullPtr) = delete; - explicit DMAWrapper(voidPtr Ptr, DmaKind Kind = DmaKind::PCI) - : fAddress(Ptr), fKind(Kind) {} - - public: - DMAWrapper &operator=(voidPtr Ptr); - - public: - DMAWrapper &operator=(const DMAWrapper &) = default; - DMAWrapper(const DMAWrapper &) = default; - - public: - ~DMAWrapper() = default; - - template - T *operator->(); - - template - T *Get(const UIntPtr off = 0); - - public: - operator bool(); - bool operator!(); - - public: - bool Write(const UIntPtr &bit, const UIntPtr &offset); - UIntPtr Read(const UIntPtr &offset); - Boolean Check(UIntPtr offset) const; - - public: - UIntPtr operator[](const UIntPtr &offset); - - private: - voidPtr fAddress{nullptr}; - DmaKind fKind{DmaKind::Invalid}; - - private: - friend class DMAFactory; -}; - -class DMAFactory final { - public: - static OwnPtr> Construct(OwnPtr &dma); -}; -} // namespace NewOS +namespace NewOS +{ + enum class DmaKind + { + PCI, // Bus mastering is required to be turned on. Basiaclly a request + // control system. 64-Bit access depends on the PAE bit and the device + // (if Double Address Cycle is available) + ISA, // Four DMA channels 0-3; 8 bit transfers and only a megabyte of RAM. + Invalid, + }; + + class DMAWrapper final + { + public: + explicit DMAWrapper() = delete; + + public: + explicit DMAWrapper(nullPtr) = delete; + explicit DMAWrapper(voidPtr Ptr, DmaKind Kind = DmaKind::PCI) + : fAddress(Ptr), fKind(Kind) + { + } + + public: + DMAWrapper& operator=(voidPtr Ptr); + + public: + DMAWrapper& operator=(const DMAWrapper&) = default; + DMAWrapper(const DMAWrapper&) = default; + + public: + ~DMAWrapper() = default; + + template + T* operator->(); + + template + T* Get(const UIntPtr off = 0); + + public: + operator bool(); + bool operator!(); + + public: + bool Write(const UIntPtr& bit, const UIntPtr& offset); + UIntPtr Read(const UIntPtr& offset); + Boolean Check(UIntPtr offset) const; + + public: + UIntPtr operator[](const UIntPtr& offset); + + private: + voidPtr fAddress{nullptr}; + DmaKind fKind{DmaKind::Invalid}; + + private: + friend class DMAFactory; + }; + + class DMAFactory final + { + public: + static OwnPtr> Construct(OwnPtr& dma); + }; +} // namespace NewOS #include diff --git a/Private/KernelKit/PCI/IO.hpp b/Private/KernelKit/PCI/IO.hpp index a0ee51dc..b76214bf 100644 --- a/Private/KernelKit/PCI/IO.hpp +++ b/Private/KernelKit/PCI/IO.hpp @@ -11,39 +11,49 @@ #include #include -namespace NewOS { -template -class IOArray final { - public: - IOArray() = delete; +namespace NewOS +{ + template + class IOArray final + { + public: + IOArray() = delete; - IOArray(nullPtr) = delete; + IOArray(nullPtr) = delete; - explicit IOArray(Array &ports) : fPorts(ports) {} - ~IOArray() {} + explicit IOArray(Array& ports) + : fPorts(ports) + { + } + ~IOArray() + { + } - IOArray &operator=(const IOArray &) = default; + IOArray& operator=(const IOArray&) = default; - IOArray(const IOArray &) = default; + IOArray(const IOArray&) = default; - operator bool() { return !fPorts.Empty(); } + operator bool() + { + return !fPorts.Empty(); + } - public: - template - T In(SizeT index); + public: + template + T In(SizeT index); - template - void Out(SizeT index, T value); + template + void Out(SizeT index, T value); - private: - Array fPorts; -}; + private: + Array fPorts; + }; -using IOArray16 = IOArray<16>; -} // namespace NewOS + using IOArray16 = IOArray<16>; +} // namespace NewOS #ifdef __x86_64__ #include #else #error Please provide platform specific code for the I/O -#endif // ifdef __x86_64__ +#endif // ifdef __x86_64__ diff --git a/Private/KernelKit/PCI/Iterator.hpp b/Private/KernelKit/PCI/Iterator.hpp index b81aae74..278711a7 100644 --- a/Private/KernelKit/PCI/Iterator.hpp +++ b/Private/KernelKit/PCI/Iterator.hpp @@ -7,30 +7,32 @@ #include #include -#define NEWOS_BUS_COUNT (256) -#define NEWOS_DEVICE_COUNT (33) +#define NEWOS_BUS_COUNT (256) +#define NEWOS_DEVICE_COUNT (33) #define NEWOS_FUNCTION_COUNT (8) -namespace NewOS::PCI { - class Iterator final { - public: - Iterator() = delete; +namespace NewOS::PCI +{ + class Iterator final + { + public: + Iterator() = delete; - public: - explicit Iterator(const Types::PciDeviceKind &deviceType); + public: + explicit Iterator(const Types::PciDeviceKind& deviceType); - Iterator &operator=(const Iterator &) = default; + Iterator& operator=(const Iterator&) = default; - Iterator(const Iterator &) = default; + Iterator(const Iterator&) = default; - ~Iterator(); + ~Iterator(); - public: - Ref operator[](const Size &sz); + public: + Ref operator[](const Size& sz); - private: - Array fDevices; - }; + private: + Array fDevices; + }; } // namespace NewOS::PCI #endif // __PCI_ITERATOR_HPP__ diff --git a/Private/KernelKit/PCI/PCI.hpp b/Private/KernelKit/PCI/PCI.hpp index 65e199ad..53f9392f 100644 --- a/Private/KernelKit/PCI/PCI.hpp +++ b/Private/KernelKit/PCI/PCI.hpp @@ -8,46 +8,51 @@ #include #define PCI_CONFIG_ADDRESS (0xCF8) -#define PCI_CONFIG_DATA (0xCFC) +#define PCI_CONFIG_DATA (0xCFC) #define PCI_DEVICE_COUNT (32) -#define PCI_FUNC_COUNT (8) -#define PCI_BUS_COUNT (255) - -namespace NewOS::PCI { -// model - struct DeviceHeader { - UInt16 VendorId; - UInt16 DeviceId; - UInt8 Command; - UInt8 Status; - UInt8 RevisionId; - UInt8 ProgIf; - UInt8 SubClass; - UInt8 Class; - UInt8 CacheLineSz; - UInt8 LatencyTimer; - UInt8 HeaderType; - UInt8 Bist; - UInt8 Bus; - UInt8 Device; - UInt8 Function; - }; - - namespace Detail { - class BAR { - public: - UIntPtr BAR; - SizeT Size; - }; - } // namespace Detail - - class BAR { - public: - Detail::BAR BAR1; - Detail::BAR BAR2; - Detail::BAR BAR3; - Detail::BAR BAR4; - Detail::BAR BAR5; - }; +#define PCI_FUNC_COUNT (8) +#define PCI_BUS_COUNT (255) + +namespace NewOS::PCI +{ + // model + struct DeviceHeader + { + UInt16 VendorId; + UInt16 DeviceId; + UInt8 Command; + UInt8 Status; + UInt8 RevisionId; + UInt8 ProgIf; + UInt8 SubClass; + UInt8 Class; + UInt8 CacheLineSz; + UInt8 LatencyTimer; + UInt8 HeaderType; + UInt8 Bist; + UInt8 Bus; + UInt8 Device; + UInt8 Function; + }; + + namespace Detail + { + class BAR + { + public: + UIntPtr BAR; + SizeT Size; + }; + } // namespace Detail + + class BAR + { + public: + Detail::BAR BAR1; + Detail::BAR BAR2; + Detail::BAR BAR3; + Detail::BAR BAR4; + Detail::BAR BAR5; + }; } // namespace NewOS::PCI -- cgit v1.2.3