From 3e607e871b1b20e14527845a511ae2a6739fcaac Mon Sep 17 00:00:00 2001 From: Amlal El Mahrouss Date: Sat, 9 Mar 2024 08:37:29 +0100 Subject: See below. - HCoreKrnl: - Improve interrupt handler for AMD64 targets. - Wrapped AHCI and PE types into a namespace. - Replace L0 with the label MainLoop. - Reworked C++Kit and NetBoot modules. - Put INewFSIterator constructor as explicit. Signed-off-by: Amlal El Mahrouss --- Private/Drivers/AHCI/Defines.hxx | 303 +++++++++++----------- Private/FSKit/NewFSIndexer.hxx | 4 +- Private/HALKit/AMD64/HalDescriptorLoader.cpp | 12 +- Private/HALKit/AMD64/HalInterruptHandlerAMD64.cxx | 29 ++- Private/HALKit/AMD64/HalNewBoot.asm | 2 +- Private/HALKit/AMD64/Processor.hpp | 4 +- Private/KernelKit/PE.hpp | 144 +++++----- Private/NewBoot/CxxRuntime/UnwindCxxKit.cxx | 29 +++ Private/NewBoot/CxxRuntime/unwind.cxx | 8 - Private/NewBoot/NetBoot/EfiModule.cxx | 3 +- 10 files changed, 283 insertions(+), 255 deletions(-) create mode 100644 Private/NewBoot/CxxRuntime/UnwindCxxKit.cxx delete mode 100644 Private/NewBoot/CxxRuntime/unwind.cxx (limited to 'Private') diff --git a/Private/Drivers/AHCI/Defines.hxx b/Private/Drivers/AHCI/Defines.hxx index 7b9ed28a..00510c3e 100644 --- a/Private/Drivers/AHCI/Defines.hxx +++ b/Private/Drivers/AHCI/Defines.hxx @@ -15,8 +15,6 @@ #include -using namespace HCore; - // Forward declarations of structs. struct HbaPort; @@ -47,168 +45,168 @@ typedef enum { typedef struct FisRegH2D final { // DWORD 0 - UInt8 fisType; // FIS_TYPE_REG_H2D + HCore::UInt8 fisType; // FIS_TYPE_REG_H2D - UInt8 portMul : 4; // Port multiplier - UInt8 reserved0 : 3; // Reserved - UInt8 cmdOrCtrl : 1; // 1: Command, 0: Control + HCore::UInt8 portMul : 4; // Port multiplier + HCore::UInt8 reserved0 : 3; // Reserved + HCore::UInt8 cmdOrCtrl : 1; // 1: Command, 0: Control - UInt8 command; // Command register - UInt8 featurel; // Feature register, 7:0 + HCore::UInt8 command; // Command register + HCore::UInt8 featurel; // Feature register, 7:0 // DWORD 1 - UInt8 lba0; // LBA low register, 7:0 - UInt8 lba1; // LBA mid register, 15:8 - UInt8 lba2; // LBA high register, 23:16 - UInt8 device; // Device register + HCore::UInt8 lba0; // LBA low register, 7:0 + HCore::UInt8 lba1; // LBA mid register, 15:8 + HCore::UInt8 lba2; // LBA high register, 23:16 + HCore::UInt8 device; // Device register // DWORD 2 - UInt8 lba3; // LBA register, 31:24 - UInt8 lba4; // LBA register, 39:32 - UInt8 lba5; // LBA register, 47:40 - UInt8 featureHigh; // Feature register, 15:8 + HCore::UInt8 lba3; // LBA register, 31:24 + HCore::UInt8 lba4; // LBA register, 39:32 + HCore::UInt8 lba5; // LBA register, 47:40 + HCore::UInt8 featureHigh; // Feature register, 15:8 // DWORD 3 - UInt8 countLow; // Count register, 7:0 - UInt8 countHigh; // Count register, 15:8 - UInt8 icc; // Isochronous command completion - UInt8 control; // Control register + HCore::UInt8 countLow; // Count register, 7:0 + HCore::UInt8 countHigh; // Count register, 15:8 + HCore::UInt8 icc; // Isochronous command completion + HCore::UInt8 control; // Control register // DWORD 4 - UInt8 reserved1[4]; // Reserved + HCore::UInt8 reserved1[4]; // Reserved } FisRegH2D; typedef struct FisRegD2H final { // DWORD 0 - UInt8 fisType; // FIS_TYPE_REG_D2H + HCore::UInt8 fisType; // FIS_TYPE_REG_D2H - UInt8 portMul : 4; // Port multiplier - UInt8 reserved0 : 2; // Reserved - UInt8 interruptBit : 1; // Interrupt bit - UInt8 reserved1 : 1; // Reserved + HCore::UInt8 portMul : 4; // Port multiplier + HCore::UInt8 reserved0 : 2; // Reserved + HCore::UInt8 interruptBit : 1; // Interrupt bit + HCore::UInt8 reserved1 : 1; // Reserved - UInt8 status; // Status register - UInt8 error; // Error register + HCore::UInt8 status; // Status register + HCore::UInt8 error; // Error register // DWORD 1 - UInt8 lba0; // LBA low register, 7:0 - UInt8 lba1; // LBA mid register, 15:8 - UInt8 lba2; // LBA high register, 23:16 - UInt8 device; // Device register + HCore::UInt8 lba0; // LBA low register, 7:0 + HCore::UInt8 lba1; // LBA mid register, 15:8 + HCore::UInt8 lba2; // LBA high register, 23:16 + HCore::UInt8 device; // Device register // DWORD 2 - UInt8 lba3; // LBA register, 31:24 - UInt8 lba4; // LBA register, 39:32 - UInt8 lba5; // LBA register, 47:40 - UInt8 rsv2; // Reserved + HCore::UInt8 lba3; // LBA register, 31:24 + HCore::UInt8 lba4; // LBA register, 39:32 + HCore::UInt8 lba5; // LBA register, 47:40 + HCore::UInt8 rsv2; // Reserved // DWORD 3 - UInt8 countLow; // Count register, 7:0 - UInt8 countHigh; // Count register, 15:8 - UInt8 rsv3[2]; // Reserved + HCore::UInt8 countLow; // Count register, 7:0 + HCore::UInt8 countHigh; // Count register, 15:8 + HCore::UInt8 rsv3[2]; // Reserved // DWORD 4 - UInt8 rsv4[4]; // Reserved + HCore::UInt8 rsv4[4]; // Reserved } FisRegD2H; typedef struct FisData final { // DWORD 0 - UInt8 fisType; // FIS_TYPE_DATA + HCore::UInt8 fisType; // FIS_TYPE_DATA - UInt8 portMul : 4; // Port multiplier - UInt8 reserved0 : 4; // Reserved + HCore::UInt8 portMul : 4; // Port multiplier + HCore::UInt8 reserved0 : 4; // Reserved - UInt8 reserved1[2]; // Reserved + HCore::UInt8 reserved1[2]; // Reserved // DWORD 1 ~ N - UInt32 data[1]; // Payload + HCore::UInt32 data[1]; // Payload } FisData; typedef struct FisPioSetup final { // DWORD 0 - UInt8 fisType; // FIS_TYPE_PIO_SETUP + HCore::UInt8 fisType; // FIS_TYPE_PIO_SETUP - UInt8 portMul : 4; // Port multiplier - UInt8 reserved0 : 1; // Reserved - UInt8 d : 1; // Data transfer direction, 1 - device to host - UInt8 interruptBit : 1; // Interrupt bit - UInt8 reserved1 : 1; + HCore::UInt8 portMul : 4; // Port multiplier + HCore::UInt8 reserved0 : 1; // Reserved + HCore::UInt8 d : 1; // Data transfer direction, 1 - device to host + HCore::UInt8 interruptBit : 1; // Interrupt bit + HCore::UInt8 reserved1 : 1; - UInt8 status; // Status register - UInt8 error; // Error register + HCore::UInt8 status; // Status register + HCore::UInt8 error; // Error register // DWORD 1 - UInt8 lba0; // LBA low register, 7:0 - UInt8 lba1; // LBA mid register, 15:8 - UInt8 lba2; // LBA high register, 23:16 - UInt8 device; // Device register + HCore::UInt8 lba0; // LBA low register, 7:0 + HCore::UInt8 lba1; // LBA mid register, 15:8 + HCore::UInt8 lba2; // LBA high register, 23:16 + HCore::UInt8 device; // Device register // DWORD 2 - UInt8 lba3; // LBA register, 31:24 - UInt8 lba4; // LBA register, 39:32 - UInt8 lba5; // LBA register, 47:40 - UInt8 rsv2; // Reserved + HCore::UInt8 lba3; // LBA register, 31:24 + HCore::UInt8 lba4; // LBA register, 39:32 + HCore::UInt8 lba5; // LBA register, 47:40 + HCore::UInt8 rsv2; // Reserved // DWORD 3 - UInt8 countLow; // Count register, 7:0 - UInt8 countHigh; // Count register, 15:8 - UInt8 rsv3; // Reserved - UInt8 eStatus; // New value of status register + HCore::UInt8 countLow; // Count register, 7:0 + HCore::UInt8 countHigh; // Count register, 15:8 + HCore::UInt8 rsv3; // Reserved + HCore::UInt8 eStatus; // New value of status register // DWORD 4 - UInt16 tc; // Transfer count - UInt8 rsv4[2]; // Reserved + HCore::UInt16 tc; // Transfer count + HCore::UInt8 rsv4[2]; // Reserved } FisPioSetup; typedef struct FisDmaSetup final { // DWORD 0 - UInt8 fisType; // FIS_TYPE_DMA_SETUP + HCore::UInt8 fisType; // FIS_TYPE_DMA_SETUP - UInt8 portMul : 4; // Port multiplier - UInt8 reserved0 : 1; // Reserved - UInt8 dtd : 1; // Data transfer direction, 1 - device to host - UInt8 interruptBit : 1; // Interrupt bit - UInt8 + HCore::UInt8 portMul : 4; // Port multiplier + HCore::UInt8 reserved0 : 1; // Reserved + HCore::UInt8 dtd : 1; // Data transfer direction, 1 - device to host + HCore::UInt8 interruptBit : 1; // Interrupt bit + HCore::UInt8 autoEnable : 1; // Auto-activate. Specifies if DMA Activate FIS is needed - UInt8 reserved1[2]; // Reserved + HCore::UInt8 reserved1[2]; // Reserved // DWORD 1&2 - UInt64 dmaBufferId; // DMA Buffer Identifier. Used to Identify DMA buffer in + HCore::UInt64 dmaBufferId; // DMA Buffer Identifier. Used to Identify DMA buffer in // host memory. SATA Spec says host specific and not in // Spec. Trying AHCI spec might work. // DWORD 3 - UInt32 rsvd; // More reserved + HCore::UInt32 rsvd; // More reserved // DWORD 4 - UInt32 dmabufOffset; // Byte offset into buffer. First 2 bits must be 0 + HCore::UInt32 dmabufOffset; // Byte offset into buffer. First 2 bits must be 0 // DWORD 5 - UInt32 transferCount; // Number of bytes to transfer. Bit 0 must be 0 + HCore::UInt32 transferCount; // Number of bytes to transfer. Bit 0 must be 0 // DWORD 6 - UInt32 reserved3; // Reserved + HCore::UInt32 reserved3; // Reserved } FisDmaSetup; typedef struct FisDevBits final { // DWORD 0 - UInt8 fisType; // FIS_TYPE_DMA_SETUP (A1h) + HCore::UInt8 fisType; // FIS_TYPE_DMA_SETUP (A1h) - UInt8 reserved0 : 5; // Reserved - UInt8 r0 : 1; - UInt8 interruptBit : 1; - UInt8 n : 1; + HCore::UInt8 reserved0 : 5; // Reserved + HCore::UInt8 r0 : 1; + HCore::UInt8 interruptBit : 1; + HCore::UInt8 n : 1; - UInt8 statusLow : 3; - UInt8 r1 : 1; - UInt8 statusHigh : 3; + HCore::UInt8 statusLow : 3; + HCore::UInt8 r1 : 1; + HCore::UInt8 statusHigh : 3; - UInt8 r2 : 1; - UInt8 error; + HCore::UInt8 r2 : 1; + HCore::UInt8 error; // DWORD 1 - UInt32 act; + HCore::UInt32 act; } FisDevBits; /// \brief Enable AHCI device bit in GHC register. @@ -217,103 +215,102 @@ typedef struct FisDevBits final { #endif //! ifndef kAhciGHC_AE typedef struct HbaPort final { - UInt32 clb; // 0x00, command list base address, 1K-byte aligned - UInt32 clbu; // 0x04, command list base address upper 32 bits - UInt32 fb; // 0x08, FIS base address, 256-byte aligned - UInt32 fbu; // 0x0C, FIS base address upper 32 bits - UInt32 is; // 0x10, interrupt status - UInt32 ie; // 0x14, interrupt enable - UInt32 cmd; // 0x18, command and status - UInt32 reserved0; // 0x1C, Reserved - UInt32 tfd; // 0x20, task file data - UInt32 sig; // 0x24, signature - UInt32 ssts; // 0x28, SATA status (SCR0:SStatus) - UInt32 sctl; // 0x2C, SATA control (SCR2:SControl) - UInt32 serr; // 0x30, SATA error (SCR1:SError) - UInt32 sact; // 0x34, SATA active (SCR3:SActive) - UInt32 ci; // 0x38, command issue - UInt32 sntf; // 0x3C, SATA notification (SCR4:SNotification) - UInt32 fbs; // 0x40, FIS-based switch control - UInt32 reserved1[11]; // 0x44 ~ 0x6F, Reserved - UInt32 vendor[4]; // 0x70 ~ 0x7F, vendor specific + HCore::UInt32 clb; // 0x00, command list base address, 1K-byte aligned + HCore::UInt32 clbu; // 0x04, command list base address upper 32 bits + HCore::UInt32 fb; // 0x08, FIS base address, 256-byte aligned + HCore::UInt32 fbu; // 0x0C, FIS base address upper 32 bits + HCore::UInt32 is; // 0x10, interrupt status + HCore::UInt32 ie; // 0x14, interrupt enable + HCore::UInt32 cmd; // 0x18, command and status + HCore::UInt32 reserved0; // 0x1C, Reserved + HCore::UInt32 tfd; // 0x20, task file data + HCore::UInt32 sig; // 0x24, signature + HCore::UInt32 ssts; // 0x28, SATA status (SCR0:SStatus) + HCore::UInt32 sctl; // 0x2C, SATA control (SCR2:SControl) + HCore::UInt32 serr; // 0x30, SATA error (SCR1:SError) + HCore::UInt32 sact; // 0x34, SATA active (SCR3:SActive) + HCore::UInt32 ci; // 0x38, command issue + HCore::UInt32 sntf; // 0x3C, SATA notification (SCR4:SNotification) + HCore::UInt32 fbs; // 0x40, FIS-based switch control + HCore::UInt32 reserved1[11]; // 0x44 ~ 0x6F, Reserved + HCore::UInt32 vendor[4]; // 0x70 ~ 0x7F, vendor specific } HbaPort; typedef struct HbaMem final { // 0x00 - 0x2B, Generic Host Control - UInt32 cap; // 0x00, Host capability - UInt32 ghc; // 0x04, Global host control - UInt32 is; // 0x08, Interrupt status - UInt32 pi; // 0x0C, Port implemented - UInt32 vs; // 0x10, Version - UInt32 ccc_ctl; // 0x14, Command completion coalescing control - UInt32 ccc_pts; // 0x18, Command completion coalescing ports - UInt32 em_loc; // 0x1C, Enclosure management location - UInt32 em_ctl; // 0x20, Enclosure management control - UInt32 cap2; // 0x24, Host capabilities extended - UInt32 bohc; // 0x28, BIOS/OS handoff control and status - - UInt16 rsv; - UInt32 resv2; + HCore::UInt32 cap; // 0x00, Host capability + HCore::UInt32 ghc; // 0x04, Global host control + HCore::UInt32 is; // 0x08, Interrupt status + HCore::UInt32 pi; // 0x0C, Port implemented + HCore::UInt32 vs; // 0x10, Version + HCore::UInt32 ccc_ctl; // 0x14, Command completion coalescing control + HCore::UInt32 ccc_pts; // 0x18, Command completion coalescing ports + HCore::UInt32 em_loc; // 0x1C, Enclosure management location + HCore::UInt32 em_ctl; // 0x20, Enclosure management control + HCore::UInt32 cap2; // 0x24, Host capabilities extended + HCore::UInt32 bohc; // 0x28, BIOS/OS handoff control and status + + HCore::UInt16 rsv; + HCore::UInt32 resv2; HbaPort ports[1]; // 1 ~ 32 } HbaMem; typedef struct HbaCmdHeader final { // DW0 - UInt8 cfl : 5; // Command FIS length in DWORDS, 2 ~ 16 - UInt8 atapi : 1; // ATAPI - UInt8 write : 1; // Write, 1: H2D, 0: D2H - UInt8 prefetchable : 1; // Prefetchable + HCore::UInt8 cfl : 5; // Command FIS length in DWORDS, 2 ~ 16 + HCore::UInt8 atapi : 1; // ATAPI + HCore::UInt8 write : 1; // Write, 1: H2D, 0: D2H + HCore::UInt8 prefetchable : 1; // Prefetchable - UInt8 reset : 1; // Reset - UInt8 BIST : 1; // BIST - UInt8 clear : 1; // Clear busy upon R_OK - UInt8 reserved0 : 1; // Reserved - UInt8 pmp : 4; // Port multiplier port + HCore::UInt8 reset : 1; // Reset + HCore::UInt8 BIST : 1; // BIST + HCore::UInt8 clear : 1; // Clear busy upon R_OK + HCore::UInt8 reserved0 : 1; // Reserved + HCore::UInt8 pmp : 4; // Port multiplier port - UInt16 prdtl; // Physical region descriptor table length in entries - volatile UInt32 prdbc; // Physical region descriptor byte count transferred + HCore::UInt16 prdtl; // Physical region descriptor table length in entries + volatile HCore::UInt32 prdbc; // Physical region descriptor byte count transferred - UInt32 ctba; // Command table descriptor base address - UInt32 ctbau; // Command table descriptor base address upper 32 bits + HCore::UInt32 ctba; // Command table descriptor base address + HCore::UInt32 ctbau; // Command table descriptor base address upper 32 bits - UInt32 reserved1[4]; // Reserved + HCore::UInt32 reserved1[4]; // Reserved } HbaCmdHeader; typedef struct HbaFis final { // 0x00 FisDmaSetup dsfis; // DMA Setup FIS - UInt8 pad0[4]; + HCore::UInt8 pad0[4]; // 0x20 FisPioSetup psfis; // PIO Setup FIS - UInt8 pad1[12]; + HCore::UInt8 pad1[12]; // 0x40 FisRegD2H rfis; // Register – Device to Host FIS - UInt8 pad2[4]; + HCore::UInt8 pad2[4]; // 0x58 FisDevBits sdbfis; // Set Device Bit FIS // 0x60 - UInt8 ufis[64]; + HCore::UInt8 ufis[64]; // 0xA0 - UInt8 rsv[0x100 - 0xA0]; + HCore::UInt8 rsv[0x100 - 0xA0]; } HbaFis; typedef struct HbaPrdtEntry final { - UInt32 dba; // Data base address - UInt32 dbau; // Data base address upper 32 bits - UInt32 reserved0; // Reserved + HCore::UInt32 dba; // Data base address + HCore::UInt32 dbau; // Data base address upper 32 bits + HCore::UInt32 reserved0; // Reserved // DW3 - UInt32 dbc : 22; // Byte count, 4M max - UInt32 reserved1 : 9; // Reserved - UInt32 interruptBit : 1; // Interrupt on completion + HCore::UInt32 dbc : 22; // Byte count, 4M max + HCore::UInt32 reserved1 : 9; // Reserved + HCore::UInt32 interruptBit : 1; // Interrupt on completion } HbaPrdtEntry; typedef struct HbaCmdTbl final { - UInt8 cfis[64]; // Command FIS - UInt8 acmd[16]; // ATAPI command, 12 or 16 bytes - UInt8 rsv[48]; // Reserved - HbaPrdtEntry - prdtEntries[1]; // Physical region descriptor table entries, 0 ~ 65535 + HCore::UInt8 cfis[64]; // Command FIS + HCore::UInt8 acmd[16]; // ATAPI command, 12 or 16 bytes + HCore::UInt8 rsv[48]; // Reserved + HbaPrdtEntry prdtEntries[1]; // Physical region descriptor table entries, 0 ~ 65535 } HbaCmdTbl; /* diff --git a/Private/FSKit/NewFSIndexer.hxx b/Private/FSKit/NewFSIndexer.hxx index e66e4913..023ebdc0 100644 --- a/Private/FSKit/NewFSIndexer.hxx +++ b/Private/FSKit/NewFSIndexer.hxx @@ -13,7 +13,7 @@ namespace HCore { namespace Indexer { class INewFSIterator; -using IndexElement = voidPtr; +using IndexElement = VoidPtr; /// /// @name INewFSIterator @@ -22,7 +22,7 @@ using IndexElement = voidPtr; class INewFSIterator { public: - INewFSIterator() = default; + explicit INewFSIterator() = default; virtual ~INewFSIterator() = default; public: diff --git a/Private/HALKit/AMD64/HalDescriptorLoader.cpp b/Private/HALKit/AMD64/HalDescriptorLoader.cpp index a68fb54a..1dbe8e9e 100644 --- a/Private/HALKit/AMD64/HalDescriptorLoader.cpp +++ b/Private/HALKit/AMD64/HalDescriptorLoader.cpp @@ -25,11 +25,12 @@ STATIC ::HCore::Detail::AMD64::InterruptDescriptorAMD64 void IDTLoader::Load(Register64 &idt) { volatile ::HCore::UIntPtr **baseIdt = (volatile ::HCore::UIntPtr **)idt.Base; + MUST_PASS(baseIdt); - - MUST_PASS(baseIdt[0]); - + for (UInt16 i = 0; i < kKernelIdtSize; i++) { + MUST_PASS(baseIdt[i]); + kInterruptVectorTable[i].Selector = kGdtCodeSelector; kInterruptVectorTable[i].Ist = 0x0; kInterruptVectorTable[i].TypeAttributes = kInterruptGate; @@ -40,10 +41,9 @@ void IDTLoader::Load(Register64 &idt) { kInterruptVectorTable[i].Zero = 0x0; } - kRegIdt.Base = (UIntPtr)kInterruptVectorTable; + kRegIdt.Base = reinterpret_cast(kInterruptVectorTable); kRegIdt.Limit = sizeof(::HCore::Detail::AMD64::InterruptDescriptorAMD64) * - kKernelIdtSize - - 1; + (kKernelIdtSize - 1); rt_load_idt(kRegIdt); diff --git a/Private/HALKit/AMD64/HalInterruptHandlerAMD64.cxx b/Private/HALKit/AMD64/HalInterruptHandlerAMD64.cxx index be0932bd..34cf049e 100644 --- a/Private/HALKit/AMD64/HalInterruptHandlerAMD64.cxx +++ b/Private/HALKit/AMD64/HalInterruptHandlerAMD64.cxx @@ -9,21 +9,26 @@ #include -/// @brief Interrupt handler 21h, 10h -/// @param rsp stack pointer. - -#define kInterruptIdAlt 0x10 #define kInterruptId 0x21 -EXTERN_C ATTRIBUTE(naked) HCore::UIntPtr rt_handle_interrupts(HCore::UIntPtr rsp) +/// @brief Runtime interrupt handler +/// @param sf The stack frame pushed by the isr. +/// @return the stackframe pointer. +EXTERN_C ATTRIBUTE(naked) HCore::UIntPtr rt_handle_interrupts(HCore::UIntPtr sf) { - HCore::HAL::StackFramePtr stackPtr = reinterpret_cast(rsp); - - if (stackPtr->IntNum == kInterruptId || - stackPtr->IntNum == kInterruptIdAlt) { - /// Do system call TODO - + volatile HCore::HAL::StackFramePtr stackPtr = reinterpret_cast(sf); + MUST_PASS(stackPtr); + + switch (stackPtr->IntNum) + { + case kInterruptId: + { + /* TODO: HcOpenDevice and such syscalls. */ + break; + } + default: + break; } - return rsp; + return sf; } \ No newline at end of file diff --git a/Private/HALKit/AMD64/HalNewBoot.asm b/Private/HALKit/AMD64/HalNewBoot.asm index a18b6814..881c1728 100644 --- a/Private/HALKit/AMD64/HalNewBoot.asm +++ b/Private/HALKit/AMD64/HalNewBoot.asm @@ -34,7 +34,7 @@ Main: push rcx call RuntimeMain pop rcx -L0: +MainLoop: cli hlt jmp $ diff --git a/Private/HALKit/AMD64/Processor.hpp b/Private/HALKit/AMD64/Processor.hpp index e5e35f20..c69e35d0 100644 --- a/Private/HALKit/AMD64/Processor.hpp +++ b/Private/HALKit/AMD64/Processor.hpp @@ -23,8 +23,8 @@ #define kCPUBackendName "AMD64" -#define IsActiveLow(flag) (flag & 2) -#define IsLevelTriggered(flag) (flag & 8) +#define IsActiveLow(FLG) (FLG & 2) +#define IsLevelTriggered(FLG) (FLG & 8) #define kInterruptGate 0x8E #define kTrapGate 0xEF diff --git a/Private/KernelKit/PE.hpp b/Private/KernelKit/PE.hpp index 9ab094d9..3a2db99f 100644 --- a/Private/KernelKit/PE.hpp +++ b/Private/KernelKit/PE.hpp @@ -17,23 +17,26 @@ #include #include -typedef HCore::UIntPtr U64; -typedef HCore::UInt32 U32; -typedef HCore::UInt16 U16; -typedef HCore::UInt8 U8; -typedef U8 BYTE; +namespace Detail +{ + typedef HCore::UIntPtr U64; + typedef HCore::UInt32 U32; + typedef HCore::UInt16 U16; + typedef HCore::UInt8 U8; + typedef Detail::U8 BYTE; +} // namespace Detail #define kPeMagic 0x00004550 typedef struct ExecHeader final { - U32 mMagic; // PE\0\0 or 0x00004550 - U16 mMachine; - U16 mNumberOfSections; - U32 mTimeDateStamp; - U32 mPointerToSymbolTable; - U32 mNumberOfSymbols; - U16 mSizeOfOptionalHeader; - U16 mCharacteristics; + Detail::U32 mMagic; // PE\0\0 or 0x00004550 + Detail::U16 mMachine; + Detail::U16 mNumberOfSections; + Detail::U32 mTimeDateStamp; + Detail::U32 mPointerToSymbolTable; + Detail::U32 mNumberOfSymbols; + Detail::U16 mSizeOfOptionalHeader; + Detail::U16 mCharacteristics; } ALIGN(8) ExecHeader, *ExecHeaderPtr; #define kMagPE32 0x010b @@ -43,79 +46,80 @@ typedef struct ExecHeader final { #define kPEMachineARM64 0xaa64 typedef struct ExecOptionalHeader final { - U16 mMagic; // 0x010b - PE32, 0x020b - PE32+ (64 bit) - U8 mMajorLinkerVersion; - U8 mMinorLinkerVersion; - U64 mSizeOfCode; - U64 mSizeOfInitializedData; - U64 mSizeOfUninitializedData; - U32 mAddressOfEntryPoint; - U32 mBaseOfCode; - U64 mImageBase; - U32 mSectionAlignment; - U32 mFileAlignment; - U16 mMajorOperatingSystemVersion; - U16 mMinorOperatingSystemVersion; - U16 mMajorImageVersion; - U16 mMinorImageVersion; - U16 mMajorSubsystemVersion; - U16 mMinorSubsystemVersion; - U32 mWin32VersionValue; - U64 mSizeOfImage; - U64 mSizeOfHeaders; - U32 mCheckSum; - U16 mSubsystem; - U16 mDllCharacteristics; - U64 mSizeOfStackReserve; - U64 mSizeOfStackCommit; - U64 mSizeOfHeapReserve; - U64 mSizeOfHeapCommit; - U32 mLoaderFlags; - U32 mNumberOfRvaAndSizes; + Detail::U16 mMagic; // 0x010b - PE32, 0x020b - PE32+ (64 bit) + Detail::U8 mMajorLinkerVersion; + Detail::U8 mMinorLinkerVersion; + Detail::U64 mSizeOfCode; + Detail::U64 mSizeOfInitializedData; + Detail::U64 mSizeOfUninitializedData; + Detail::U32 mAddressOfEntryPoint; + Detail::U32 mBaseOfCode; + Detail::U64 mImageBase; + Detail::U32 mSectionAlignment; + Detail::U32 mFileAlignment; + Detail::U16 mMajorOperatingSystemVersion; + Detail::U16 mMinorOperatingSystemVersion; + Detail::U16 mMajorImageVersion; + Detail::U16 mMinorImageVersion; + Detail::U16 mMajorSubsystemVersion; + Detail::U16 mMinorSubsystemVersion; + Detail::U32 mWin32VersionValue; + Detail::U64 mSizeOfImage; + Detail::U64 mSizeOfHeaders; + Detail::U32 mCheckSum; + Detail::U16 mSubsystem; + Detail::U16 mDllCharacteristics; + Detail::U64 mSizeOfStackReserve; + Detail::U64 mSizeOfStackCommit; + Detail::U64 mSizeOfHeapReserve; + Detail::U64 mSizeOfHeapCommit; + Detail::U32 mLoaderFlags; + Detail::U32 mNumberOfRvaAndSizes; } ExecOptionalHeader, *ExecOptionalHeaderPtr; typedef struct ExecSectionHeader final { - BYTE mName[8]; - U32 mVirtualSize; - U32 mVirtualAddress; - U32 mSizeOfRawData; - U32 mPointerToRawData; - U32 mPointerToRelocations; - U32 mPointerToLinenumbers; - U16 mNumberOfRelocations; - U16 mNumberOfLinenumbers; - U32 mCharacteristics; + Detail::BYTE mName[8]; + Detail::U32 mVirtualSize; + Detail::U32 mVirtualAddress; + Detail::U32 mSizeOfRawData; + Detail::U32 mPointerToRawData; + Detail::U32 mPointerToRelocations; + Detail::U32 mPointerToLinenumbers; + Detail::U16 mNumberOfRelocations; + Detail::U16 mNumberOfLinenumbers; + Detail::U32 mCharacteristics; } ExecSectionHeader, *ExecSectionHeaderPtr; enum kExecDataDirParams { kExecExport, kExecImport, - kExecCnt, + kExecInvalid, + kExecCount, }; typedef struct ExecExportDirectory { - U32 mCharacteristics; - U32 mTimeDateStamp; - U16 mMajorVersion; - U16 mMinorVersion; - U32 mName; - U32 mBase; - U32 mNumberOfFunctions; - U32 mNumberOfNames; - U32 mAddressOfFunctions; // export table rva - U32 mAddressOfNames; - U32 mAddressOfNameOrdinal; // ordinal table rva + Detail::U32 mCharacteristics; + Detail::U32 mTimeDateStamp; + Detail::U16 mMajorVersion; + Detail::U16 mMinorVersion; + Detail::U32 mName; + Detail::U32 mBase; + Detail::U32 mNumberOfFunctions; + Detail::U32 mNumberOfNames; + Detail::U32 mAddressOfFunctions; // export table rva + Detail::U32 mAddressOfNames; + Detail::U32 mAddressOfNameOrdinal; // ordinal table rva } ExecExportDirectory, *ExecExportDirectoryPtr; typedef struct ExecImportDirectory { union { - U32 mCharacteristics; - U32 mOriginalFirstThunk; + Detail::U32 mCharacteristics; + Detail::U32 mOriginalFirstThunk; }; - U32 mTimeDateStamp; - U32 mForwarderChain; - U32 mNameRva; - U32 mThunkTableRva; + Detail::U32 mTimeDateStamp; + Detail::U32 mForwarderChain; + Detail::U32 mNameRva; + Detail::U32 mThunkTableRva; } ExecImportDirectory, *ExecImportDirectoryPtr; #define kPeStart "__hcore_subsys_start" diff --git a/Private/NewBoot/CxxRuntime/UnwindCxxKit.cxx b/Private/NewBoot/CxxRuntime/UnwindCxxKit.cxx new file mode 100644 index 00000000..551cb599 --- /dev/null +++ b/Private/NewBoot/CxxRuntime/UnwindCxxKit.cxx @@ -0,0 +1,29 @@ +/* + * ======================================================== + * + * CxxKit + * Copyright Mahrouss Logic, all rights reserved. + * + * ======================================================== + */ + +#include + +namespace cxxkit +{ +///! @brief C++ ABI unwinding +///! Fini array (r1) +///! Numbers of Fini (r2) +EXTERN_C void __unwind(void (**finis)(void), int cnt) +{ + for (int i = 0; i < cnt; ++i) + (finis[i])(); +} +} // namespace cxxkit + +EXTERN_C Int32 EfiMain(EfiHandlePtr handle, EfiSystemTable* SystemTable) +{ + SystemTable->ConOut->OutputString(SystemTable->ConOut, L"HCoreLdr: C++ Runtime Add-in\r\n"); + + return kEfiOk; +} \ No newline at end of file diff --git a/Private/NewBoot/CxxRuntime/unwind.cxx b/Private/NewBoot/CxxRuntime/unwind.cxx deleted file mode 100644 index 4f8807cd..00000000 --- a/Private/NewBoot/CxxRuntime/unwind.cxx +++ /dev/null @@ -1,8 +0,0 @@ -namespace cxxkit { -///! @brief C++ ABI unwinding -///! Fini array (r1) -///! Numbers of Fini (r2) -extern "C" void __unwind(void (**finis)(void), int cnt) { - for (int i = 0; i < cnt; ++i) (finis[i])(); -} -} // namespace cxxkit diff --git a/Private/NewBoot/NetBoot/EfiModule.cxx b/Private/NewBoot/NetBoot/EfiModule.cxx index 36a7288c..42415dc7 100644 --- a/Private/NewBoot/NetBoot/EfiModule.cxx +++ b/Private/NewBoot/NetBoot/EfiModule.cxx @@ -9,6 +9,7 @@ #include -extern "C" Int32 EfiMain(EfiHandlePtr handle, EfiSystemTable* SystemTable) { +EXTERN_C Int32 EfiMain(EfiHandlePtr handle, EfiSystemTable* SystemTable) +{ return kEfiOk; } -- cgit v1.2.3