MHR-21: work in progress arm64 support, made a structure to describe

opcodes.

Signed-off-by: Amlal EL Mahrouss <amlal@softwarelabs.com>

4 files changed, 60 insertions, 28 deletions

diff --git a/Comm/AsmKit/CPU/amd64.hpp b/Comm/AsmKit/CPU/amd64.hpp
index 63ed1b3..17b515b 100644
--- a/Comm/AsmKit/CPU/amd64.hpp
+++ b/Comm/AsmKit/CPU/amd64.hpp
@@ -39,18 +39,19 @@ struct CpuOpcodeAMD64
 
 inline std::vector<CpuOpcodeAMD64> kOpcodesAMD64 = {
 	kAsmOpcodeDecl("int", 0xCD)
-		kAsmOpcodeDecl("into", 0xCE)
-			kAsmOpcodeDecl("intd", 0xF1)
-				kAsmOpcodeDecl("int3", 0xC3)
-					kAsmOpcodeDecl("iret", 0xCF)
-						kAsmOpcodeDecl("retf", 0xCB)
-							kAsmOpcodeDecl("retn", 0xC3)
-								kAsmOpcodeDecl("ret", 0xC3)
-									kAsmOpcodeDecl("sti", 0xfb)
-										kAsmOpcodeDecl("cli", 0xfa)
-											kAsmOpcodeDecl("hlt", 0xf4)
-												kAsmOpcodeDecl("nop", 0x90)
-													kAsmOpcodeDecl("mov", 0x48)
-														kAsmOpcodeDecl("call", 0xFF)};
+	kAsmOpcodeDecl("into", 0xCE)
+	kAsmOpcodeDecl("intd", 0xF1)
+	kAsmOpcodeDecl("int3", 0xC3)
+	kAsmOpcodeDecl("iret", 0xCF)
+	kAsmOpcodeDecl("retf", 0xCB)
+	kAsmOpcodeDecl("retn", 0xC3)
+	kAsmOpcodeDecl("ret", 0xC3)
+	kAsmOpcodeDecl("sti", 0xfb)
+	kAsmOpcodeDecl("cli", 0xfa)
+	kAsmOpcodeDecl("hlt", 0xf4)
+	kAsmOpcodeDecl("nop", 0x90)
+	kAsmOpcodeDecl("mov", 0x48)
+	kAsmOpcodeDecl("call", 0xFF)
+};
 
 #define kAsmRegisterLimit 15
diff --git a/Comm/AsmKit/CPU/arm64.hpp b/Comm/AsmKit/CPU/arm64.hpp
new file mode 100644
index 0000000..a6b558a
--- /dev/null
+++ b/Comm/AsmKit/CPU/arm64.hpp
@@ -0,0 +1,27 @@
+/* -------------------------------------------
+
+Copyright Zeta Electronics Corporation
+
+------------------------------------------- */
+
+#pragma once
+
+#include <Comm/Defines.hpp>
+
+/// @brief ARM64 encoding support.
+/// @file CPU/arm64.hpp
+
+struct CpuOpcodeArm64;
+
+/// @brief ARM64 opcode header.
+struct CpuOpcodeArm64 final
+{
+	uint8_t fOpcode; // opcode
+	uint8_t fRegisterLeft; // left register index
+	uint8_t fRegisterRight; // right register index
+	bool fRegisterLeftHooked;
+	bool fRegisterRightHooked;
+	uint32_t fImmediateValue; // immediate 32-bit value
+	bool fImmediateValueHooked;
+};
+
diff --git a/Comm/AsmKit/CPU/ppc.hpp b/Comm/AsmKit/CPU/ppc.hpp
index c4265da..4afbf5a 100644
--- a/Comm/AsmKit/CPU/ppc.hpp
+++ b/Comm/AsmKit/CPU/ppc.hpp
@@ -1,3 +1,13 @@
+/* -------------------------------------------
+
+	Some modifications are copyrighted under:  
+	Zeta Electronics Corporation
+
+	Original author:
+	Apple Inc
+
+------------------------------------------- */
+
 #pragma once
 
 #include <cstdint>
diff --git a/Comm/Public/SDK/CRT/__mpcc_defines.hxx b/Comm/Public/SDK/CRT/__mpcc_defines.hxx
index c05ee73..a526fd3 100644
--- a/Comm/Public/SDK/CRT/__mpcc_defines.hxx
+++ b/Comm/Public/SDK/CRT/__mpcc_defines.hxx
@@ -30,8 +30,9 @@ typedef char*  caddr_t;
 #ifdef __GNUC__
 #include <CRT/__mpcc_alloca.hxx>
 #define __mpcc_alloca(sz) __mpcc_alloca_gcc(sz)
+#define __packed__ __attribute__((packed))
 #elif defined(__MPCC__)
-
+#define __packed__ __mpcc_packed__
 #define __alloca(sz) __mpcc_alloca(sz)
 #endif
 
@@ -41,24 +42,17 @@ typedef char*  caddr_t;
 #define __init_decl() \
 	extern "C"        \
 	{
+
+
 #define __fini_decl() \
-	}                 \
-	;
+	};				  \
+
+
 #else
 #define __init_decl()
 #define __fini_decl()
 #endif
 
-#if __has_builtin(__builtin_alloca)
-#define alloca(sz) __builtin_alloca(sz)
-#ifdef __alloca
-#undef __alloca
-#endif
-#define __alloca alloca
-#else
-#warning alloca not detected (MPCC)
-#endif
-
 typedef long long		   off_t;
 typedef unsigned long long uoff_t;
 
@@ -71,7 +65,7 @@ typedef union float_cast {
 	};
 
 	float f;
-} __attribute__((packed)) float_cast_t;
+} __packed__ float_cast_t;
 
 typedef union double_cast {
 	struct
@@ -82,7 +76,7 @@ typedef union double_cast {
 	};
 
 	double f;
-} __attribute__((packed)) double_cast_t;
+} __packed__ double_cast_t;
 
 #endif // ifndef __GNUC__