From befde76cfa46c766e81f74eb5ac65d3dae2dde87 Mon Sep 17 00:00:00 2001 From: Amlal El Mahrouss Date: Sat, 19 Apr 2025 17:33:26 +0200 Subject: dev, LibCompiler, tooling: refactor and separate components into modules (cppdrv, cxxdrv) Signed-off-by: Amlal El Mahrouss --- dev/LibCompiler/Backend/arm64.h | 44 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 dev/LibCompiler/Backend/arm64.h (limited to 'dev/LibCompiler/Backend/arm64.h') diff --git a/dev/LibCompiler/Backend/arm64.h b/dev/LibCompiler/Backend/arm64.h new file mode 100644 index 0000000..08096ee --- /dev/null +++ b/dev/LibCompiler/Backend/arm64.h @@ -0,0 +1,44 @@ +/* ------------------------------------------- + +Copyright (C) 2024-2025 Amlal EL Mahrous, all rights reserved + +------------------------------------------- */ + +#pragma once + +#include +#include + +/// @brief ARM64 encoding support. +/// @file Backend/arm64.hpp + +struct CpuOpcodeArm64; + +/// @brief ARM64 opcode header. +struct PACKED CpuOpcodeArm64_Data final +{ + uint32_t fOpcode : 10; // Bits 31–22: Opcode for operation + uint32_t fRm : 5; // Bits 21–16: Source register Rm + uint32_t fShamt : 6; // Bits 15–10: Shift amount + uint32_t fRn : 5; // Bits 9–5: Source register Rn + uint32_t fRd : 5; // Bits 4–0: Destination register Rd +}; + +typedef struct +{ + uint32_t opcode : 6; // Bits 31–26: Branch opcode + int32_t offset : 26; // Bits 25–0: Signed offset (branch target) +} PACKED CpuOpcodeArm64_Branch; + +typedef struct +{ + uint32_t size : 2; // Bits 31–30: Size of the data + uint32_t opcode : 7; // Bits 29–23: Opcode for load/store + uint32_t offset : 12; // Bits 22–10: Offset + uint32_t rn : 5; // Bits 9–5: Base address register Rn + uint32_t rt : 5; // Bits 4–0: Target/source register Rt +} PACKED CpuOpcodeArm64_LoadStore; + +#define kAsmRegisterLimit (30) +#define kAsmRegisterPrefix "x" +#define kOpcodeARM64Count (1000) -- cgit v1.2.3