From 20042235d1f53ae428aa154e64afdbae5d8d91ad Mon Sep 17 00:00:00 2001 From: Amlal Date: Fri, 25 Apr 2025 13:14:01 +0200 Subject: meta: update .clang-format, format codebase. Signed-off-by: Amlal --- dev/LibCompiler/Backend/32x0.h | 68 +- dev/LibCompiler/Backend/64x0.h | 85 +- dev/LibCompiler/Backend/amd64.h | 48 +- dev/LibCompiler/Backend/arm64.h | 39 +- dev/LibCompiler/Backend/power64.h | 3404 +++++++++++++++++-------------------- 5 files changed, 1625 insertions(+), 2019 deletions(-) (limited to 'dev/LibCompiler/Backend') diff --git a/dev/LibCompiler/Backend/32x0.h b/dev/LibCompiler/Backend/32x0.h index 32f31ff..bb0a5aa 100644 --- a/dev/LibCompiler/Backend/32x0.h +++ b/dev/LibCompiler/Backend/32x0.h @@ -1,6 +1,6 @@ /* ------------------------------------------- - Copyright (C) 2024-2025 Amlal EL Mahrous, all rights reserved + Copyright (C) 2024-2025 Amlal EL Mahrous, all rights reserved ------------------------------------------- */ @@ -12,47 +12,43 @@ // @file Backend/32x0.hpp #define kAsmOpcodeDecl(__NAME, __OPCODE, __FUNCT3, __FUNCT7) \ - {.fName = __NAME, \ - .fOpcode = __OPCODE, \ - .fFunct3 = __FUNCT3, \ - .fFunct7 = __FUNCT7}, + {.fName = __NAME, .fOpcode = __OPCODE, .fFunct3 = __FUNCT3, .fFunct7 = __FUNCT7}, #define kAsmImmediate 0x01 -#define kAsmSyscall 0x02 -#define kAsmJump 0x03 -#define kAsmNoArgs 0x04 +#define kAsmSyscall 0x02 +#define kAsmJump 0x03 +#define kAsmNoArgs 0x04 -#define kAsmByte 0 +#define kAsmByte 0 #define kAsmHWord 1 -#define kAsmWord 2 - -struct CpuCode32x0 -{ - const char fName[32]; - uint8_t fOpcode; - uint8_t fSize; - uint8_t fFunct3; - uint8_t fFunct7; +#define kAsmWord 2 + +struct CpuCode32x0 { + const char fName[32]; + uint8_t fOpcode; + uint8_t fSize; + uint8_t fFunct3; + uint8_t fFunct7; }; #define kAsmDWordStr ".dword" /* 64 bit */ -#define kAsmWordStr ".word" /* 32-bit */ +#define kAsmWordStr ".word" /* 32-bit */ #define kAsmHWordStr ".half" /* 16-bit */ -#define kAsmByteStr ".byte" /* 8-bit */ +#define kAsmByteStr ".byte" /* 8-bit */ inline std::vector kOpcodes32x0 = { - kAsmOpcodeDecl("nop", 0b0100011, 0b000, kAsmNoArgs) // nothing to do. (1C) - kAsmOpcodeDecl("jmp", 0b1110011, 0b001, kAsmJump) // jump to branch (2C) - kAsmOpcodeDecl("mov", 0b0100011, 0b101, kAsmImmediate) // move registers (3C) - kAsmOpcodeDecl("psh", 0b0111011, 0b000, kAsmImmediate) // push to sp (2C) - kAsmOpcodeDecl("pop", 0b0111011, 0b001, kAsmImmediate) // pop from sp. (1C) - kAsmOpcodeDecl("lea", 0b0111011, 0b010, - kAsmImmediate) // setup stack and call, store address to CR (1C). - kAsmOpcodeDecl("ret", 0b0111011, 0b110, - kAsmImmediate) // return from procedure (2C). - kAsmOpcodeDecl("uc", 0b0111111, 0b000, kAsmSyscall) // user call (1C) - kAsmOpcodeDecl("kc", 0b0111111, 0b001, kAsmSyscall) // kernel call (1C) - kAsmOpcodeDecl("int", 0b0111111, 0b010, kAsmSyscall) // raise interrupt (1C) + kAsmOpcodeDecl("nop", 0b0100011, 0b000, kAsmNoArgs) // nothing to do. (1C) + kAsmOpcodeDecl("jmp", 0b1110011, 0b001, kAsmJump) // jump to branch (2C) + kAsmOpcodeDecl("mov", 0b0100011, 0b101, kAsmImmediate) // move registers (3C) + kAsmOpcodeDecl("psh", 0b0111011, 0b000, kAsmImmediate) // push to sp (2C) + kAsmOpcodeDecl("pop", 0b0111011, 0b001, kAsmImmediate) // pop from sp. (1C) + kAsmOpcodeDecl("lea", 0b0111011, 0b010, + kAsmImmediate) // setup stack and call, store address to CR (1C). + kAsmOpcodeDecl("ret", 0b0111011, 0b110, + kAsmImmediate) // return from procedure (2C). + kAsmOpcodeDecl("uc", 0b0111111, 0b000, kAsmSyscall) // user call (1C) + kAsmOpcodeDecl("kc", 0b0111111, 0b001, kAsmSyscall) // kernel call (1C) + kAsmOpcodeDecl("int", 0b0111111, 0b010, kAsmSyscall) // raise interrupt (1C) }; // \brief 64x0 register prefix @@ -61,10 +57,10 @@ inline std::vector kOpcodes32x0 = { // r0 -> hw zero #define kAsmRegisterPrefix "r" -#define kAsmRegisterLimit 16 -#define kAsmPcRegister 17 -#define kAsmCrRegister 18 -#define kAsmSpRegister 5 +#define kAsmRegisterLimit 16 +#define kAsmPcRegister 17 +#define kAsmCrRegister 18 +#define kAsmSpRegister 5 /* return address register */ #define kAsmRetRegister 19 diff --git a/dev/LibCompiler/Backend/64x0.h b/dev/LibCompiler/Backend/64x0.h index a0084b1..745dff0 100644 --- a/dev/LibCompiler/Backend/64x0.h +++ b/dev/LibCompiler/Backend/64x0.h @@ -1,6 +1,6 @@ /* ------------------------------------------- - Copyright (C) 2024-2025 Amlal EL Mahrous, all rights reserved + Copyright (C) 2024-2025 Amlal EL Mahrous, all rights reserved ------------------------------------------- */ @@ -13,53 +13,48 @@ // @file Backend/64x0.hpp #define kAsmOpcodeDecl(__NAME, __OPCODE, __FUNCT3, __FUNCT7) \ - {.fName = __NAME, \ - .fOpcode = __OPCODE, \ - .fFunct3 = __FUNCT3, \ - .fFunct7 = __FUNCT7}, + {.fName = __NAME, .fOpcode = __OPCODE, .fFunct3 = __FUNCT3, .fFunct7 = __FUNCT7}, #define kAsmImmediate 0x01 -#define kAsmRegToReg 0x02 -#define kAsmSyscall 0x03 -#define kAsmJump 0x04 -#define kAsmNoArgs 0x00 +#define kAsmRegToReg 0x02 +#define kAsmSyscall 0x03 +#define kAsmJump 0x04 +#define kAsmNoArgs 0x00 -typedef char e64k_character_t; +typedef char e64k_character_t; typedef uint8_t e64k_num_t; -struct CpuOpcode64x0 -{ - const e64k_character_t fName[32]; - e64k_num_t fOpcode; - e64k_num_t fFunct3; - e64k_num_t fFunct7; +struct CpuOpcode64x0 { + const e64k_character_t fName[32]; + e64k_num_t fOpcode; + e64k_num_t fFunct3; + e64k_num_t fFunct7; }; inline std::vector kOpcodes64x0 = { - kAsmOpcodeDecl("nop", 0b0000000, 0b0000000, kAsmNoArgs) // no-operation. - kAsmOpcodeDecl("np", 0b0000000, 0b0000000, kAsmNoArgs) // no-operation. - kAsmOpcodeDecl("jlr", 0b1110011, 0b0000111, - kAsmJump) // jump to linked return register - kAsmOpcodeDecl("jrl", 0b1110011, 0b0001111, - kAsmJump) // jump from return register. - kAsmOpcodeDecl("mv", 0b0100011, 0b101, kAsmRegToReg) - kAsmOpcodeDecl("bg", 0b1100111, 0b111, kAsmRegToReg) - kAsmOpcodeDecl("bl", 0b1100111, 0b011, kAsmRegToReg) - kAsmOpcodeDecl("beq", 0b1100111, 0b000, kAsmRegToReg) - kAsmOpcodeDecl("bne", 0b1100111, 0b001, kAsmRegToReg) - kAsmOpcodeDecl("bge", 0b1100111, 0b101, kAsmRegToReg) - kAsmOpcodeDecl("ble", 0b1100111, 0b100, kAsmRegToReg) - kAsmOpcodeDecl("stw", 0b0001111, 0b100, kAsmImmediate) - kAsmOpcodeDecl("ldw", 0b0001111, 0b100, kAsmImmediate) - kAsmOpcodeDecl("lda", 0b0001111, 0b101, kAsmImmediate) - kAsmOpcodeDecl("sta", 0b0001111, 0b001, kAsmImmediate) - // add/sub without carry flag - kAsmOpcodeDecl("add", 0b0101011, 0b100, kAsmImmediate) - kAsmOpcodeDecl("sub", 0b0101011, 0b101, kAsmImmediate) - // add/sub with carry flag - kAsmOpcodeDecl("addc", 0b0101011, 0b110, kAsmImmediate) - kAsmOpcodeDecl("subc", 0b0101011, 0b111, kAsmImmediate) - kAsmOpcodeDecl("sc", 0b1110011, 0b00, kAsmSyscall)}; + kAsmOpcodeDecl("nop", 0b0000000, 0b0000000, kAsmNoArgs) // no-operation. + kAsmOpcodeDecl("np", 0b0000000, 0b0000000, kAsmNoArgs) // no-operation. + kAsmOpcodeDecl("jlr", 0b1110011, 0b0000111, + kAsmJump) // jump to linked return register + kAsmOpcodeDecl("jrl", 0b1110011, 0b0001111, + kAsmJump) // jump from return register. + kAsmOpcodeDecl("mv", 0b0100011, 0b101, kAsmRegToReg) kAsmOpcodeDecl( + "bg", 0b1100111, 0b111, kAsmRegToReg) kAsmOpcodeDecl("bl", 0b1100111, 0b011, kAsmRegToReg) + kAsmOpcodeDecl("beq", 0b1100111, 0b000, kAsmRegToReg) + kAsmOpcodeDecl("bne", 0b1100111, 0b001, kAsmRegToReg) + kAsmOpcodeDecl("bge", 0b1100111, 0b101, kAsmRegToReg) + kAsmOpcodeDecl("ble", 0b1100111, 0b100, kAsmRegToReg) + kAsmOpcodeDecl("stw", 0b0001111, 0b100, kAsmImmediate) + kAsmOpcodeDecl("ldw", 0b0001111, 0b100, kAsmImmediate) + kAsmOpcodeDecl("lda", 0b0001111, 0b101, kAsmImmediate) + kAsmOpcodeDecl("sta", 0b0001111, 0b001, kAsmImmediate) + // add/sub without carry flag + kAsmOpcodeDecl("add", 0b0101011, 0b100, kAsmImmediate) + kAsmOpcodeDecl("sub", 0b0101011, 0b101, kAsmImmediate) + // add/sub with carry flag + kAsmOpcodeDecl("addc", 0b0101011, 0b110, kAsmImmediate) + kAsmOpcodeDecl("subc", 0b0101011, 0b111, kAsmImmediate) + kAsmOpcodeDecl("sc", 0b1110011, 0b00, kAsmSyscall)}; // \brief 64x0 register prefix // example: r32, r0 @@ -67,13 +62,13 @@ inline std::vector kOpcodes64x0 = { // r0 -> hw zero #define kAsmFloatZeroRegister 0 -#define kAsmZeroRegister 0 +#define kAsmZeroRegister 0 #define kAsmRegisterPrefix "r" -#define kAsmRegisterLimit 30 -#define kAsmPcRegister 17 -#define kAsmCrRegister 18 -#define kAsmSpRegister 5 +#define kAsmRegisterLimit 30 +#define kAsmPcRegister 17 +#define kAsmCrRegister 18 +#define kAsmSpRegister 5 /* return address register */ #define kAsmRetRegister 19 diff --git a/dev/LibCompiler/Backend/amd64.h b/dev/LibCompiler/Backend/amd64.h index 8486b01..f42b131 100644 --- a/dev/LibCompiler/Backend/amd64.h +++ b/dev/LibCompiler/Backend/amd64.h @@ -1,6 +1,6 @@ /* ------------------------------------------- - Copyright (C) 2024-2025 Amlal EL Mahrous, all rights reserved + Copyright (C) 2024-2025 Amlal EL Mahrous, all rights reserved ------------------------------------------- */ @@ -13,46 +13,36 @@ #define kAsmOpcodeDecl(__NAME, __OPCODE) {.fName = __NAME, .fOpcode = __OPCODE}, -typedef char i64_character_t; -typedef uint8_t i64_byte_t; +typedef char i64_character_t; +typedef uint8_t i64_byte_t; typedef uint16_t i64_hword_t; typedef uint32_t i64_word_t; #define kAsmRegisterPrefix "r" -struct CpuOpcodeAMD64 -{ - std::string fName; - i64_byte_t fPrefixBytes[4]; - i64_hword_t fOpcode; - i64_hword_t fModReg; - i64_word_t fDisplacment; - i64_word_t fImmediate; +struct CpuOpcodeAMD64 { + std::string fName; + i64_byte_t fPrefixBytes[4]; + i64_hword_t fOpcode; + i64_hword_t fModReg; + i64_word_t fDisplacment; + i64_word_t fImmediate; }; /// these two are edge cases -#define kAsmIntOpcode 0xCC +#define kAsmIntOpcode 0xCC #define kasmIntOpcodeAlt 0xCD -#define kAsmJumpOpcode 0x0F80 -#define kJumpLimit 30 -#define kJumpLimitStandard 0xE3 +#define kAsmJumpOpcode 0x0F80 +#define kJumpLimit 30 +#define kJumpLimitStandard 0xE3 #define kJumpLimitStandardLimit 0xEB inline std::vector kOpcodesAMD64 = { - kAsmOpcodeDecl("int", 0xCD) - kAsmOpcodeDecl("into", 0xCE) - kAsmOpcodeDecl("intd", 0xF1) - kAsmOpcodeDecl("int3", 0xC3) - kAsmOpcodeDecl("iret", 0xCF) - kAsmOpcodeDecl("retf", 0xCB) - kAsmOpcodeDecl("retn", 0xC3) - kAsmOpcodeDecl("ret", 0xC3) - kAsmOpcodeDecl("sti", 0xfb) - kAsmOpcodeDecl("cli", 0xfa) - kAsmOpcodeDecl("hlt", 0xf4) - kAsmOpcodeDecl("nop", 0x90) - kAsmOpcodeDecl("mov", 0x48) - kAsmOpcodeDecl("call", 0xFF)}; + kAsmOpcodeDecl("int", 0xCD) kAsmOpcodeDecl("into", 0xCE) kAsmOpcodeDecl("intd", 0xF1) + kAsmOpcodeDecl("int3", 0xC3) kAsmOpcodeDecl("iret", 0xCF) kAsmOpcodeDecl("retf", 0xCB) + kAsmOpcodeDecl("retn", 0xC3) kAsmOpcodeDecl("ret", 0xC3) kAsmOpcodeDecl("sti", 0xfb) + kAsmOpcodeDecl("cli", 0xfa) kAsmOpcodeDecl("hlt", 0xf4) kAsmOpcodeDecl("nop", 0x90) + kAsmOpcodeDecl("mov", 0x48) kAsmOpcodeDecl("call", 0xFF)}; #define kAsmRegisterLimit 16 diff --git a/dev/LibCompiler/Backend/arm64.h b/dev/LibCompiler/Backend/arm64.h index 08096ee..fb91a1c 100644 --- a/dev/LibCompiler/Backend/arm64.h +++ b/dev/LibCompiler/Backend/arm64.h @@ -6,8 +6,8 @@ Copyright (C) 2024-2025 Amlal EL Mahrous, all rights reserved #pragma once -#include #include +#include /// @brief ARM64 encoding support. /// @file Backend/arm64.hpp @@ -15,30 +15,27 @@ Copyright (C) 2024-2025 Amlal EL Mahrous, all rights reserved struct CpuOpcodeArm64; /// @brief ARM64 opcode header. -struct PACKED CpuOpcodeArm64_Data final -{ - uint32_t fOpcode : 10; // Bits 31–22: Opcode for operation - uint32_t fRm : 5; // Bits 21–16: Source register Rm - uint32_t fShamt : 6; // Bits 15–10: Shift amount - uint32_t fRn : 5; // Bits 9–5: Source register Rn - uint32_t fRd : 5; // Bits 4–0: Destination register Rd +struct PACKED CpuOpcodeArm64_Data final { + uint32_t fOpcode : 10; // Bits 31–22: Opcode for operation + uint32_t fRm : 5; // Bits 21–16: Source register Rm + uint32_t fShamt : 6; // Bits 15–10: Shift amount + uint32_t fRn : 5; // Bits 9–5: Source register Rn + uint32_t fRd : 5; // Bits 4–0: Destination register Rd }; -typedef struct -{ - uint32_t opcode : 6; // Bits 31–26: Branch opcode - int32_t offset : 26; // Bits 25–0: Signed offset (branch target) +typedef struct { + uint32_t opcode : 6; // Bits 31–26: Branch opcode + int32_t offset : 26; // Bits 25–0: Signed offset (branch target) } PACKED CpuOpcodeArm64_Branch; -typedef struct -{ - uint32_t size : 2; // Bits 31–30: Size of the data - uint32_t opcode : 7; // Bits 29–23: Opcode for load/store - uint32_t offset : 12; // Bits 22–10: Offset - uint32_t rn : 5; // Bits 9–5: Base address register Rn - uint32_t rt : 5; // Bits 4–0: Target/source register Rt +typedef struct { + uint32_t size : 2; // Bits 31–30: Size of the data + uint32_t opcode : 7; // Bits 29–23: Opcode for load/store + uint32_t offset : 12; // Bits 22–10: Offset + uint32_t rn : 5; // Bits 9–5: Base address register Rn + uint32_t rt : 5; // Bits 4–0: Target/source register Rt } PACKED CpuOpcodeArm64_LoadStore; -#define kAsmRegisterLimit (30) +#define kAsmRegisterLimit (30) #define kAsmRegisterPrefix "x" -#define kOpcodeARM64Count (1000) +#define kOpcodeARM64Count (1000) diff --git a/dev/LibCompiler/Backend/power64.h b/dev/LibCompiler/Backend/power64.h index 0f797a5..03aea49 100644 --- a/dev/LibCompiler/Backend/power64.h +++ b/dev/LibCompiler/Backend/power64.h @@ -1,10 +1,10 @@ /* ------------------------------------------- - Some modifications are copyrighted under: - Amlal El Mahrouss + Some modifications are copyrighted under: + Amlal El Mahrouss - Original author: - Apple Inc + Original author: + Apple Inc ------------------------------------------- */ @@ -22,1908 +22,1536 @@ * is zero it can execute on all cpus. The defines are or'ed together. This * information is used to set the cpusubtype in the resulting object file. */ -#define CPU601 0x1 -#define IMPL64 0x2 -#define OPTIONAL 0x4 -#define VMX 0x8 -#define CPU970 0x10 /* added to OPTIONAL insts that the 970 has */ +#define CPU601 0x1 +#define IMPL64 0x2 +#define OPTIONAL 0x4 +#define VMX 0x8 +#define CPU970 0x10 /* added to OPTIONAL insts that the 970 has */ #define CPUMAHROUSS 0x12 /* optional mahrouss insts. */ -enum OpcodeType -{ - NONE, /* no operand */ - JBSR, /* jbsr pseudo op */ - PCREL, /* PC relative (branch offset) */ - BADDR, /* Branch address (sign extended absolute address) */ - D, /* 16 bit displacement */ - DS, /* 14 bit displacement (double word) */ - SI, /* signed 16 bit immediate */ - UI, /* unsigned 16 bit immediate */ - HI, /* high 16 bit immediate (with truncation) */ - GREG, /* general register */ - G0REG, /* general register r1-r31 or 0 */ - FREG, /* float register */ - VREG, /* vector register */ - SGREG, /* segment register */ - SPREG, /* special register (or 10 bit number, 5 bit halves reversed) */ - BCND, /* branch condition opcode */ - CRF, /* condition register field */ - CRFONLY, /* condition register field only no expression allowed */ - sh, /* 6 bit number (0 - 63) (sh field, split and reversed) */ - mb, /* 6 bit number (0 - 63) (mb field, mb5 || mb0:4 reversed) */ - NUM, /* number */ - SNUM, /* signed number */ - NUM0, /* number (where 1<