From f6b400b80efc64b918c03352e93ec9de4e2369a1 Mon Sep 17 00:00:00 2001 From: Amlal Date: Fri, 25 Apr 2025 19:21:22 +0200 Subject: dev, general: codebase needed refactors and tweaks, for NeKernel's 0.0.2 release. details: - things needed to be cleared off, short sighted decisions fixed. - the inconsistency of certain files have been fixed too. Signed-off-by: Amlal --- dev/LibCompiler/Backend/32x0.h | 2 +- dev/LibCompiler/Backend/64x0.h | 31 +- dev/LibCompiler/Backend/Aarch64.h | 41 + dev/LibCompiler/Backend/Amd64.h | 48 ++ dev/LibCompiler/Backend/PowerPC.h | 1557 +++++++++++++++++++++++++++++++++++++ dev/LibCompiler/Backend/amd64.h | 48 -- dev/LibCompiler/Backend/arm64.h | 41 - dev/LibCompiler/Backend/power64.h | 1557 ------------------------------------- 8 files changed, 1664 insertions(+), 1661 deletions(-) create mode 100644 dev/LibCompiler/Backend/Aarch64.h create mode 100644 dev/LibCompiler/Backend/Amd64.h create mode 100644 dev/LibCompiler/Backend/PowerPC.h delete mode 100644 dev/LibCompiler/Backend/amd64.h delete mode 100644 dev/LibCompiler/Backend/arm64.h delete mode 100644 dev/LibCompiler/Backend/power64.h (limited to 'dev/LibCompiler/Backend') diff --git a/dev/LibCompiler/Backend/32x0.h b/dev/LibCompiler/Backend/32x0.h index bb0a5aa..49bb978 100644 --- a/dev/LibCompiler/Backend/32x0.h +++ b/dev/LibCompiler/Backend/32x0.h @@ -9,7 +9,7 @@ #include // @brief 32x0 support. -// @file Backend/32x0.hpp +// @file Backend/32x0.h #define kAsmOpcodeDecl(__NAME, __OPCODE, __FUNCT3, __FUNCT7) \ {.fName = __NAME, .fOpcode = __OPCODE, .fFunct3 = __FUNCT3, .fFunct7 = __FUNCT7}, diff --git a/dev/LibCompiler/Backend/64x0.h b/dev/LibCompiler/Backend/64x0.h index 745dff0..b2c4b56 100644 --- a/dev/LibCompiler/Backend/64x0.h +++ b/dev/LibCompiler/Backend/64x0.h @@ -10,7 +10,7 @@ #include // @brief 64x0 support. -// @file Backend/64x0.hpp +// @file Backend/64x0.h #define kAsmOpcodeDecl(__NAME, __OPCODE, __FUNCT3, __FUNCT7) \ {.fName = __NAME, .fOpcode = __OPCODE, .fFunct3 = __FUNCT3, .fFunct7 = __FUNCT7}, @@ -38,23 +38,26 @@ inline std::vector kOpcodes64x0 = { kAsmJump) // jump to linked return register kAsmOpcodeDecl("jrl", 0b1110011, 0b0001111, kAsmJump) // jump from return register. - kAsmOpcodeDecl("mv", 0b0100011, 0b101, kAsmRegToReg) kAsmOpcodeDecl( - "bg", 0b1100111, 0b111, kAsmRegToReg) kAsmOpcodeDecl("bl", 0b1100111, 0b011, kAsmRegToReg) - kAsmOpcodeDecl("beq", 0b1100111, 0b000, kAsmRegToReg) - kAsmOpcodeDecl("bne", 0b1100111, 0b001, kAsmRegToReg) - kAsmOpcodeDecl("bge", 0b1100111, 0b101, kAsmRegToReg) - kAsmOpcodeDecl("ble", 0b1100111, 0b100, kAsmRegToReg) - kAsmOpcodeDecl("stw", 0b0001111, 0b100, kAsmImmediate) - kAsmOpcodeDecl("ldw", 0b0001111, 0b100, kAsmImmediate) - kAsmOpcodeDecl("lda", 0b0001111, 0b101, kAsmImmediate) - kAsmOpcodeDecl("sta", 0b0001111, 0b001, kAsmImmediate) + kAsmOpcodeDecl("mv", 0b0100011, 0b101, kAsmRegToReg) + kAsmOpcodeDecl( + "bg", 0b1100111, 0b111, kAsmRegToReg) + kAsmOpcodeDecl("bl", 0b1100111, 0b011, kAsmRegToReg) + kAsmOpcodeDecl("beq", 0b1100111, 0b000, kAsmRegToReg) + kAsmOpcodeDecl("bne", 0b1100111, 0b001, kAsmRegToReg) + kAsmOpcodeDecl("bge", 0b1100111, 0b101, kAsmRegToReg) + kAsmOpcodeDecl("ble", 0b1100111, 0b100, kAsmRegToReg) + kAsmOpcodeDecl("stw", 0b0001111, 0b100, kAsmImmediate) + kAsmOpcodeDecl("ldw", 0b0001111, 0b100, kAsmImmediate) + kAsmOpcodeDecl("lda", 0b0001111, 0b101, kAsmImmediate) + kAsmOpcodeDecl("sta", 0b0001111, 0b001, kAsmImmediate) // add/sub without carry flag kAsmOpcodeDecl("add", 0b0101011, 0b100, kAsmImmediate) - kAsmOpcodeDecl("sub", 0b0101011, 0b101, kAsmImmediate) + kAsmOpcodeDecl("sub", 0b0101011, 0b101, kAsmImmediate) // add/sub with carry flag kAsmOpcodeDecl("addc", 0b0101011, 0b110, kAsmImmediate) - kAsmOpcodeDecl("subc", 0b0101011, 0b111, kAsmImmediate) - kAsmOpcodeDecl("sc", 0b1110011, 0b00, kAsmSyscall)}; + kAsmOpcodeDecl("subc", 0b0101011, 0b111, kAsmImmediate) + kAsmOpcodeDecl("sc", 0b1110011, 0b00, kAsmSyscall) +}; // \brief 64x0 register prefix // example: r32, r0 diff --git a/dev/LibCompiler/Backend/Aarch64.h b/dev/LibCompiler/Backend/Aarch64.h new file mode 100644 index 0000000..dcafa0a --- /dev/null +++ b/dev/LibCompiler/Backend/Aarch64.h @@ -0,0 +1,41 @@ +/* ------------------------------------------- + +Copyright (C) 2024-2025 Amlal EL Mahrous, all rights reserved + +------------------------------------------- */ + +#pragma once + +#include +#include + +/// @brief ARM64 encoding support. +/// @file Backend/Aarch64.h + +struct CpuOpcodeArm64; + +/// @brief ARM64 opcode header. +struct PACKED CpuOpcodeArm64_Data final { + uint32_t fOpcode : 10; // Bits 31–22: Opcode for operation + uint32_t fRm : 5; // Bits 21–16: Source register Rm + uint32_t fShamt : 6; // Bits 15–10: Shift amount + uint32_t fRn : 5; // Bits 9–5: Source register Rn + uint32_t fRd : 5; // Bits 4–0: Destination register Rd +}; + +typedef struct { + uint32_t opcode : 6; // Bits 31–26: Branch opcode + int32_t offset : 26; // Bits 25–0: Signed offset (branch target) +} PACKED CpuOpcodeArm64_Branch; + +typedef struct { + uint32_t size : 2; // Bits 31–30: Size of the data + uint32_t opcode : 7; // Bits 29–23: Opcode for load/store + uint32_t offset : 12; // Bits 22–10: Offset + uint32_t rn : 5; // Bits 9–5: Base address register Rn + uint32_t rt : 5; // Bits 4–0: Target/source register Rt +} PACKED CpuOpcodeArm64_LoadStore; + +#define kAsmRegisterLimit (30) +#define kAsmRegisterPrefix "x" +#define kOpcodeARM64Count (1000) diff --git a/dev/LibCompiler/Backend/Amd64.h b/dev/LibCompiler/Backend/Amd64.h new file mode 100644 index 0000000..a3fb8a2 --- /dev/null +++ b/dev/LibCompiler/Backend/Amd64.h @@ -0,0 +1,48 @@ +/* ------------------------------------------- + + Copyright (C) 2024-2025 Amlal EL Mahrous, all rights reserved + +------------------------------------------- */ + +#pragma once + +#include + +// @brief AMD64 support. +// @file Backend/Amd64.h + +#define kAsmOpcodeDecl(__NAME, __OPCODE) {.fName = __NAME, .fOpcode = __OPCODE}, + +typedef char i64_character_t; +typedef uint8_t i64_byte_t; +typedef uint16_t i64_hword_t; +typedef uint32_t i64_word_t; + +#define kAsmRegisterPrefix "r" + +struct CpuOpcodeAMD64 { + std::string fName; + i64_byte_t fPrefixBytes[4]; + i64_hword_t fOpcode; + i64_hword_t fModReg; + i64_word_t fDisplacment; + i64_word_t fImmediate; +}; + +/// these two are edge cases +#define kAsmIntOpcode 0xCC +#define kasmIntOpcodeAlt 0xCD + +#define kAsmJumpOpcode 0x0F80 +#define kJumpLimit 30 +#define kJumpLimitStandard 0xE3 +#define kJumpLimitStandardLimit 0xEB + +inline std::vector kOpcodesAMD64 = { + kAsmOpcodeDecl("int", 0xCD) kAsmOpcodeDecl("into", 0xCE) kAsmOpcodeDecl("intd", 0xF1) + kAsmOpcodeDecl("int3", 0xC3) kAsmOpcodeDecl("iret", 0xCF) kAsmOpcodeDecl("retf", 0xCB) + kAsmOpcodeDecl("retn", 0xC3) kAsmOpcodeDecl("ret", 0xC3) kAsmOpcodeDecl("sti", 0xfb) + kAsmOpcodeDecl("cli", 0xfa) kAsmOpcodeDecl("hlt", 0xf4) kAsmOpcodeDecl("nop", 0x90) + kAsmOpcodeDecl("mov", 0x48) kAsmOpcodeDecl("call", 0xFF)}; + +#define kAsmRegisterLimit 16 diff --git a/dev/LibCompiler/Backend/PowerPC.h b/dev/LibCompiler/Backend/PowerPC.h new file mode 100644 index 0000000..03aea49 --- /dev/null +++ b/dev/LibCompiler/Backend/PowerPC.h @@ -0,0 +1,1557 @@ +/* ------------------------------------------- + + Some modifications are copyrighted under: + Amlal El Mahrouss + + Original author: + Apple Inc + +------------------------------------------- */ + +#pragma once + +#include + +/// @note Based of: +/// https://opensource.apple.com/source/cctools/cctools-750/as/ppc-opcode.h.auto.html + +#define kOpcodePPCCount (1073U) + +/* + * These defines are use in the cpus field of the instructions. If the field + * is zero it can execute on all cpus. The defines are or'ed together. This + * information is used to set the cpusubtype in the resulting object file. + */ +#define CPU601 0x1 +#define IMPL64 0x2 +#define OPTIONAL 0x4 +#define VMX 0x8 +#define CPU970 0x10 /* added to OPTIONAL insts that the 970 has */ +#define CPUMAHROUSS 0x12 /* optional mahrouss insts. */ + +enum OpcodeType { + NONE, /* no operand */ + JBSR, /* jbsr pseudo op */ + PCREL, /* PC relative (branch offset) */ + BADDR, /* Branch address (sign extended absolute address) */ + D, /* 16 bit displacement */ + DS, /* 14 bit displacement (double word) */ + SI, /* signed 16 bit immediate */ + UI, /* unsigned 16 bit immediate */ + HI, /* high 16 bit immediate (with truncation) */ + GREG, /* general register */ + G0REG, /* general register r1-r31 or 0 */ + FREG, /* float register */ + VREG, /* vector register */ + SGREG, /* segment register */ + SPREG, /* special register (or 10 bit number, 5 bit halves reversed) */ + BCND, /* branch condition opcode */ + CRF, /* condition register field */ + CRFONLY, /* condition register field only no expression allowed */ + sh, /* 6 bit number (0 - 63) (sh field, split and reversed) */ + mb, /* 6 bit number (0 - 63) (mb field, mb5 || mb0:4 reversed) */ + NUM, /* number */ + SNUM, /* signed number */ + NUM0, /* number (where 1< - -// @brief AMD64 support. -// @file Backend/amd64.hpp - -#define kAsmOpcodeDecl(__NAME, __OPCODE) {.fName = __NAME, .fOpcode = __OPCODE}, - -typedef char i64_character_t; -typedef uint8_t i64_byte_t; -typedef uint16_t i64_hword_t; -typedef uint32_t i64_word_t; - -#define kAsmRegisterPrefix "r" - -struct CpuOpcodeAMD64 { - std::string fName; - i64_byte_t fPrefixBytes[4]; - i64_hword_t fOpcode; - i64_hword_t fModReg; - i64_word_t fDisplacment; - i64_word_t fImmediate; -}; - -/// these two are edge cases -#define kAsmIntOpcode 0xCC -#define kasmIntOpcodeAlt 0xCD - -#define kAsmJumpOpcode 0x0F80 -#define kJumpLimit 30 -#define kJumpLimitStandard 0xE3 -#define kJumpLimitStandardLimit 0xEB - -inline std::vector kOpcodesAMD64 = { - kAsmOpcodeDecl("int", 0xCD) kAsmOpcodeDecl("into", 0xCE) kAsmOpcodeDecl("intd", 0xF1) - kAsmOpcodeDecl("int3", 0xC3) kAsmOpcodeDecl("iret", 0xCF) kAsmOpcodeDecl("retf", 0xCB) - kAsmOpcodeDecl("retn", 0xC3) kAsmOpcodeDecl("ret", 0xC3) kAsmOpcodeDecl("sti", 0xfb) - kAsmOpcodeDecl("cli", 0xfa) kAsmOpcodeDecl("hlt", 0xf4) kAsmOpcodeDecl("nop", 0x90) - kAsmOpcodeDecl("mov", 0x48) kAsmOpcodeDecl("call", 0xFF)}; - -#define kAsmRegisterLimit 16 diff --git a/dev/LibCompiler/Backend/arm64.h b/dev/LibCompiler/Backend/arm64.h deleted file mode 100644 index fb91a1c..0000000 --- a/dev/LibCompiler/Backend/arm64.h +++ /dev/null @@ -1,41 +0,0 @@ -/* ------------------------------------------- - -Copyright (C) 2024-2025 Amlal EL Mahrous, all rights reserved - -------------------------------------------- */ - -#pragma once - -#include -#include - -/// @brief ARM64 encoding support. -/// @file Backend/arm64.hpp - -struct CpuOpcodeArm64; - -/// @brief ARM64 opcode header. -struct PACKED CpuOpcodeArm64_Data final { - uint32_t fOpcode : 10; // Bits 31–22: Opcode for operation - uint32_t fRm : 5; // Bits 21–16: Source register Rm - uint32_t fShamt : 6; // Bits 15–10: Shift amount - uint32_t fRn : 5; // Bits 9–5: Source register Rn - uint32_t fRd : 5; // Bits 4–0: Destination register Rd -}; - -typedef struct { - uint32_t opcode : 6; // Bits 31–26: Branch opcode - int32_t offset : 26; // Bits 25–0: Signed offset (branch target) -} PACKED CpuOpcodeArm64_Branch; - -typedef struct { - uint32_t size : 2; // Bits 31–30: Size of the data - uint32_t opcode : 7; // Bits 29–23: Opcode for load/store - uint32_t offset : 12; // Bits 22–10: Offset - uint32_t rn : 5; // Bits 9–5: Base address register Rn - uint32_t rt : 5; // Bits 4–0: Target/source register Rt -} PACKED CpuOpcodeArm64_LoadStore; - -#define kAsmRegisterLimit (30) -#define kAsmRegisterPrefix "x" -#define kOpcodeARM64Count (1000) diff --git a/dev/LibCompiler/Backend/power64.h b/dev/LibCompiler/Backend/power64.h deleted file mode 100644 index 03aea49..0000000 --- a/dev/LibCompiler/Backend/power64.h +++ /dev/null @@ -1,1557 +0,0 @@ -/* ------------------------------------------- - - Some modifications are copyrighted under: - Amlal El Mahrouss - - Original author: - Apple Inc - -------------------------------------------- */ - -#pragma once - -#include - -/// @note Based of: -/// https://opensource.apple.com/source/cctools/cctools-750/as/ppc-opcode.h.auto.html - -#define kOpcodePPCCount (1073U) - -/* - * These defines are use in the cpus field of the instructions. If the field - * is zero it can execute on all cpus. The defines are or'ed together. This - * information is used to set the cpusubtype in the resulting object file. - */ -#define CPU601 0x1 -#define IMPL64 0x2 -#define OPTIONAL 0x4 -#define VMX 0x8 -#define CPU970 0x10 /* added to OPTIONAL insts that the 970 has */ -#define CPUMAHROUSS 0x12 /* optional mahrouss insts. */ - -enum OpcodeType { - NONE, /* no operand */ - JBSR, /* jbsr pseudo op */ - PCREL, /* PC relative (branch offset) */ - BADDR, /* Branch address (sign extended absolute address) */ - D, /* 16 bit displacement */ - DS, /* 14 bit displacement (double word) */ - SI, /* signed 16 bit immediate */ - UI, /* unsigned 16 bit immediate */ - HI, /* high 16 bit immediate (with truncation) */ - GREG, /* general register */ - G0REG, /* general register r1-r31 or 0 */ - FREG, /* float register */ - VREG, /* vector register */ - SGREG, /* segment register */ - SPREG, /* special register (or 10 bit number, 5 bit halves reversed) */ - BCND, /* branch condition opcode */ - CRF, /* condition register field */ - CRFONLY, /* condition register field only no expression allowed */ - sh, /* 6 bit number (0 - 63) (sh field, split and reversed) */ - mb, /* 6 bit number (0 - 63) (mb field, mb5 || mb0:4 reversed) */ - NUM, /* number */ - SNUM, /* signed number */ - NUM0, /* number (where 1<