From bbe2c77243c541ca7e0075149f5be3262eb89523 Mon Sep 17 00:00:00 2001 From: Amlal El Mahrouss Date: Mon, 24 Nov 2025 03:05:29 +0100 Subject: feat! breaking changes on necti sources. Signed-off-by: Amlal El Mahrouss --- src/CompilerKit/impl/Aarch64.h | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 src/CompilerKit/impl/Aarch64.h (limited to 'src/CompilerKit/impl/Aarch64.h') diff --git a/src/CompilerKit/impl/Aarch64.h b/src/CompilerKit/impl/Aarch64.h new file mode 100644 index 0000000..c1e9c77 --- /dev/null +++ b/src/CompilerKit/impl/Aarch64.h @@ -0,0 +1,41 @@ +/* ======================================== + +Copyright (C) 2024-2025 Amlal El Mahrouss, Licensed under the Apache 2.0 license + +======================================== */ + +#pragma once + +#include +#include + +/// @brief ARM64 encoding support. +/// @file impl/Aarch64.h + +struct CpuOpcodeArm64; + +/// @brief ARM64 opcode header. +struct PACKED CpuOpcodeArm64_Data final { + uint32_t fOpcode : 10; // Bits 31–22: Opcode for operation + uint32_t fRm : 5; // Bits 21–16: Source register Rm + uint32_t fShamt : 6; // Bits 15–10: Shift amount + uint32_t fRn : 5; // Bits 9–5: Source register Rn + uint32_t fRd : 5; // Bits 4–0: Destination register Rd +}; + +typedef struct { + uint32_t opcode : 6; // Bits 31–26: Branch opcode + int32_t offset : 26; // Bits 25–0: Signed offset (branch target) +} PACKED CpuOpcodeArm64_Branch; + +typedef struct { + uint32_t size : 2; // Bits 31–30: Size of the data + uint32_t opcode : 7; // Bits 29–23: Opcode for load/store + uint32_t offset : 12; // Bits 22–10: Offset + uint32_t rn : 5; // Bits 9–5: Base address register Rn + uint32_t rt : 5; // Bits 4–0: Target/source register Rt +} PACKED CpuOpcodeArm64_LoadStore; + +#define kAsmRegisterLimit (30) +#define kAsmRegisterPrefix "x" +#define kOpcodeARM64Count (1000) -- cgit v1.2.3