diff options
| -rwxr-xr-x | format.sh | 2 | ||||
| -rw-r--r-- | lib/30pin.h | 21 | ||||
| -rw-r--r-- | lib/boot.h | 52 | ||||
| -rw-r--r-- | lib/pci-tree.h | 14 | ||||
| -rw-r--r-- | lib/ppc64/mmu.h | 12 | ||||
| -rw-r--r-- | lib/ppc64/processor.h | 146 | ||||
| -rw-r--r-- | lib/xcoff.h | 13 | ||||
| -rw-r--r-- | libfdt/libfdt_env.h | 6 | ||||
| -rw-r--r-- | src/arm64/arm64-30pin.c | 2 | ||||
| -rw-r--r-- | src/arm64/arm64-err.c | 2 | ||||
| -rw-r--r-- | src/arm64/arm64-uart.c | 2 | ||||
| -rw-r--r-- | src/coreboot-ahci-driver.c | 14 | ||||
| -rw-r--r-- | src/coreboot-partition-map.c | 8 | ||||
| -rw-r--r-- | src/coreboot-pci-tree.c | 20 | ||||
| -rw-r--r-- | src/coreboot-start.c | 8 | ||||
| -rw-r--r-- | src/ppc64/ppc64-boot.S | 6 | ||||
| -rw-r--r-- | src/ppc64/ppc64-hal.c | 39 | ||||
| -rw-r--r-- | src/ppc64/ppc64-uart.c | 6 | ||||
| -rw-r--r-- | src/rv64/rv64-boot.s | 4 | ||||
| -rw-r--r-- | src/rv64/rv64-uart.c | 4 |
20 files changed, 202 insertions, 179 deletions
@@ -5,7 +5,7 @@ THIS_DIR="$(dirname "$THIS_PATH")" # Find all files in THIS_DIR which end in .ino, .cpp, etc., as specified # in the regular expression just below -FILE_LIST="$(find "$THIS_DIR" | grep -E ".*(\.ino|\.cpp|\.c|\.h|\.hpp|\.hxx|\.cxx|\.cc|\.hh)$")" +FILE_LIST="$(find "$THIS_DIR" | grep -E ".*(\.cc|\.c|\.h)$")" echo -e "Files found to format = \n\"\"\"\n$FILE_LIST\n\"\"\"" diff --git a/lib/30pin.h b/lib/30pin.h index f194b66..71d998d 100644 --- a/lib/30pin.h +++ b/lib/30pin.h @@ -6,12 +6,21 @@ #pragma once +#include <lib/boot.h> + /// @note This version is for the 30-pin recovery system. -struct TRB_PACKET +/// @brief 30pin recovery header. +/// @param mag magic number. +/// @param kind kind of packet we deal with. +/// @param buffer the data of the packet. +/// @param eop end of packet data. +struct _cb_tpin_recovery_packet { - char mag[2]; - char kind; - char buffer[498]; - char eop[11]; -};
\ No newline at end of file + uint8_t mag[2]; + uint8_t kind; + uint8_t buffer[498]; + uint8_t eop[11]; +}; + +typedef struct _cb_tpin_recovery_packet cb_tpin_recovery_packet_t;
\ No newline at end of file @@ -61,39 +61,39 @@ typedef ptrtype_t size_t; #define yes __yes #ifndef __cplusplus -#define bool boolean +#define bool boolean #define false no -#define true yes +#define true yes #endif //!_cplusplus -#define SYS_RESTART 0 -#define SYS_SHUTDOWN 1 +#define CB_RESTART 0 +#define CB_SHUTDOWN 1 #define __COPYRIGHT(s) /* unused */ #ifdef __COMPILE_RISCV__ -#define SYS_BOOT_ADDR (0x80020000) -#define SYS_BOOT_ADDR_STR "0x80020000" -#define SYS_FRAMEBUFFER_ADDR 0x40000000L -#define SYS_UART_BASE 0x10000000 -#define SYS_FLASH_BASE_ADDR 0x08000000 +#define CB_BOOT_ADDR (0x80020000) +#define CB_BOOT_ADDR_STR "0x80020000" +#define CB_FRAMEBUFFER_ADDR 0x40000000L +#define CB_UART_BASE 0x10000000 +#define CB_FLASH_BASE_ADDR 0x08000000 #define cb_sync_synchronize() __sync_synchronize() #elif defined(__COMPILE_POWERPC__) -#define SYS_UART_BASE 0x10000000 -#define SYS_BOOT_ADDR 0x1030000 -#define SYS_BOOT_ADDR_STR "0x1030000" -#define SYS_FRAMEBUFFER_ADDR 0x40000000L -#define SYS_FLASH_BASE_ADDR 0x08000000 +#define CB_UART_BASE 0x10000000 +#define CB_BOOT_ADDR 0x1030000 +#define CB_BOOT_ADDR_STR "0x1030000" +#define CB_FRAMEBUFFER_ADDR 0x40000000L +#define CB_FLASH_BASE_ADDR 0x08000000 #define cb_sync_synchronize() __sync_synchronize() #elif defined(__COMPILE_ARM64__) -#define SYS_UART_BASE 0x09000000 -#define SYS_BOOT_ADDR 0x1030000 -#define SYS_BOOT_ADDR_STR "0x1030000" -#define SYS_FRAMEBUFFER_ADDR 0x40000000L -#define SYS_FLASH_BASE_ADDR 0x08000000 +#define CB_UART_BASE 0x09000000 +#define CB_BOOT_ADDR 0x1030000 +#define CB_BOOT_ADDR_STR "0x1030000" +#define CB_FRAMEBUFFER_ADDR 0x40000000L +#define CB_FLASH_BASE_ADDR 0x08000000 static inline void __sync_synchronize(void) { @@ -103,20 +103,20 @@ static inline void __sync_synchronize(void) #define cb_sync_synchronize() __sync_synchronize() #endif // ifndef __COMPILE_POWERPC__ -#define SYS_BAUDRATE_TABLE \ +#define CB_BAUDRATE_TABLE \ { \ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 \ } -#define SYS_STRING(s) #s +#define CB_STRING(s) #s -#define SYS_BOOT_MAG_0 'C' -#define SYS_BOOT_MAG_1 'B' +#define CB_BOOT_MAG_0 'C' +#define CB_BOOT_MAG_1 'B' -#define SYS_BOOT_VER 0x101 +#define CB_BOOT_VER 0x101 -#define SYS_BOOT_CALL(struct, offset) \ - cb_proc_t proc_##offset = (cb_proc_t)(struct->offset); \ +#define CB_BOOT_CALL(struct, offset) \ + volatile cb_proc_t proc_##offset = (volatile cb_proc_t)(struct->offset); \ proc_##offset(); /// @brief floating point representation (IEE 7554) in a C structure diff --git a/lib/pci-tree.h b/lib/pci-tree.h index 3bd64d5..9b83da0 100644 --- a/lib/pci-tree.h +++ b/lib/pci-tree.h @@ -16,8 +16,8 @@ #define PCI_INVALID_DATA_U16 ((uint16_t)~0) #define PCI_INVALID_DATA_U32 ((uint32_t)~0) -#define SYS_BASE_ADDRESS (0x20008000) /* PCI base mapped in virtual memory. */ -#define SYS_PCI_TREE_BASE (0x802000) /* The PCI tree base address. */ +#define CB_BASE_ADDRESS (0x20008000) /* PCI base mapped in virtual memory. */ +#define CB_PCI_TREE_BASE (0x802000) /* The PCI tree base address. */ #define PCI_CONFIG_SPACE (4096U) @@ -26,12 +26,12 @@ #define PCI_FN_MAX (8U) /* version 1.0 */ -#define SYS_PCI_VERSION (0x0100) +#define CB_PCI_VERSION (0x0100) -#define SYS_PCI_DEV_MAGIC (0xfeedd00d) -#define SYS_PCI_INT_SZ sizeof(cb_pci_num_t) +#define CB_PCI_DEV_MAGIC (0xfeedd00d) +#define CB_PCI_INT_SZ sizeof(cb_pci_num_t) -#define SYS_PCI_NAME_LEN (255U) +#define CB_PCI_NAME_LEN (255U) typedef char cb_pci_char_t; typedef uintptr_t cb_pci_num_t; @@ -54,7 +54,7 @@ struct hw_cb_pci_tree cb_pci_num_t d_first_node; cb_pci_num_t d_next_sibling; - cb_pci_char_t d_name[SYS_PCI_NAME_LEN]; + cb_pci_char_t d_name[CB_PCI_NAME_LEN]; }; /// @brief Init PCI tree. diff --git a/lib/ppc64/mmu.h b/lib/ppc64/mmu.h index 206876e..d68fcf5 100644 --- a/lib/ppc64/mmu.h +++ b/lib/ppc64/mmu.h @@ -413,7 +413,7 @@ extern void print_bats(void); #define MAS0_TLBSEL(x) (((x) << 28) & MAS0_TLBSEL_MSK) #define MAS0_ESEL_MSK 0x0FFF0000 #define MAS0_ESEL(x) (((x) << 16) & MAS0_ESEL_MSK) -#define MAS0_NV(x) ((x) & 0x00000FFF) +#define MAS0_NV(x) ((x)&0x00000FFF) #define MAS1_VALID 0x80000000 #define MAS1_IPROT 0x40000000 @@ -470,9 +470,9 @@ extern void print_bats(void); (((ts) << 12) & MAS1_TS) | \ (MAS1_TSIZE(tsize))) #define FSL_BOOKE_MAS2(epn, wimge) \ - (((epn) & MAS3_RPN) | (wimge)) + (((epn)&MAS3_RPN) | (wimge)) #define FSL_BOOKE_MAS3(rpn, user, perms) \ - (((rpn) & MAS3_RPN) | (user) | (perms)) + (((rpn)&MAS3_RPN) | (user) | (perms)) #define FSL_BOOKE_MAS7(rpn) \ (((uint64_t)(rpn)) >> 32) @@ -640,10 +640,10 @@ extern int num_tlb_entries; /* Some handy macros */ -#define EPN(e) ((e) & 0xfffffc00) +#define EPN(e) ((e)&0xfffffc00) #define TLB0(epn, sz) ((EPN((epn)) | (sz) | TLB_VALID)) -#define TLB1(rpn, erpn) (((rpn) & 0xfffffc00) | (erpn)) -#define TLB2(a) ((a) & 0x00000fbf) +#define TLB1(rpn, erpn) (((rpn)&0xfffffc00) | (erpn)) +#define TLB2(a) ((a)&0x00000fbf) #define tlbtab_start \ mflr r1; \ diff --git a/lib/ppc64/processor.h b/lib/ppc64/processor.h index 02a6d8a..602ff08 100644 --- a/lib/ppc64/processor.h +++ b/lib/ppc64/processor.h @@ -141,36 +141,36 @@ struct pt_regs #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ #define DBCR_EDM 0x80000000 #define DBCR_IDM 0x40000000 -#define DBCR_RST(x) (((x) & 0x3) << 28) +#define DBCR_RST(x) (((x)&0x3) << 28) #define DBCR_RST_NONE 0 #define DBCR_RST_CORE 1 #define DBCR_RST_CHIP 2 #define DBCR_RST_SYSTEM 3 -#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ -#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ -#define DBCR_EDE 0x02000000 /* Exception Debug Event */ -#define DBCR_TDE 0x01000000 /* TRAP Debug Event */ -#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ -#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ -#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ -#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ -#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ -#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ -#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ +#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ +#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ +#define DBCR_EDE 0x02000000 /* Exception Debug Event */ +#define DBCR_TDE 0x01000000 /* TRAP Debug Event */ +#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ +#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ +#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ +#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ +#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ +#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ +#define DBCR_D1S(x) (((x)&0x3) << 12) /* Data Adrr. Compare 1 Size */ #define DAC_BYTE 0 #define DAC_HALF 1 #define DAC_WORD 2 #define DAC_QUAD 3 -#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ -#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ -#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ -#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ -#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ -#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ -#define DBCR_SIA 0x00000008 /* Second IAC Enable */ -#define DBCR_SDA 0x00000004 /* Second DAC Enable */ -#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ -#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ +#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ +#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ +#define DBCR_D2S(x) (((x)&0x3) << 8) /* Data Addr. Compare 2 Size */ +#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ +#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ +#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ +#define DBCR_SIA 0x00000008 /* Second IAC Enable */ +#define DBCR_SDA 0x00000004 /* Second DAC Enable */ +#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ +#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ #ifndef CONFIG_BOOKE #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ #else @@ -395,27 +395,27 @@ struct pt_regs #define TCR_WP(x) (((64 - x) & 0x3) << 30) | \ (((64 - x) & 0x3c) << 15) /* WDT Period 2^x clocks*/ #else -#define TCR_WP(x) (((x) & 0x3) << 30) /* WDT Period */ -#define WP_2_17 0 /* 2^17 clocks */ -#define WP_2_21 1 /* 2^21 clocks */ -#define WP_2_25 2 /* 2^25 clocks */ -#define WP_2_29 3 /* 2^29 clocks */ -#endif /* CONFIG_E500 */ -#define TCR_WRC(x) (((x) & 0x3) << 28) /* WDT Reset Control */ -#define WRC_NONE 0 /* No reset will occur */ -#define WRC_CORE 1 /* Core reset will occur */ -#define WRC_CHIP 2 /* Chip reset will occur */ -#define WRC_SYSTEM 3 /* System reset will occur */ -#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ -#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ -#define TCR_FP(x) (((x) & 0x3) << 24) /* FIT Period */ -#define FP_2_9 0 /* 2^9 clocks */ -#define FP_2_13 1 /* 2^13 clocks */ -#define FP_2_17 2 /* 2^17 clocks */ -#define FP_2_21 3 /* 2^21 clocks */ -#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ -#define TCR_ARE 0x00400000 /* Auto Reload Enable */ -#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ +#define TCR_WP(x) (((x)&0x3) << 30) /* WDT Period */ +#define WP_2_17 0 /* 2^17 clocks */ +#define WP_2_21 1 /* 2^21 clocks */ +#define WP_2_25 2 /* 2^25 clocks */ +#define WP_2_29 3 /* 2^29 clocks */ +#endif /* CONFIG_E500 */ +#define TCR_WRC(x) (((x)&0x3) << 28) /* WDT Reset Control */ +#define WRC_NONE 0 /* No reset will occur */ +#define WRC_CORE 1 /* Core reset will occur */ +#define WRC_CHIP 2 /* Chip reset will occur */ +#define WRC_SYSTEM 3 /* System reset will occur */ +#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ +#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ +#define TCR_FP(x) (((x)&0x3) << 24) /* FIT Period */ +#define FP_2_9 0 /* 2^9 clocks */ +#define FP_2_13 1 /* 2^13 clocks */ +#define FP_2_17 2 /* 2^17 clocks */ +#define FP_2_21 3 /* 2^21 clocks */ +#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ +#define TCR_ARE 0x00400000 /* Auto Reload Enable */ +#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ #define THRM1_TIN (1 << 0) #define THRM1_TIV (1 << 1) #define THRM1_THRES (0x7f << 2) @@ -429,26 +429,26 @@ struct pt_regs #ifndef CONFIG_BOOKE #define SPRN_TSR 0x3D8 /* Timer Status Register */ #else -#define SPRN_TSR 0x150 /* Book E Timer Status Register */ -#endif /* CONFIG_BOOKE */ -#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ -#define TSR_WIS 0x40000000 /* WDT Interrupt Status */ -#define TSR_WRS(x) (((x) & 0x3) << 28) /* WDT Reset Status */ -#define WRS_NONE 0 /* No WDT reset occurred */ -#define WRS_CORE 1 /* WDT forced core reset */ -#define WRS_CHIP 2 /* WDT forced chip reset */ -#define WRS_SYSTEM 3 /* WDT forced system reset */ -#define TSR_PIS 0x08000000 /* PIT Interrupt Status */ -#define TSR_FIS 0x04000000 /* FIT Interrupt Status */ -#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ -#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ -#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ -#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ -#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ -#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ -#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ -#define SPRN_XER 0x001 /* Fixed Point Exception Register */ -#define SPRN_ZPR 0x3B0 /* Zone Protection Register */ +#define SPRN_TSR 0x150 /* Book E Timer Status Register */ +#endif /* CONFIG_BOOKE */ +#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ +#define TSR_WIS 0x40000000 /* WDT Interrupt Status */ +#define TSR_WRS(x) (((x)&0x3) << 28) /* WDT Reset Status */ +#define WRS_NONE 0 /* No WDT reset occurred */ +#define WRS_CORE 1 /* WDT forced core reset */ +#define WRS_CHIP 2 /* WDT forced chip reset */ +#define WRS_SYSTEM 3 /* WDT forced system reset */ +#define TSR_PIS 0x08000000 /* PIT Interrupt Status */ +#define TSR_FIS 0x04000000 /* FIT Interrupt Status */ +#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ +#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ +#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ +#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ +#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ +#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ +#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ +#define SPRN_XER 0x001 /* Fixed Point Exception Register */ +#define SPRN_ZPR 0x3B0 /* Zone Protection Register */ /* Book E definitions */ #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ @@ -853,7 +853,7 @@ struct pt_regs #define IOCR_PTD 0x00000400 #define IOCR_ARE 0x00000080 #define IOCR_DRC 0x00000020 -#define IOCR_RDM(x) (((x) & 0x3) << 3) +#define IOCR_RDM(x) (((x)&0x3) << 3) #define IOCR_TCS 0x00000004 #define IOCR_SCS 0x00000002 #define IOCR_SPC 0x00000001 @@ -1022,29 +1022,29 @@ struct pt_regs /* * 405EX/EXr CHIP_21 Errata */ -#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY -#define CONFIG_SYS_4xx_CHIP_21_ERRATA +#ifdef CONFIG_CB_4xx_CHIP_21_405EX_SECURITY +#define CONFIG_CB_4xx_CHIP_21_ERRATA #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX1_RC #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX1_RD #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x0 #endif -#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY -#define CONFIG_SYS_4xx_CHIP_21_ERRATA +#ifdef CONFIG_CB_4xx_CHIP_21_405EX_NO_SECURITY +#define CONFIG_CB_4xx_CHIP_21_ERRATA #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX2_RC #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX2_RD #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x1 #endif -#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY -#define CONFIG_SYS_4xx_CHIP_21_ERRATA +#ifdef CONFIG_CB_4xx_CHIP_21_405EXr_SECURITY +#define CONFIG_CB_4xx_CHIP_21_ERRATA #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR1_RC #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR1_RD #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x2 #endif -#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY -#define CONFIG_SYS_4xx_CHIP_21_ERRATA +#ifdef CONFIG_CB_4xx_CHIP_21_405EXr_NO_SECURITY +#define CONFIG_CB_4xx_CHIP_21_ERRATA #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR2_RC #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR2_RD #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x3 @@ -1252,7 +1252,7 @@ int fsl_qoriq_dsp_core_to_cluster(unsigned int core); #if defined(CONFIG_MPC83xx) #define CPU_TYPE_ENTRY(x) \ { \ - #x, SPR_##x \ +#x, SPR_##x \ } #endif #endif diff --git a/lib/xcoff.h b/lib/xcoff.h index 03223ef..ed19029 100644 --- a/lib/xcoff.h +++ b/lib/xcoff.h @@ -18,6 +18,8 @@ #define XCOFF_MAG 0x01F7 +#define XCOFF_NAME_LEN 256U + #define XCOFF_REL_FLG 0x0001 #define XCOFF_EXEC_FLG 0x0002 #define XCOFF_LNNO_FLG 0x0004 @@ -35,6 +37,17 @@ typedef struct _xcoff_header uint16_t opthdr; // ?: Number of bytes in optional header } xcoff_header_t; +/// @brief This the executable's manifest fork, designed for NeFS. +/// @param prop_xml_fork The XML fork of the executable. +/// @param dyld_fork The DYLD fork metadata. +/// @param code_sign_fork Executable's certificate contained in a fork. +typedef struct _xcoff_fork_header +{ + char prop_xml_fork[XCOFF_NAME_LEN]; + char dyld_fork[XCOFF_NAME_LEN]; + char code_sign_fork[XCOFF_NAME_LEN]; +} xcoff_fork_header_t; + typedef xcoff_header_t xcoff_header64_t; typedef xcoff_header_t xcoff_header32_t; diff --git a/libfdt/libfdt_env.h b/libfdt/libfdt_env.h index 9720afc..bc8f389 100644 --- a/libfdt/libfdt_env.h +++ b/libfdt/libfdt_env.h @@ -4,8 +4,8 @@ ------------------------------------------- */ -#ifndef __SYS_FDT_H__ -#define __SYS_FDT_H__ +#ifndef __CB_FDT_H__ +#define __CB_FDT_H__ #include <lib/boot.h> @@ -65,4 +65,4 @@ static inline fdt64_t cpu_to_fdt64(uint64_t x) #undef CPU_TO_FDT16 #undef EXTRACT_BYTE -#endif //!__SYS_FDT_H__ +#endif //!__CB_FDT_H__ diff --git a/src/arm64/arm64-30pin.c b/src/arm64/arm64-30pin.c index 427b078..f347f0d 100644 --- a/src/arm64/arm64-30pin.c +++ b/src/arm64/arm64-30pin.c @@ -7,4 +7,4 @@ #include <lib/partition-map.h> #include <lib/30pin.h> -extern size_t cb_send_read_30pin(voidptr_t blob, size_t* size, size_t* start_lba); +extern size_t cb_read_30pin(voidptr_t blob, size_t* size, size_t* start_lba); diff --git a/src/arm64/arm64-err.c b/src/arm64/arm64-err.c index 045a58e..052b302 100644 --- a/src/arm64/arm64-err.c +++ b/src/arm64/arm64-err.c @@ -12,7 +12,7 @@ /// @param reason why? void cb_panic(const char* reason) { - cb_put_string("Error: "); + cb_put_string("panic: "); cb_put_string(reason); cb_put_char('\n'); diff --git a/src/arm64/arm64-uart.c b/src/arm64/arm64-uart.c index 1fdb550..362fc24 100644 --- a/src/arm64/arm64-uart.c +++ b/src/arm64/arm64-uart.c @@ -13,7 +13,7 @@ /* this file handles the UART */ -static uint32_t* cb_uart_ptr = (uint32_t*)SYS_UART_BASE; +static uint32_t* cb_uart_ptr = (uint32_t*)CB_UART_BASE; // we need that one, to avoid sending mutliple chars to UART. static boolean cb_locked_put_char = no; diff --git a/src/coreboot-ahci-driver.c b/src/coreboot-ahci-driver.c index 1f368d4..2ef2098 100644 --- a/src/coreboot-ahci-driver.c +++ b/src/coreboot-ahci-driver.c @@ -18,7 +18,7 @@ #include <lib/pci-tree.h> #include <lib/boot.h> -#define SYS_AHCI_DRIVER_NAME ("@sata") +#define CB_AHCI_DRIVER_NAME ("@sata") /// BUGS: 0 /// @brief AHCI support for PowerPC. @@ -49,7 +49,7 @@ typedef struct cb_hba_port /// @brief Check if port is active. /// @param port host bus address port. -/// @return +/// @return whether sact is active or not. static boolean cb_hba_port_active(volatile cb_hba_port_t* port) { if (!port) @@ -58,9 +58,9 @@ static boolean cb_hba_port_active(volatile cb_hba_port_t* port) return port->sact; } -/// @brief Start HBA command. +/// @brief Start HBA command processor. /// @param port host bus address port. -/// @return +/// @return whether it was successful or not. static boolean cb_hba_start_cmd(volatile cb_hba_port_t* port) { if (!port) @@ -82,9 +82,9 @@ static boolean cb_hba_start_cmd(volatile cb_hba_port_t* port) return true; } -/// @brief Stop HBA command. +/// @brief Stop HBA command from processing. /// @param port host bus address port. -/// @return +/// @return whether it was successful or not. static boolean cb_hba_stop_cmd(volatile cb_hba_port_t* port) { if (!port) @@ -93,7 +93,7 @@ static boolean cb_hba_stop_cmd(volatile cb_hba_port_t* port) port->cmd &= ~0x0001; port->cmd &= ~0x0010; - while (1) + while (yes) { if ((port->cmd & 0x8000)) continue; diff --git a/src/coreboot-partition-map.c b/src/coreboot-partition-map.c index 40c3ff0..69bcddd 100644 --- a/src/coreboot-partition-map.c +++ b/src/coreboot-partition-map.c @@ -9,8 +9,8 @@ // include this for documentation. -#define MP_FILESYSTEM_COUNT 4 -#define MP_FILESYSTEM_LIST \ +#define CB_FILESYSTEM_COUNT 4 +#define CB_FILESYSTEM_LIST \ { \ "NeFS", "HeFS", "FAT32", "ext4" \ } @@ -23,9 +23,9 @@ boolean cb_filesystem_exists(caddr_t fs, size_t len) *fs == 0) return no; - char* fs_list[] = MP_FILESYSTEM_LIST; + char* fs_list[] = CB_FILESYSTEM_LIST; - for (size_t fs_index = 0; fs_index < MP_FILESYSTEM_COUNT; fs_index++) + for (size_t fs_index = 0; fs_index < CB_FILESYSTEM_COUNT; fs_index++) { if (strncmp(fs_list[fs_index], fs, strlen(fs_list[fs_index])) == 0) { diff --git a/src/coreboot-pci-tree.c b/src/coreboot-pci-tree.c index 65e4b77..b39c024 100644 --- a/src/coreboot-pci-tree.c +++ b/src/coreboot-pci-tree.c @@ -21,7 +21,7 @@ /// BUGS: 0 /// Standard Root table (Mahrouss Table) -#define SYS_PCI_ROOT_NAME "/pci-tree/@/" +#define CB_PCI_ROOT_NAME "/pci-tree/@/" static struct hw_cb_pci_tree* cb_base_tree = nil; static struct hw_cb_pci_tree* cb_latest_tree = nil; @@ -32,27 +32,27 @@ static struct hw_cb_pci_tree* cb_last_tree = nil; /// Otherwise true. boolean cb_pci_init_tree(void) { - cb_base_tree = (struct hw_cb_pci_tree*)(SYS_PCI_TREE_BASE); + cb_base_tree = (struct hw_cb_pci_tree*)(CB_PCI_TREE_BASE); // huh? anyway let's ignore it then. - if (cb_base_tree->d_magic != SYS_PCI_DEV_MAGIC) + if (cb_base_tree->d_magic != CB_PCI_DEV_MAGIC) { - cb_base_tree->d_magic = SYS_PCI_DEV_MAGIC; + cb_base_tree->d_magic = CB_PCI_DEV_MAGIC; - memncpy(cb_base_tree->d_name, SYS_PCI_ROOT_NAME, strlen(SYS_PCI_ROOT_NAME)); + memncpy(cb_base_tree->d_name, CB_PCI_ROOT_NAME, strlen(CB_PCI_ROOT_NAME)); cb_base_tree->d_next_sibling = 0; cb_base_tree->d_off_props = 0; cb_base_tree->d_sz_struct = 0; cb_base_tree->d_sz_props = 0; cb_base_tree->d_off_struct = 0; - cb_base_tree->d_version = SYS_PCI_VERSION; + cb_base_tree->d_version = CB_PCI_VERSION; cb_base_tree->d_next_sibling = (cb_pci_num_t)(cb_base_tree + sizeof(struct hw_cb_pci_tree)); cb_base_tree->d_first_node = (cb_pci_num_t)cb_base_tree; - cb_put_string(">> Append root device: " SYS_PCI_ROOT_NAME "\r\n"); + cb_put_string(">> Append root device: " CB_PCI_ROOT_NAME "\r\n"); } cb_latest_tree = cb_base_tree; @@ -71,7 +71,7 @@ boolean cb_pci_append_tree(const caddr_t name, cb_pci_num_t struct_ptr, cb_pci_n struct hw_cb_pci_tree* cb_pci_tree = (struct hw_cb_pci_tree*)(cb_latest_tree); - while (cb_pci_tree->d_magic == SYS_PCI_DEV_MAGIC) + while (cb_pci_tree->d_magic == CB_PCI_DEV_MAGIC) { if (strcmp(cb_pci_tree->d_name, name) == 0) return no; @@ -81,7 +81,7 @@ boolean cb_pci_append_tree(const caddr_t name, cb_pci_num_t struct_ptr, cb_pci_n sizeof(struct hw_cb_pci_tree)); } - cb_pci_tree->d_magic = SYS_PCI_DEV_MAGIC; + cb_pci_tree->d_magic = CB_PCI_DEV_MAGIC; memncpy(cb_pci_tree->d_name, name, strlen(name)); @@ -89,7 +89,7 @@ boolean cb_pci_append_tree(const caddr_t name, cb_pci_num_t struct_ptr, cb_pci_n cb_pci_tree->d_sz_struct = struct_sz; cb_pci_tree->d_off_props = 0; cb_pci_tree->d_sz_props = 0; - cb_pci_tree->d_version = SYS_PCI_VERSION; + cb_pci_tree->d_version = CB_PCI_VERSION; cb_pci_tree->d_next_sibling = (cb_pci_num_t)(cb_pci_tree + sizeof(struct hw_cb_pci_tree)); diff --git a/src/coreboot-start.c b/src/coreboot-start.c index a4e1efc..21ee5b0 100644 --- a/src/coreboot-start.c +++ b/src/coreboot-start.c @@ -74,7 +74,7 @@ void cb_start_exec(void) /// @brief Boots here if LX header matches what we except. volatile struct cb_boot_header* boot_hdr = - (volatile struct cb_boot_header*)(SYS_FLASH_BASE_ADDR); + (volatile struct cb_boot_header*)(CB_FLASH_BASE_ADDR); /** boot if: @@ -82,10 +82,10 @@ void cb_start_exec(void) - version matches. */ - if (boot_hdr->h_mag[0] == SYS_BOOT_MAG_0 && - boot_hdr->h_mag[1] == SYS_BOOT_MAG_1) + if (boot_hdr->h_mag[0] == CB_BOOT_MAG_0 && + boot_hdr->h_mag[1] == CB_BOOT_MAG_1) { - if (boot_hdr->h_revision != SYS_BOOT_VER) + if (boot_hdr->h_revision != CB_BOOT_VER) { if (hart == 1) { diff --git a/src/ppc64/ppc64-boot.S b/src/ppc64/ppc64-boot.S index 17d6fa5..28d1865 100644 --- a/src/ppc64/ppc64-boot.S +++ b/src/ppc64/ppc64-boot.S @@ -29,11 +29,11 @@ cb_reset_vector: .global cb_start_context
.global cb_boot_processor_ready
-.equ SYS_BOOT_ADDR, 0x1030000
+.equ CB_BOOT_ADDR, 0x1030000
cb_start_rom:
- lis 3, SYS_BOOT_ADDR@h
- addi 3, 3, SYS_BOOT_ADDR@l
+ lis 3, CB_BOOT_ADDR@h
+ addi 3, 3, CB_BOOT_ADDR@l
blr
diff --git a/src/ppc64/ppc64-hal.c b/src/ppc64/ppc64-hal.c index 53e16d2..f47f0b3 100644 --- a/src/ppc64/ppc64-hal.c +++ b/src/ppc64/ppc64-hal.c @@ -36,6 +36,7 @@ void cb_set_tlb(uint8_t tlb, // this mmu-version does not allow odd tsize values
return;
}
+
uint32_t mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
uint32_t mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
uint32_t mas2 = FSL_BOOKE_MAS2(epn, wimge);
@@ -52,18 +53,18 @@ void cb_init_hw(void) /// amlal:
/// map VGA framebuffer
- cb_set_tlb(0, SYS_FRAMEBUFFER_ADDR, /* v_addr, 0x0000A0000 */
- 0x0000A000, /* p_addr. 0x0000A0000 */
- MAS3_SW | MAS3_SR, /* perm type=TLB_MAP_IO */
- MAS2_I | MAS2_G, /* wimge type=TLB_MAP_IO */
- 0, /* ts i.e AS=0 */
- 1, /* esel (a.k.a tlb_index*/
- BOOKE_PAGESZ_64K, /* tsize ie 2^10kB ie 1MB */
+ cb_set_tlb(0, CB_FRAMEBUFFER_ADDR, /* v_addr, 0x0000A0000 */
+ 0x0000A000, /* p_addr. 0x0000A0000 */
+ MAS3_SW | MAS3_SR, /* perm type=TLB_MAP_IO */
+ MAS2_I | MAS2_G, /* wimge type=TLB_MAP_IO */
+ 0, /* ts i.e AS=0 */
+ 1, /* esel (a.k.a tlb_index*/
+ BOOKE_PAGESZ_64K, /* tsize ie 2^10kB ie 1MB */
1);
// map ccsrbar and uart.
// at start we execute from esel = 0, so chose something else..
- cb_set_tlb(1, SYS_UART_BASE, /* v_addr 0xe0000000 see qemu-ppce500.h */
+ cb_set_tlb(1, CB_UART_BASE, /* v_addr 0xe0000000 see qemu-ppce500.h */
0xfe0000000, /* p_addr. 0xfe0000000 */
MAS3_SW | MAS3_SR, /* perm type=TLB_MAP_IO */
MAS2_I | MAS2_G, /* wimge type=TLB_MAP_IO */
@@ -74,21 +75,21 @@ void cb_init_hw(void) /// amlal:
/// map pci base for kernel
- cb_set_tlb(0, SYS_BASE_ADDRESS, /* v_addr, 0xFE008000 */
- 0xFE0008000, /* p_addr. 0xfe0000000 */
- MAS3_SW | MAS3_SR, /* perm type=TLB_MAP_IO */
- MAS2_I | MAS2_G, /* wimge type=TLB_MAP_IO */
- 0, /* ts i.e AS=0 */
- 3, /* esel (a.k.a tlb_index*/
- BOOKE_PAGESZ_1M, /* tsize ie 2^10kB ie 1MB */
+ cb_set_tlb(0, CB_BASE_ADDRESS, /* v_addr, 0xFE008000 */
+ 0xFE0008000, /* p_addr. 0xfe0000000 */
+ MAS3_SW | MAS3_SR, /* perm type=TLB_MAP_IO */
+ MAS2_I | MAS2_G, /* wimge type=TLB_MAP_IO */
+ 0, /* ts i.e AS=0 */
+ 3, /* esel (a.k.a tlb_index*/
+ BOOKE_PAGESZ_1M, /* tsize ie 2^10kB ie 1MB */
1);
cb_pci_init_tree();
- cb_pci_append_tree("@fb", SYS_FRAMEBUFFER_ADDR, 0x0);
- cb_pci_append_tree("@mbci", 0x0, 0x0);
- cb_pci_append_tree("@serial", SYS_UART_BASE, 0);
- cb_pci_append_tree("@pci", SYS_BASE_ADDRESS, 0x0);
+ cb_pci_append_tree("@fb", CB_FRAMEBUFFER_ADDR, 0x0);
+ cb_pci_append_tree("@mbci", 0x0, 0x0); // did not found a MBCI base for now...
+ cb_pci_append_tree("@serial", CB_UART_BASE, 0);
+ cb_pci_append_tree("@pci", CB_BASE_ADDRESS, 0x0);
cb_flush_tlb();
}
diff --git a/src/ppc64/ppc64-uart.c b/src/ppc64/ppc64-uart.c index 0a01857..c908eae 100644 --- a/src/ppc64/ppc64-uart.c +++ b/src/ppc64/ppc64-uart.c @@ -9,10 +9,10 @@ /// BUGS: 0
-#define SYS_NS16550_COM1 (SYS_UART_BASE + 0x4500)
-#define SYS_NS16550_COM2 (SYS_UART_BASE + 0x4600)
+#define CB_NS16550_COM1 (CB_UART_BASE + 0x4500)
+#define CB_NS16550_COM2 (CB_UART_BASE + 0x4600)
-volatile ascii_char_t* const UART0DR = (ascii_char_t*)SYS_NS16550_COM1;
+volatile ascii_char_t* const UART0DR = (ascii_char_t*)CB_NS16550_COM1;
/* this file handles the UART */
diff --git a/src/rv64/rv64-boot.s b/src/rv64/rv64-boot.s index ae975da..fb95d55 100644 --- a/src/rv64/rv64-boot.s +++ b/src/rv64/rv64-boot.s @@ -81,10 +81,10 @@ cb_start_context: add ra, zero, a1 mret -.equ SYS_BOOT_ADDR, 0x80020000 +.equ CB_BOOT_ADDR, 0x80020000 cb_start_rom: - li x5, SYS_BOOT_ADDR + li x5, CB_BOOT_ADDR mv ra, zero add ra, zero, t0 mret diff --git a/src/rv64/rv64-uart.c b/src/rv64/rv64-uart.c index 4c96178..73964ef 100644 --- a/src/rv64/rv64-uart.c +++ b/src/rv64/rv64-uart.c @@ -11,11 +11,11 @@ /* this file handles the UART */ -static uint8_t* cb_uart_ptr = (uint8_t*)SYS_UART_BASE; +static uint8_t* cb_uart_ptr = (uint8_t*)CB_UART_BASE; utf_char_t cb_get_char(void) { - uintptr_t ptr = SYS_UART_BASE; + uintptr_t ptr = CB_UART_BASE; while (!(*(((volatile uint8_t*)ptr) + 0x05) & 0x01)) ; |