git: port from mercurial repo.

Signed-off-by: Amlal El Mahrouss <amlal.elmahrouss@icloud.com>

50 files changed, 1649 insertions, 0 deletions

diff --git a/HALKit/.gitkeep b/HALKit/.gitkeep
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/HALKit/.gitkeep
diff --git a/HALKit/AMD64/ACPI/ACPI.hpp b/HALKit/AMD64/ACPI/ACPI.hpp
new file mode 100644
index 00000000..9c000409
--- /dev/null
+++ b/HALKit/AMD64/ACPI/ACPI.hpp
@@ -0,0 +1,72 @@
+/*
+ *	========================================================
+ *
+ *	hCore 	Date Added: 13/02/2023
+ * 	Copyright XPX Corp, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#ifndef _INC_ACPI_MANAGER_H
+#define _INC_ACPI_MANAGER_H
+
+#include <NewKit/Defines.hpp>
+
+namespace hCore {
+    class SDT {
+    public:
+        Char Signature[4];
+        UInt32 Length;
+        UInt8 Revision;
+        Char Checksum;
+        Char OemId[6];
+        Char OemTableId[8];
+        UInt32 OemRev;
+        UInt32 CreatorID;
+        UInt32 CreatorRevision;
+    };
+
+    class RSDP : public SDT
+    {
+    public:
+        UInt32 RsdtAddress;
+        UIntPtr XsdtAddress;
+        UInt8 ExtendedChecksum;
+        UInt8 Reserved0[3];
+
+    };
+
+    class ConfigHeader
+    {
+    public:
+        UInt64 BaseAddress;
+        UInt16 PciSegGroup;
+        UInt8 StartBus;
+        UInt8 EndBus;
+        UInt32 Reserved;
+
+    };
+
+    enum class AddressSpace : UInt8
+    {
+        SystemMemory = 0,
+        SystemIO = 1,
+        Pci = 2,
+        Controller = 3,
+        SmBus = 4,
+        Invalid = 0xFF,
+    };
+
+    class Address
+    {
+    public:
+        AddressSpace AddressSpaceId;
+        UInt8 RegisterBitWidth;
+        UInt8 RegisterBitOffset;
+        UInt8 Reserved;
+        UIntPtr Address;
+
+    };
+} // namespace hCore
+
+#endif // !_INC_ACPI_MANAGER_H
diff --git a/HALKit/AMD64/ACPI/ACPIManager.hpp b/HALKit/AMD64/ACPI/ACPIManager.hpp
new file mode 100644
index 00000000..d8cf6bcf
--- /dev/null
+++ b/HALKit/AMD64/ACPI/ACPIManager.hpp
@@ -0,0 +1,52 @@
+/*
+ *	========================================================
+ *
+ *	hCore 	Date Added: 20/02/2023
+ * 	Copyright XPX Corp, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#ifndef _INC_ACPI_H
+#define _INC_ACPI_H
+
+#include <HALKit/AMD64/ACPI/ACPI.hpp>
+#include <KernelKit/DebugOutput.hpp>
+#include <NewKit/Defines.hpp>
+#include <NewKit/Ref.hpp>
+
+namespace hCore
+{
+    class ACPIManager
+    {
+    public:
+        ACPIManager(voidPtr rsdptr);
+
+    public:
+        ~ACPIManager() = default;
+
+        ACPIManager &operator=(const ACPIManager &) = default;
+
+        ACPIManager(const ACPIManager &) = default;
+
+    public:
+        void Shutdown(); // shutdown
+        void Reset();    // soft-reboot
+
+        ErrorOr <voidPtr> Find(const char *signature);
+
+        bool Checksum(const char *checksum, SSizeT len); // watch for collides!
+
+    public:
+        ErrorOr <voidPtr> operator[](const char *signature) {
+            return this->Find(signature);
+        }
+
+    private:
+        VoidPtr m_Rsdp;   // pointer to root descriptor.
+        SSizeT m_Entries; // number of entries, -1 tells that no invalid entries were found.
+
+    };
+} // namespace hCore
+
+#endif // !_INC_ACPI_H
diff --git a/HALKit/AMD64/ACPIManagerAMD64.cpp b/HALKit/AMD64/ACPIManagerAMD64.cpp
new file mode 100644
index 00000000..735726ec
--- /dev/null
+++ b/HALKit/AMD64/ACPIManagerAMD64.cpp
@@ -0,0 +1,87 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#include <HALKit/AMD64/ACPI/ACPIManager.hpp>
+#include <NewKit/String.hpp>
+
+#include <HALKit/AMD64/Processor.hpp>
+
+namespace hCore
+{
+    ACPIManager::ACPIManager(voidPtr rsdPtr)
+        : m_Rsdp(rsdPtr), m_Entries(0)
+    {
+        RSDP* _rsdPtr = reinterpret_cast<RSDP*>(this->m_Rsdp);
+
+        MUST_PASS(_rsdPtr);
+        MUST_PASS(_rsdPtr->Revision >= 2);
+    }
+
+    void ACPIManager::Shutdown() {}
+    void ACPIManager::Reset() {}
+
+    ErrorOr <voidPtr> ACPIManager::Find(const char *signature)
+    {
+        MUST_PASS(m_Rsdp);
+
+        if (!signature)
+            return ErrorOr<voidPtr>{-2};
+
+        if (*signature == 0)
+            return ErrorOr<voidPtr>{-3};
+
+        RSDP *rsdPtr = reinterpret_cast<RSDP*>(this->m_Rsdp);
+
+        auto xsdt = rsdPtr->XsdtAddress;
+        SizeT num = (rsdPtr->Length + sizeof(SDT)) / 8;
+
+        for (Size index = 0; index < num; ++index)
+        {
+            SDT *sdt = reinterpret_cast<SDT*>(xsdt + sizeof(SDT) + index * 8);
+
+            if (!Checksum(sdt->Signature, 4))
+                panic(RUNTIME_CHECK_ACPI);
+
+            if (StringBuilder::Equals(const_cast<const char*>(sdt->Signature), signature))
+                return ErrorOr<voidPtr>(reinterpret_cast<voidPtr>(sdt));
+        }
+
+        return ErrorOr<voidPtr>{-1};
+    }
+
+    bool ACPIManager::Checksum(const char *checksum, SSizeT len)
+    {
+        if (len == 0)
+            return -1;
+
+        char chr = 0;
+
+        for (int index = 0; index < len; ++index)
+        {
+            chr += checksum[index];
+        }
+
+        return chr == 0;
+    }
+
+    void rt_shutdown_acpi_qemu_20(void)
+    {
+        HAL::out16(0xb004, 0x2000);
+    }
+
+    void rt_shutdown_acpi_qemu_30_plus(void)
+    {
+        HAL::out16(0x604, 0x2000);
+    }
+
+    void rt_shutdown_acpi_virtualbox(void)
+    {
+        HAL::out16(0x4004, 0x3400);
+    }
+} // namespace hCore
diff --git a/HALKit/AMD64/ArchAMD64.cpp b/HALKit/AMD64/ArchAMD64.cpp
new file mode 100644
index 00000000..c069ba9c
--- /dev/null
+++ b/HALKit/AMD64/ArchAMD64.cpp
@@ -0,0 +1,55 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#include <ArchKit/Arch.hpp>
+
+namespace hCore::HAL
+{
+    struct RegisterAMD64
+    {
+        UIntPtr base;
+        UShort limit;
+    };
+
+    void GDTLoader::Load(Register64 &gdt)
+    {
+        RegisterAMD64* reg = new RegisterAMD64();
+        MUST_PASS(reg);
+
+        reg->base = gdt.Base;
+        reg->limit = gdt.Limit;
+
+        rt_cli();
+        load_gdt(reg);
+        rt_sti();
+    }
+
+    void IDTLoader::Load(Register64 &idt)
+    {
+        RegisterAMD64* reg = new RegisterAMD64();
+        MUST_PASS(reg);
+
+        reg->base = idt.Base;
+        reg->limit = idt.Limit;
+
+        rt_cli();
+        load_idt(reg);
+        rt_sti();
+    }
+
+    void GDTLoader::Load(Ref<Register64> &gdt)
+    {
+        GDTLoader::Load(gdt.Leak());
+    }
+
+    void IDTLoader::Load(Ref<Register64> &idt)
+    {
+        IDTLoader::Load(idt.Leak());
+    }
+} // namespace hCore::HAL
diff --git a/HALKit/AMD64/ControlRegister.s b/HALKit/AMD64/ControlRegister.s
new file mode 100644
index 00000000..d7e0c019
--- /dev/null
+++ b/HALKit/AMD64/ControlRegister.s
@@ -0,0 +1,35 @@
+.globl write_cr3
+.globl write_cr0
+.globl read_cr2
+.globl read_cr3
+.globl read_cr0
+.globl flush_tlb
+
+.section .text
+    flush_tlb:
+        mov %rsi, %cr3
+        mov %cr3, %rsi
+        xor %rax, %rax
+        ret
+
+    read_cr3:
+        movq %rax, %cr3
+        ret
+
+    read_cr0:
+        movq %rax, %cr0
+        ret
+
+    read_cr2:
+        movq %rax, %cr2
+        ret
+
+    write_cr3:
+        movq %cr3, %rdi
+        ret
+
+    write_cr0:
+        movq %cr0, %rdi
+        ret
+
+
diff --git a/HALKit/AMD64/CoreInterruptHandlerAMD64.cpp b/HALKit/AMD64/CoreInterruptHandlerAMD64.cpp
new file mode 100644
index 00000000..4e93d990
--- /dev/null
+++ b/HALKit/AMD64/CoreInterruptHandlerAMD64.cpp
@@ -0,0 +1,82 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#include <ArchKit/Arch.hpp>
+#include <NewKit/String.hpp>
+#include <KernelKit/ProcessManager.hpp>
+
+extern "C" void idt_handle_system_call(hCore::UIntPtr rsp)
+{
+    hCore::HAL::StackFrame *sf = reinterpret_cast<hCore::HAL::StackFrame*>(rsp);
+    rt_syscall_handle(sf);
+
+    hCore::kcout << "System Call with ID: " << hCore::StringBuilder::FromInt("syscall{%}", sf->SID);
+}
+
+extern "C" void idt_handle_gpf(hCore::UIntPtr rsp)
+{
+    MUST_PASS(hCore::ProcessManager::Shared().Leak().GetCurrent());
+
+    hCore::kcout << hCore::StringBuilder::FromInt("sp{%}", rsp);
+
+    hCore::kcout << "General Protection Fault, Caused by "
+                   << hCore::ProcessManager::Shared().Leak().GetCurrent().Leak().GetName();
+
+    hCore::ProcessManager::Shared().Leak().GetCurrent().Leak().Crash();
+}
+
+extern "C" void idt_handle_scheduler(hCore::UIntPtr rsp)
+{
+    hCore::kcout << hCore::StringBuilder::FromInt("sp{%}", rsp);
+
+    hCore::kcout << "Will be scheduled back later "
+                   << hCore::ProcessManager::Shared().Leak().GetCurrent().Leak().GetName();
+
+    /// schedule another process.
+    if (!hCore::ProcessHelper::StartScheduling())
+    {
+        hCore::kcout << "Let's continue schedule this process...\r\n";
+    }
+}
+
+extern "C" void idt_handle_pf(hCore::UIntPtr rsp)
+{
+    hCore::kcout << hCore::StringBuilder::FromInt("sp{%}", rsp);
+
+    MUST_PASS(hCore::ProcessManager::Shared().Leak().GetCurrent());
+
+    hCore::kcout << "Segmentation Fault, Caused by "
+                   << hCore::ProcessManager::Shared().Leak().GetCurrent().Leak().GetName();
+
+    hCore::ProcessManager::Shared().Leak().GetCurrent().Leak().Crash();
+}
+
+extern "C" void idt_handle_math(hCore::UIntPtr rsp)
+{
+    hCore::kcout << hCore::StringBuilder::FromInt("sp{%}", rsp);
+
+    MUST_PASS(hCore::ProcessManager::Shared().Leak().GetCurrent());
+
+    hCore::kcout << "Math error, Caused by "
+                   << hCore::ProcessManager::Shared().Leak().GetCurrent().Leak().GetName();
+
+    hCore::ProcessManager::Shared().Leak().GetCurrent().Leak().Crash();
+}
+
+extern "C" void idt_handle_generic(hCore::UIntPtr rsp)
+{
+    hCore::kcout << hCore::StringBuilder::FromInt("sp{%}", rsp);
+
+    MUST_PASS(hCore::ProcessManager::Shared().Leak().GetCurrent());
+
+    hCore::kcout << "Processor error, Caused by "
+                   << hCore::ProcessManager::Shared().Leak().GetCurrent().Leak().GetName();
+
+    hCore::ProcessManager::Shared().Leak().GetCurrent().Leak().Crash();
+}
diff --git a/HALKit/AMD64/CoreMultiProcessingAMD64.cpp b/HALKit/AMD64/CoreMultiProcessingAMD64.cpp
new file mode 100644
index 00000000..59812227
--- /dev/null
+++ b/HALKit/AMD64/CoreMultiProcessingAMD64.cpp
@@ -0,0 +1,134 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#include <HALKit/AMD64/Processor.hpp>
+#include <HALKit/AMD64/ACPI/ACPIManager.hpp>
+
+///////////////////////////////////////////////////////////////////////////////////////
+
+//! NOTE: fGSI stands 'Field Global System Interrupt'
+
+namespace hCore::HAL
+{
+    constexpr Int32 kThreadAPIC = 0;
+    constexpr Int32 kThreadLAPIC = 1;
+    constexpr Int32 kThreadIOAPIC = 2;
+    constexpr Int32 kThreadAPIC64 = 3;
+    constexpr Int32 kThreadBoot = 4;
+
+    /*
+     *
+     * this is used to store info about the current running thread
+     * we use this struct to determine if we can use it, or mark it as used or on sleep.
+     *
+     */
+
+    struct ProcessorInfoAMD64 final
+    {
+        Int32 ThreadType;
+        UIntPtr JumpAddress;
+
+        struct
+        {
+            UInt32 Code;
+            UInt32 Data;
+            UInt32 BSS;
+        } Selector;
+    };
+
+    static voidPtr kApicMadt = nullptr;
+    static const char* kApicSignature = "APIC";
+
+    struct Madt final
+    {
+        char fMag[4];
+        Int32 fLength;
+        char fRev;
+        
+        struct MadtAddress final
+        {
+            UInt32 fPhysicalAddress;
+            UInt32 fFlags; // 1 = Dual Legacy PICs installed
+            
+            Char fType;
+            Char fRecLen; // record length
+        };
+    };
+
+    struct MadtProcessorLocalApic final
+    {
+        Char fProcessorId;
+        Char fApicId;
+        UInt32 fFlags;
+    };
+
+    struct MadtIOApic final
+    {
+        Char fApicId;
+        Char fReserved;
+        UInt32 fAddress;
+        UInt32 fSystemInterruptBase;
+    };
+
+    struct MadtInterruptSource final
+    {
+        Char fBusSource;
+        Char fIrqSource;
+        UInt32 fGSI;
+        UInt16 fFlags;	    
+    };
+
+    struct MadtInterruptNmi final
+    {
+        Char fNmiSource;
+        Char fReserved;
+        UInt16 fFlags;
+        UInt32 fGSI;	    
+    };
+
+    struct MadtLocalApicAddressOverride final { UInt16 fResvered; UIntPtr fAddress; };
+
+///////////////////////////////////////////////////////////////////////////////////////
+
+    static Madt kApicMadtList[256];
+
+    Madt* system_find_core(Madt* madt)
+    {
+        madt = madt + sizeof(Madt);
+
+        if (string_compare(madt->fMag, kApicSignature, string_length(kApicSignature)) == 0)
+            return madt;
+
+        return nullptr;
+    }
+
+///////////////////////////////////////////////////////////////////////////////////////
+
+    void system_get_cores(voidPtr rsdPtr)
+    {
+        auto acpi = ACPIManager(rsdPtr);
+        kApicMadt = acpi.Find(kApicSignature).Leak().Leak();
+
+        MUST_PASS(kApicMadt); // MADT must exist.
+
+        SizeT counter = 0UL;
+        Madt* offset = system_find_core((Madt*)kApicMadt);
+        //! now find core addresses.
+        while (offset != nullptr)
+        {
+            // calls rt_copy_memory in NewC++
+            kApicMadtList[counter] = *offset;
+            offset = system_find_core(offset);
+
+            ++counter;
+        }
+    }
+}
+
+///////////////////////////////////////////////////////////////////////////////////////
diff --git a/HALKit/AMD64/CoreSyscallHandlerAMD64.cpp b/HALKit/AMD64/CoreSyscallHandlerAMD64.cpp
new file mode 100644
index 00000000..e93bf2c8
--- /dev/null
+++ b/HALKit/AMD64/CoreSyscallHandlerAMD64.cpp
@@ -0,0 +1,25 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#include <KernelKit/PermissionSelector.hxx>
+#include <HALKit/AMD64/Processor.hpp>
+
+#include <ArchKit/Arch.hpp>
+
+hCore::Array<void (*)(hCore::Int32 id, hCore::HAL::StackFrame *), kMaxSyscalls> kSyscalls;
+
+// IDT System Call Handler.
+// NOTE: don't trust the user.
+extern "C" void rt_syscall_handle(hCore::HAL::StackFrame *stack)
+{
+    for (hCore::SizeT index = 0UL; index < kMaxSyscalls; ++index)
+    {
+        (kSyscalls[index].Leak().Leak())(stack->SID, stack);
+    }
+}
diff --git a/HALKit/AMD64/DebugManager.asm b/HALKit/AMD64/DebugManager.asm
new file mode 100644
index 00000000..bbdb76f7
--- /dev/null
+++ b/HALKit/AMD64/DebugManager.asm
@@ -0,0 +1,31 @@
+;; /*
+;; *	========================================================
+;; *
+;; *	hCore
+;; * 	Copyright Mahrouss Logic, all rights reserved.
+;; *
+;; * 	========================================================
+;; */
+
+[global rt_debug_fence]
+[global rt_debug_fence_end]
+[global __rt_debug_int_3]
+
+;; //////////////////////////////////////////////////// ;;
+
+__rt_debug_record_table:
+    db "DebugMgr/hCore", 0xa, 0xd, 0
+    resb 16
+    dw 0x5566
+__rt_debug_int_3:
+    push 0x6677 ;; Debug check error
+L0:
+    hlt
+    jmp $
+
+rt_debug_fence:
+    push __rt_debug_record_table
+    jmp [rbx]
+rt_debug_fence_end:
+
+;; //////////////////////////////////////////////////// ;;
\ No newline at end of file
diff --git a/HALKit/AMD64/DebugOutput.cxx b/HALKit/AMD64/DebugOutput.cxx
new file mode 100644
index 00000000..21237d4a
--- /dev/null
+++ b/HALKit/AMD64/DebugOutput.cxx
@@ -0,0 +1,68 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#include <KernelKit/DebugOutput.hpp>
+
+#include <ArchKit/Arch.hpp>
+#include <NewKit/Utils.hpp>
+
+namespace hCore
+{
+    namespace Detail
+    {
+        constexpr short PORT = 0x3F8;
+
+        bool serial_init()
+        {
+            HAL::out8(PORT + 1, 0x00); // Disable all interrupts
+            HAL::out8(PORT + 3, 0x80); // Enable DLAB (set baud rate divisor)
+            HAL::out8(PORT + 0, 0x03); // Set divisor to 3 (lo byte) 38400 baud
+            HAL::out8(PORT + 1, 0x00); //                  (hi byte)
+            HAL::out8(PORT + 3, 0x03); // 8 bits, no parity, one stop bit
+            HAL::out8(PORT + 2, 0xC7); // Enable FIFO, clear them, with 14-byte threshold
+            HAL::out8(PORT + 4, 0x0B); // IRQs enabled, RTS/DSR set
+            HAL::out8(PORT + 4, 0x1E); // Set in loopback mode, test the serial chip
+            HAL::out8(PORT + 0, 0xAE); // Test serial chip (send byte 0xAE and check if
+                                       // serial returns same byte)
+
+            // Check if serial is faulty (i.e: not same byte as sent)
+            if (HAL::in8(PORT) != 0xAE)
+            {
+#ifdef __DEBUG__
+                panic(RUNTIME_CHECK_HANDSHAKE);
+#else
+                return false;
+#endif
+            }
+
+            // If serial is not faulty set it in normal operation mode
+            // (not-loopback with IRQs enabled and OUT#1 and OUT#2 bits enabled)
+            HAL::out8(Detail::PORT + 4, 0x0F);
+
+            return true;
+        }
+    }
+
+    void system_io_print(const char *bytes)
+    {
+        if (!bytes)
+            return;
+
+        SizeT index = 0;
+        SizeT len = string_length(bytes, 256);
+
+        while (index < len)
+        {
+            HAL::out8(Detail::PORT, bytes[index]);
+            ++index;
+        }
+    }
+
+    TerminalDevice kcout(hCore::system_io_print, nullptr);
+} // namespace hCore
diff --git a/HALKit/AMD64/DebugPort.cxx b/HALKit/AMD64/DebugPort.cxx
new file mode 100644
index 00000000..ae6012aa
--- /dev/null
+++ b/HALKit/AMD64/DebugPort.cxx
@@ -0,0 +1,66 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+//! @file DebuggerPort.cxx
+//! @brief UART debug via packets.
+
+#include <ArchKit/Arch.hpp>
+
+#define kDebugMaxPorts 16
+	
+#define kDebugUnboundPort 0xFFFF
+
+#define kDebugMag0 'X'
+#define kDebugMag1 'D'
+#define kDebugMag2 'B'
+#define kDebugMag3 'G'
+
+#define kDebugSourceFile 0
+#define kDebugLine 		 33
+#define kDebugTeam 		 43
+#define kDebugEOP  		 49
+
+// after that we have start of additional data.
+
+namespace hCore
+{
+	typedef Char rt_debug_type[255];
+		
+	class DebuggerPorts final
+	{
+	public:
+		Int16 fPort[kDebugMaxPorts];
+		Int16 fBoundCnt;
+		
+	};
+	
+	void rt_debug_listen(DebuggerPorts* theHook) noexcept
+	{
+		if (theHook == nullptr)
+			return;
+		
+		for (UInt32 i = 0U; i < kDebugMaxPorts; ++i)
+		{
+			HAL::out16(theHook->fPort[i], kDebugMag0);
+			HAL::rt_wait_for_io();
+		
+			HAL::out16(theHook->fPort[i], kDebugMag1);
+			HAL::rt_wait_for_io();
+		
+			HAL::out16(theHook->fPort[i], kDebugMag2);
+			HAL::rt_wait_for_io();
+		
+			HAL::out16(theHook->fPort[i], kDebugMag3);
+			HAL::rt_wait_for_io();
+			
+			if (HAL::in16(theHook->fPort[i] != kDebugUnboundPort))
+				theHook->fBoundCnt++;	
+		}
+	}
+}
diff --git a/HALKit/AMD64/HalPageAlloc.cpp b/HALKit/AMD64/HalPageAlloc.cpp
new file mode 100644
index 00000000..3c57dc04
--- /dev/null
+++ b/HALKit/AMD64/HalPageAlloc.cpp
@@ -0,0 +1,61 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#include <HALKit/AMD64/HalPageAlloc.hpp>
+#include <NewKit/Defines.hpp>
+#include <NewKit/Panic.hpp>
+
+// this files handles paging.
+
+static hCore::UIntPtr kPagePtr = 0x0900000;
+static hCore::SizeT kPageCnt = 0UL;
+
+namespace hCore
+{
+    namespace HAL
+    {
+        static auto hal_try_alloc_new_page(SizeT sz, Boolean rw, Boolean user) -> PageTable64*
+        {
+            char *ptr = &(reinterpret_cast<char*>(kPagePtr))[kPageCnt + 1];
+
+            PageTable64 *pte = reinterpret_cast<PageTable64*>(ptr);
+            pte->Rw = rw;
+            pte->User = user;
+            pte->Present = true;
+
+            return pte;
+        }
+
+        auto hal_alloc_page(SizeT sz, Boolean rw, Boolean user) -> PageTable64*
+        {
+            for (SizeT i = 0; i < kPageCnt; ++i)
+            {
+                PageTable64 *pte = (reinterpret_cast<PageTable64*>(&kPagePtr) + i);
+
+                if (!pte->Present) {
+                    pte->User = user;
+                    pte->Rw = rw;
+                    pte->Present = true;
+
+                    return pte;
+                }
+            }
+
+            return hal_try_alloc_new_page(sz, rw, user);
+        }
+
+        auto hal_create_page(Boolean rw, Boolean user) -> UIntPtr
+        {
+            PageTable64 *new_pte = hal_alloc_page(sizeof(PageTable64), rw, user);
+            MUST_PASS(new_pte);
+
+            return reinterpret_cast<UIntPtr>(new_pte);
+        }
+    } // namespace HAL
+} // namespace hCore
diff --git a/HALKit/AMD64/HalPageAlloc.hpp b/HALKit/AMD64/HalPageAlloc.hpp
new file mode 100644
index 00000000..d3efa1f1
--- /dev/null
+++ b/HALKit/AMD64/HalPageAlloc.hpp
@@ -0,0 +1,50 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#pragma once
+
+#include <NewKit/Defines.hpp>
+
+#ifndef PTE_MAX
+#define PTE_MAX (512)
+#endif //! PTE_MAX
+
+#ifndef PTE_ALIGN
+#define PTE_ALIGN (4096)
+#endif //! PTE_ALIGN
+
+extern "C" void flush_tlb(hCore::UIntPtr VirtualAddr);
+extern "C" void write_cr3(hCore::UIntPtr pde);
+extern "C" void write_cr0(hCore::UIntPtr bit);
+
+extern "C" hCore::UIntPtr read_cr0();
+extern "C" hCore::UIntPtr read_cr2();
+extern "C" hCore::UIntPtr read_cr3();
+
+namespace hCore::HAL
+{
+    struct PageTable64
+    {
+        bool Present: 1;
+        bool Rw: 1;
+        bool User: 1;
+        bool Wt: 1;
+        bool Cache: 1;
+        bool Accessed: 1;
+        hCore::Int32 Reserved: 6;
+        hCore::UIntPtr PhysicalAddress: 36;
+        hCore::Int32 Reserved1: 15;
+        bool ExecDisable: 1;
+
+    };
+
+    PageTable64 *hal_alloc_page(SizeT sz, Boolean rw, Boolean user);
+
+    UIntPtr hal_create_page(Boolean rw, Boolean user);
+} // namespace hCore::HAL
diff --git a/HALKit/AMD64/HalRoutines.s b/HALKit/AMD64/HalRoutines.s
new file mode 100644
index 00000000..ed15418a
--- /dev/null
+++ b/HALKit/AMD64/HalRoutines.s
@@ -0,0 +1,27 @@
+.globl load_idt
+.globl load_gdt
+.globl rt_wait_for_io
+.globl rt_get_current_context
+
+.section .text
+load_gdt:
+    lgdt (%rdi)
+    ret
+
+load_idt:
+    lidt (%rdi)
+    sti
+    ret
+
+.section .text
+rt_wait_for_io:
+    jmp .loop
+    .loop:
+        jmp .loop2
+    .loop2:
+        ret
+
+rt_get_current_context:
+    mov %rbp, %rax
+    ret
+
diff --git a/HALKit/AMD64/HardwareAPIC.cpp b/HALKit/AMD64/HardwareAPIC.cpp
new file mode 100644
index 00000000..9c6f61fb
--- /dev/null
+++ b/HALKit/AMD64/HardwareAPIC.cpp
@@ -0,0 +1,46 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#include <ArchKit/Arch.hpp>
+
+// bugs = 0
+
+namespace hCore
+{
+    // @brief wakes up thread.
+    // wakes up thread from hang.
+    void rt_wakeup_thread(HAL::StackFrame* stack)
+    {
+        __asm__ volatile ("cli");
+
+        stack->Rbp = stack->R15;
+        stack->Rsi = stack->Rbp;
+
+        __asm__ volatile ("sti");
+    }
+    
+    static void __rt_hang_proc(void)
+    {
+        while (1)
+            ;
+    }
+
+    // @brief makes thread sleep.
+    // hooks and hangs thread to prevent code from executing.
+    void rt_hang_thread(HAL::StackFrame* stack)
+    {
+        __asm__ volatile ("cli");
+
+        stack->R15 = stack->Rbp;
+        stack->Rbp = (HAL::Reg)&__rt_hang_proc;
+        stack->Rsp = stack->Rbp;
+
+        __asm__ volatile ("sti");
+    }
+}
\ No newline at end of file
diff --git a/HALKit/AMD64/HardwareInit.cpp b/HALKit/AMD64/HardwareInit.cpp
new file mode 100644
index 00000000..4f744a8b
--- /dev/null
+++ b/HALKit/AMD64/HardwareInit.cpp
@@ -0,0 +1,22 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#include <ArchKit/Arch.hpp>
+
+// bugs = 0
+
+namespace hCore
+{
+    bool initialize_hardware_components()
+    {
+        // TODO: Hardware Specific stuff.
+
+        return true;
+    }
+}
\ No newline at end of file
diff --git a/HALKit/AMD64/Hypervisor.hpp b/HALKit/AMD64/Hypervisor.hpp
new file mode 100644
index 00000000..e95cdbf9
--- /dev/null
+++ b/HALKit/AMD64/Hypervisor.hpp
@@ -0,0 +1,38 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#pragma once
+
+#include <NewKit/Defines.hpp>
+
+namespace hCore {
+    MAKE_STRING_ENUM(HYPERVISOR)
+    ENUM_STRING(Qemu,
+    "TCGTCGTCGTCG");
+    ENUM_STRING(KVM,
+    " KVMKVMKVM  ");
+    ENUM_STRING(VMWare,
+    "VMwareVMware");
+    ENUM_STRING(VirtualBox,
+    "VBoxVBoxVBox");
+    ENUM_STRING(Xen,
+    "XenVMMXenVMM");
+    ENUM_STRING(Microsoft,
+    "Microsoft Hv");
+    ENUM_STRING(Parallels,
+    " prl hyperv ");
+    ENUM_STRING(ParallelsAlt,
+    " lrpepyh vr ");
+    ENUM_STRING(Bhyve,
+    "bhyve bhyve ");
+    ENUM_STRING(Qnx,
+    " QNXQVMBSQG ");
+
+    END_STRING_ENUM()
+} // namespace hCore
diff --git a/HALKit/AMD64/PCI/Database.cpp b/HALKit/AMD64/PCI/Database.cpp
new file mode 100644
index 00000000..f5095f7c
--- /dev/null
+++ b/HALKit/AMD64/PCI/Database.cpp
@@ -0,0 +1,14 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#include <KernelKit/PCI/Database.hpp>
+
+namespace hCore
+{
+}
diff --git a/HALKit/AMD64/PCI/Device.cpp b/HALKit/AMD64/PCI/Device.cpp
new file mode 100644
index 00000000..4cd35636
--- /dev/null
+++ b/HALKit/AMD64/PCI/Device.cpp
@@ -0,0 +1,127 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#include <ArchKit/Arch.hpp>
+#include <KernelKit/PCI/Device.hpp>
+
+
+hCore::UInt LumiaPCIReadRaw(hCore::UInt bar, hCore::UShort bus, hCore::UShort dev, hCore::UShort fun)
+{
+    hCore::UInt target = 0x80000000 | ((hCore::UInt) bus << 16) | ((hCore::UInt) dev << 11) | ((hCore::UInt) fun << 8) |
+                  (bar & 0xFC);
+
+    hCore::HAL::out32((hCore::UShort) hCore::PCI::PciConfigKind::ConfigAddress, target);
+
+    return hCore::HAL::in32((hCore::UShort) hCore::PCI::PciConfigKind::ConfigData);
+}
+
+void LumiaPCISetCfgTarget(hCore::UInt bar, hCore::UShort bus, hCore::UShort dev, hCore::UShort fun)
+{
+    hCore::UInt target =
+            0x80000000 | ((hCore::UInt) bus << 16) | ((hCore::UInt) dev << 11) | ((hCore::UInt) fun << 8) | (bar & ~3);
+
+    hCore::HAL::out32((hCore::UShort) hCore::PCI::PciConfigKind::ConfigAddress, target);
+}
+
+namespace hCore::PCI
+{
+    Device::Device(UShort bus, UShort device, UShort func, UShort bar)
+            : m_Bus(bus), m_Device(device), m_Function(func), m_Bar(bar)
+    {}
+
+    Device::~Device() {}
+
+    UInt Device::Read(UInt bar, Size sz)
+    {
+        LumiaPCISetCfgTarget(bar, m_Bus, m_Device, m_Function);
+
+        if (sz == 4)
+            return HAL::in32((UShort) PciConfigKind::ConfigData + (m_Bar & 3));
+        if (sz == 2)
+            return HAL::in16((UShort) PciConfigKind::ConfigData + (m_Bar & 3));
+        if (sz == 1)
+            return HAL::in8((UShort) PciConfigKind::ConfigData + (m_Bar & 3));
+
+        return 0xFFFF;
+    }
+
+    void Device::Write(UInt bar, UIntPtr data, Size sz)
+    {
+        LumiaPCISetCfgTarget(bar, m_Bus, m_Device, m_Function);
+
+        if (sz == 4)
+            HAL::out32((UShort) PciConfigKind::ConfigData + (m_Bar & 3), (UInt) data);
+        if (sz == 2)
+            HAL::out16((UShort) PciConfigKind::ConfigData + (m_Bar & 3), (UShort) data);
+        if (sz == 1)
+            HAL::out8((UShort) PciConfigKind::ConfigData + (m_Bar & 3), (UChar) data);
+    }
+
+    UShort Device::DeviceId()
+    {
+        return (UShort)(LumiaPCIReadRaw(0x0 >> 16, m_Bus, m_Device, m_Function));
+    }
+
+    UShort Device::VendorId()
+    {
+        return (UShort) (LumiaPCIReadRaw(0x0, m_Bus, m_Device, m_Function) >> 16);
+    }
+
+    UShort Device::InterfaceId()
+    {
+        return (UShort)(LumiaPCIReadRaw(0x0, m_Bus, m_Device, m_Function) >> 16);
+    }
+
+    UChar Device::Class()
+    {
+        return (UChar)(LumiaPCIReadRaw(0x08, m_Bus, m_Device, m_Function) >> 24);
+    }
+
+    UChar Device::Subclass()
+    {
+        return (UChar)(LumiaPCIReadRaw(0x08, m_Bus, m_Device, m_Function) >> 16);
+    }
+
+    UChar Device::ProgIf()
+    {
+        return (UChar)(LumiaPCIReadRaw(0x08, m_Bus, m_Device, m_Function) >> 8);
+    }
+
+    UChar Device::HeaderType()
+    {
+        return (UChar)(LumiaPCIReadRaw(0xC, m_Bus, m_Device, m_Function) >> 16);
+    }
+
+    void Device::EnableMmio()
+    {
+        bool enable = Read(0x04, sizeof(UChar)) | (1 << 1);
+        Write(0x04, enable, sizeof(UShort));
+    }
+
+    void Device::BecomeBusMaster()
+    {
+        bool enable = Read(0x04, sizeof(UShort)) | (1 << 2);
+        Write(0x04, enable, sizeof(UShort));
+    }
+
+    UShort Device::Vendor()
+    {
+        UShort vendor = VendorId();
+
+        if (vendor != (UShort) PciConfigKind::Invalid)
+            m_Device = (UShort) Read(0x0, sizeof(UShort));
+
+        return m_Device;
+    }
+
+    Device::operator bool()
+    {
+        return VendorId() != (UShort) PciConfigKind::Invalid;
+    }
+} // namespace hCore::PCI
diff --git a/HALKit/AMD64/PCI/Dma.cpp b/HALKit/AMD64/PCI/Dma.cpp
new file mode 100644
index 00000000..f3e858c0
--- /dev/null
+++ b/HALKit/AMD64/PCI/Dma.cpp
@@ -0,0 +1,75 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#include <KernelKit/PCI/Dma.hpp>
+
+namespace hCore {
+    DMAWrapper::operator bool() {
+        return m_Address;
+    }
+
+    bool DMAWrapper::operator!() {
+        return !m_Address;
+    }
+
+    Boolean DMAWrapper::Check(UIntPtr offset) const {
+        if (!m_Address)
+            return false;
+        if (offset == 0)
+            return true;
+
+        kcout << "[DMAWrapper::IsIn] Checking offset..\n";
+        return reinterpret_cast<UIntPtr>(m_Address) >= offset;
+    }
+
+    bool DMAWrapper::Write(const UIntPtr &bit, const UIntPtr &offset) {
+        if (!m_Address)
+            return false;
+
+        kcout << "[DMAWrapper::Write] Writing at address..\n";
+
+        auto addr = (volatile UIntPtr *) (reinterpret_cast<UIntPtr>(m_Address) + offset);
+        *addr = bit;
+
+        return true;
+    }
+
+    UIntPtr DMAWrapper::Read(const UIntPtr &offset) {
+        kcout << "[DMAWrapper::Read] checking m_Address..\n";
+        if (!m_Address)
+            return 0;
+
+        kcout << "[DMAWrapper::Read] Reading m_Address..\n";
+        return *(volatile UIntPtr *) (reinterpret_cast<UIntPtr>(m_Address) + offset);;
+    }
+
+    UIntPtr DMAWrapper::operator[](const UIntPtr &offset) {
+        return this->Read(offset);
+    }
+
+    OwnPtr <IOBuf<Char *>> DMAFactory::Construct(OwnPtr <DMAWrapper> &dma) {
+        if (!dma)
+            return {};
+
+        OwnPtr < IOBuf < Char * >> dmaOwnPtr = make_ptr < IOBuf < Char * >, char * >
+                                                                            (reinterpret_cast<char*>(dma->m_Address));
+
+        if (!dmaOwnPtr)
+            return {};
+
+        kcout << "Returning the new OwnPtr<IOBuf<Char*>>!\r\n";
+        return dmaOwnPtr;
+    }
+
+    DMAWrapper& DMAWrapper::operator=(voidPtr Ptr)
+    {
+        m_Address = Ptr;
+        return *this;
+    }
+} // namespace hCore
diff --git a/HALKit/AMD64/PCI/Express.cpp b/HALKit/AMD64/PCI/Express.cpp
new file mode 100644
index 00000000..2cbc7134
--- /dev/null
+++ b/HALKit/AMD64/PCI/Express.cpp
@@ -0,0 +1,13 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#include <KernelKit/PCI/Express.hpp>
+
+namespace hCore {
+}
\ No newline at end of file
diff --git a/HALKit/AMD64/PCI/IO.cpp b/HALKit/AMD64/PCI/IO.cpp
new file mode 100644
index 00000000..547a83a4
--- /dev/null
+++ b/HALKit/AMD64/PCI/IO.cpp
@@ -0,0 +1,10 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#include <KernelKit/PCI/IO.hpp>
diff --git a/HALKit/AMD64/PCI/Iterator.cpp b/HALKit/AMD64/PCI/Iterator.cpp
new file mode 100644
index 00000000..a5649e52
--- /dev/null
+++ b/HALKit/AMD64/PCI/Iterator.cpp
@@ -0,0 +1,39 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#include <KernelKit/PCI/Iterator.hpp>
+
+#define PCI_ITERATOR_FIND_AND_UNWRAP(DEV, SZ)                                                                          \
+    if (DEV.Leak())                                                                                                    \
+        return DEV.Leak();
+
+namespace hCore::PCI {
+    Iterator::Iterator(const Types::PciDeviceKind &type) {
+        // probe devices.
+        for (int bus = 0; bus < ME_BUS_COUNT; ++bus) {
+            for (int device = 0; device < ME_DEVICE_COUNT; ++device) {
+                for (int function = 0; function < ME_FUNCTION_COUNT; ++function) {
+                    Device dev(bus, device, function, 0);
+
+                    if (dev.Class() == (UChar) type) {
+                        m_Devices[bus].Leak().Leak() = dev;
+                    }
+                }
+            }
+        }
+    }
+
+    Iterator::~Iterator() {
+    }
+
+    Ref<PCI::Device> Iterator::operator[](const Size &sz) {
+        PCI_ITERATOR_FIND_AND_UNWRAP(m_Devices[sz], sz);
+        return {};
+    }
+} // namespace hCore::PCI
diff --git a/HALKit/AMD64/PCI/PCI.cpp b/HALKit/AMD64/PCI/PCI.cpp
new file mode 100644
index 00000000..492b7a4d
--- /dev/null
+++ b/HALKit/AMD64/PCI/PCI.cpp
@@ -0,0 +1,10 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#include <KernelKit/PCI/PCI.hpp>
\ No newline at end of file
diff --git a/HALKit/AMD64/Processor.cpp b/HALKit/AMD64/Processor.cpp
new file mode 100644
index 00000000..8d082b2d
--- /dev/null
+++ b/HALKit/AMD64/Processor.cpp
@@ -0,0 +1,61 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#include <HALKit/AMD64/Processor.hpp>
+
+namespace hCore::HAL {
+    void out8(UInt16 port, UInt8 value) {
+        asm volatile("outb %%al, %1" : : "a"(value), "Nd"(port) : "memory");
+    }
+
+    void out16(UInt16 port, UInt16 value) {
+        asm volatile("outw %%ax, %1" : : "a"(value), "Nd"(port) : "memory");
+    }
+
+    void out32(UInt16 port, UInt32 value) {
+        asm volatile("outl %%eax, %1" : : "a"(value), "Nd"(port) : "memory");
+    }
+
+    UInt8 in8(UInt16 port) {
+        UInt8 value = 0UL;
+        asm volatile("inb %1, %%al" : "=a"(value) : "Nd"(port) : "memory");
+
+        return value;
+    }
+
+    UInt16 in16(UInt16 port) {
+        UInt16 value = 0UL;
+        asm volatile("inw %1, %%ax" : "=a"(value) : "Nd"(port) : "memory");
+
+        return value;
+    }
+
+    UInt32 in32(UInt16 port) {
+        UInt32 value = 0UL;
+        asm volatile("inl %1, %%eax" : "=a"(value) : "Nd"(port) : "memory");
+
+        return value;
+    }
+
+    void rt_halt() {
+        asm volatile("hlt");
+    }
+
+    void rt_cli() {
+        asm volatile("cli");
+    }
+
+    void rt_sti() {
+        asm volatile("sti");
+    }
+
+    void rt_cld() {
+        asm volatile("cld");
+    }
+} // namespace hCore::HAL
diff --git a/HALKit/AMD64/Processor.hpp b/HALKit/AMD64/Processor.hpp
new file mode 100644
index 00000000..0f6531c2
--- /dev/null
+++ b/HALKit/AMD64/Processor.hpp
@@ -0,0 +1,135 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#pragma once
+
+#include <NewKit/Defines.hpp>
+#include <NewKit/Array.hpp>
+#include <NewKit/Utils.hpp>
+
+#define IsActiveLow(flag) (flag & 2)
+#define IsLevelTriggered(flag) (flag & 8)
+
+namespace hCore::HAL 
+{
+    extern "C" UChar in8(UInt16 port);
+    extern "C" UShort in16(UInt16 port);
+    extern "C" UInt in32(UInt16 port);
+
+    extern "C" void out16(UShort port, UShort byte);
+    extern "C" void out8(UShort port, UChar byte);
+    extern "C" void out32(UShort port, UInt byte);
+
+    extern "C" void rt_wait_for_io();
+    extern "C" void rt_halt();
+    extern "C" void rt_cli();
+    extern "C" void rt_sti();
+    extern "C" void rt_cld();
+
+    class Register64 
+    {
+    public:
+        UIntPtr Base;
+        UShort Limit;
+
+        operator bool() { return Base > Limit; }
+
+    };
+
+    using RawRegister = UInt64;
+
+    using InterruptId = UShort; /* For each element in the IVT */
+    using interruptTrap = UIntPtr(UIntPtr sp);
+
+    typedef UIntPtr Reg;
+
+    struct __attribute__((packed)) StackFrame
+    {
+        Reg Rax;
+        Reg Rbx;
+        Reg Rcx;
+        Reg Rdx;
+        Reg Rsi;
+        Reg Rdi;
+        Reg Rbp;
+        Reg Rsp;
+        Reg R8;
+        Reg R9;
+        Reg R10;
+        Reg R11;
+        Reg R12;
+        Reg R13;
+        Reg R14;
+        Reg R15; // Reserved: Multi Processor manager (Hal)
+        Reg SID; // Reserved: system call id (Hal)
+    };
+
+    typedef StackFrame* StackFramePtr;
+
+    class InterruptDescriptor final
+    {
+    public:
+        UShort Offset;
+        UShort Selector;
+        UChar Ist;
+        UChar Atrributes;
+
+        UShort SecondOffset;
+        UInt ThirdOffset;
+        UInt Zero;
+
+        operator bool() { return Offset != 0xFFFF; }
+
+    };
+
+    using InterruptDescriptorArray = Array<InterruptDescriptor, 256>;
+
+    class SegmentDescriptor final
+    {
+    public:
+        UIntPtr Base;
+        UIntPtr BaseMiddle;
+        UIntPtr BaseHigh;
+
+        UShort Limit;
+        UChar Gran;
+        UChar AB;
+
+        operator bool() { return Base > Limit; }
+        
+    };
+
+    using SegmentArray = Array<SegmentDescriptor, 6>;
+
+    class GDTLoader final
+    {
+    public:
+        static void Load(Register64 &gdt);
+        static void Load(Ref<Register64> &gdt);
+
+    };
+
+    class IDTLoader final
+    {
+    public:
+        static void Load(Register64 &idt);
+        static void Load(Ref<Register64> &idt);
+
+    };
+    
+    void system_get_cores(voidPtr rsdPtr);
+} // namespace hCore::HAL
+
+extern "C" void idt_handle_system_call(hCore::UIntPtr rsp);
+extern "C" void idt_handle_generic(hCore::UIntPtr rsp);
+extern "C" void load_idt(hCore::voidPtr ptr);
+extern "C" void load_gdt(hCore::voidPtr ptr);
+extern "C" void idt_handle_gpf(hCore::UIntPtr rsp);
+extern "C" void idt_handle_math(hCore::UIntPtr rsp);
+extern "C" void idt_handle_pf(hCore::UIntPtr rsp);
diff --git a/HALKit/AMD64/SMPCoreManager.asm b/HALKit/AMD64/SMPCoreManager.asm
new file mode 100644
index 00000000..a528f847
--- /dev/null
+++ b/HALKit/AMD64/SMPCoreManager.asm
@@ -0,0 +1,16 @@
+[bits 64]
+
+[global rt_do_context_switch]
+[extern rt_debug_fence]
+[extern rt_debug_fence_end]
+
+rt_do_context_switch:
+    mov rsi, [rt_do_context_switch]
+    call rt_debug_fence
+
+    mov rsi, rdi
+    mov rax, rsi
+
+    call rt_debug_fence_end
+
+    iret
\ No newline at end of file
diff --git a/HALKit/AMD64/crti.s b/HALKit/AMD64/crti.s
new file mode 100644
index 00000000..5856b9e9
--- /dev/null
+++ b/HALKit/AMD64/crti.s
@@ -0,0 +1,18 @@
+/* x86_64 crti.s */
+.section .init
+.global _init
+.type _init, @function
+_init:
+	push %rbp
+	movq %rsp, %rbp
+	/* gcc will nicely put the contents of crtbegin.o's .init section here. */
+
+.section .fini
+.global _fini
+.type _fini, @function
+_fini:
+	push %rbp
+	movq %rsp, %rbp
+	/* gcc will nicely put the contents of crtbegin.o's .fini section here. */
+
+
diff --git a/HALKit/AMD64/crtn.s b/HALKit/AMD64/crtn.s
new file mode 100644
index 00000000..acc8faa5
--- /dev/null
+++ b/HALKit/AMD64/crtn.s
@@ -0,0 +1,11 @@
+/* x86_64 crtn.s */
+.section .init
+	/* gcc will nicely put the contents of crtend.o's .init section here. */
+	popq %rbp
+	ret
+
+.section .fini
+	/* gcc will nicely put the contents of crtend.o's .fini section here. */
+	popq %rbp
+	ret
+
diff --git a/HALKit/ARC/.hgkeep b/HALKit/ARC/.hgkeep
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/HALKit/ARC/.hgkeep
diff --git a/HALKit/ARM64/.gitkeep b/HALKit/ARM64/.gitkeep
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/HALKit/ARM64/.gitkeep
diff --git a/HALKit/Alpha/CR.s b/HALKit/Alpha/CR.s
new file mode 100644
index 00000000..b01dc619
--- /dev/null
+++ b/HALKit/Alpha/CR.s
@@ -0,0 +1,11 @@
+.globl read_lr1
+.globl read_lr0
+
+.section .text
+    read_lr0:
+        movq %r30, %cr3
+        ret
+
+    read_cr0:
+        movq %r30, %cr0
+        ret
\ No newline at end of file
diff --git a/HALKit/Alpha/CoreInterruptHandlerDEC.cpp b/HALKit/Alpha/CoreInterruptHandlerDEC.cpp
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/HALKit/Alpha/CoreInterruptHandlerDEC.cpp
diff --git a/HALKit/Alpha/CoreSyscallHandlerDEC.cpp b/HALKit/Alpha/CoreSyscallHandlerDEC.cpp
new file mode 100644
index 00000000..d1c656d6
--- /dev/null
+++ b/HALKit/Alpha/CoreSyscallHandlerDEC.cpp
@@ -0,0 +1,21 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#include <ArchKit/Arch.hpp>
+#include <HALKit/Alpha/Processor.hpp>
+
+hCore::Array<void (*)(hCore::Int32 id, hCore::HAL::StackFrame *), kMaxSyscalls> kSyscalls;
+
+extern "C" void rt_syscall_handle(hCore::HAL::StackFrame *stack)
+{
+    for (hCore::SizeT index = 0UL; index < kMaxSyscalls; ++index)
+    {
+        (kSyscalls[index].Leak().Leak())(stack->ID, stack);
+    }
+}
diff --git a/HALKit/Alpha/HAL.s b/HALKit/Alpha/HAL.s
new file mode 100644
index 00000000..46127130
--- /dev/null
+++ b/HALKit/Alpha/HAL.s
@@ -0,0 +1,13 @@
+.globl rt_wait_for_io
+
+.section .text
+rt_wait_for_io:
+    jmp .L
+.L:
+	jmp .L2
+	wtint ;; wait for interrupt
+.L2:
+
+    ret
+
+
diff --git a/HALKit/Alpha/Processor.hpp b/HALKit/Alpha/Processor.hpp
new file mode 100644
index 00000000..7e230c0e
--- /dev/null
+++ b/HALKit/Alpha/Processor.hpp
@@ -0,0 +1,10 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright XPX Corp, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#pragma once
\ No newline at end of file
diff --git a/HALKit/Alpha/README b/HALKit/Alpha/README
new file mode 100644
index 00000000..91e7b134
--- /dev/null
+++ b/HALKit/Alpha/README
@@ -0,0 +1 @@
+This is for DEC Alpha.
diff --git a/HALKit/Alpha/SYSCALL.s b/HALKit/Alpha/SYSCALL.s
new file mode 100644
index 00000000..19cab808
--- /dev/null
+++ b/HALKit/Alpha/SYSCALL.s
@@ -0,0 +1,10 @@
+.section .text
+system_handle_user_call:
+	.cfi_startproc
+
+	push %r0
+	jmp %r1
+	mov %r30, %r2
+
+	.cfi_endproc
+	retsys
\ No newline at end of file
diff --git a/HALKit/Alpha/VM.s b/HALKit/Alpha/VM.s
new file mode 100644
index 00000000..d8d7aa71
--- /dev/null
+++ b/HALKit/Alpha/VM.s
@@ -0,0 +1,5 @@
+.global flush_tlb
+
+.section .text
+flush_tlb:
+	swppal
\ No newline at end of file
diff --git a/HALKit/NewCPU b/HALKit/NewCPU
new file mode 120000
index 00000000..22f9ce8e
--- /dev/null
+++ b/HALKit/NewCPU
@@ -0,0 +1 @@
+ARC
\ No newline at end of file
diff --git a/HALKit/PC b/HALKit/PC
new file mode 120000
index 00000000..4af647a3
--- /dev/null
+++ b/HALKit/PC
@@ -0,0 +1 @@
+AMD64/
\ No newline at end of file
diff --git a/HALKit/PowerPC/.gitkeep b/HALKit/PowerPC/.gitkeep
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/HALKit/PowerPC/.gitkeep
diff --git a/HALKit/PowerPC/CoreContextSwitchPowerPC.s b/HALKit/PowerPC/CoreContextSwitchPowerPC.s
new file mode 100644
index 00000000..96ef6d80
--- /dev/null
+++ b/HALKit/PowerPC/CoreContextSwitchPowerPC.s
@@ -0,0 +1,20 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+.align 4
+.type name, @function
+.text
+.globl rt_do_context_switch
+
+/* r3 = assigner stack, r4 = assignee stack */
+rt_do_context_switch:
+
+    lwz %r4, 0(%r3)
+
+    blr
diff --git a/HALKit/PowerPC/CoreSyscallHandlerPowerPC.cpp b/HALKit/PowerPC/CoreSyscallHandlerPowerPC.cpp
new file mode 100644
index 00000000..213b45ec
--- /dev/null
+++ b/HALKit/PowerPC/CoreSyscallHandlerPowerPC.cpp
@@ -0,0 +1,21 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#include <ArchKit/Arch.hpp>
+#include <NewKit/Array.hpp>
+
+hCore::Array<void (*)(hCore::Int32 id, hCore::HAL::StackFrame *), kMaxSyscalls> kSyscalls;
+
+extern "C" void rt_syscall_handle(hCore::HAL::StackFrame *stack)
+{
+    for (hCore::SizeT index = 0UL; index < kMaxSyscalls; ++index)
+    {
+        (kSyscalls[index].Leak().Leak())(stack->ID, stack);
+    }
+}
diff --git a/HALKit/PowerPC/PCI/.gitkeep b/HALKit/PowerPC/PCI/.gitkeep
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/HALKit/PowerPC/PCI/.gitkeep
diff --git a/HALKit/PowerPC/PCI/Device.cxx b/HALKit/PowerPC/PCI/Device.cxx
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/HALKit/PowerPC/PCI/Device.cxx
diff --git a/HALKit/PowerPC/Processor.hpp b/HALKit/PowerPC/Processor.hpp
new file mode 100644
index 00000000..a1add51c
--- /dev/null
+++ b/HALKit/PowerPC/Processor.hpp
@@ -0,0 +1,50 @@
+/*
+ *	========================================================
+ *
+ *	hCore
+ * 	Copyright Mahrouss Logic, all rights reserved.
+ *
+ * 	========================================================
+ */
+
+#pragma once
+
+#include <NewKit/Defines.hpp>
+#include <NewKit/Utils.hpp>
+
+#define __aligned __attribute__((aligned(4)))
+
+namespace hCore::HAL
+{
+    typedef UIntPtr Reg;
+
+    struct __aligned StackFrame
+    {
+        Reg R0;
+        Reg R1;
+        Reg R2;
+        Reg R3;
+        Reg R4;
+        Reg R5;
+        Reg R6;
+        Reg R7;
+        Reg ID; // R8
+    };
+
+    typedef StackFrame* StackFramePtr;
+
+    inline void rt_halt()
+    {
+        while (1)
+        {}
+    }
+
+    inline void rt_cli()
+    {
+
+    }
+}
+
+extern "C" void int_handle_math(hCore::UIntPtr sp);
+extern "C" void int_handle_pf(hCore::UIntPtr sp);
+extern "C" void* __ppc_alloca(size_t sz);
\ No newline at end of file
diff --git a/HALKit/X86S/.gitkeep b/HALKit/X86S/.gitkeep
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/HALKit/X86S/.gitkeep
diff --git a/HALKit/compile_flags.txt b/HALKit/compile_flags.txt
new file mode 100644
index 00000000..a37ae6bf
--- /dev/null
+++ b/HALKit/compile_flags.txt
@@ -0,0 +1,5 @@
+-nostdlib
+-ffreestanding
+-std=c++20
+-I./
+-I../