diff options
| author | Amlal <amlal.elmahrouss@icloud.com> | 2025-02-20 15:18:09 +0100 |
|---|---|---|
| committer | Amlal <amlal.elmahrouss@icloud.com> | 2025-02-20 15:18:09 +0100 |
| commit | 4fc35d979196c4ff82ae9a59913d555fa034c417 (patch) | |
| tree | 1e1b5fef79ee8b42ff61fcc954a5e65daf7120c5 /dev/Kernel/HALKit/AMD64/PCI | |
| parent | 05464fa7f99ce2bb76762bf00cc18be3f7ff33f1 (diff) | |
AHCI.cc: Lots of patches.
Signed-off-by: Amlal <amlal.elmahrouss@icloud.com>
Diffstat (limited to 'dev/Kernel/HALKit/AMD64/PCI')
| -rw-r--r-- | dev/Kernel/HALKit/AMD64/PCI/Device.cc | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/dev/Kernel/HALKit/AMD64/PCI/Device.cc b/dev/Kernel/HALKit/AMD64/PCI/Device.cc index 576fe026..348e058a 100644 --- a/dev/Kernel/HALKit/AMD64/PCI/Device.cc +++ b/dev/Kernel/HALKit/AMD64/PCI/Device.cc @@ -7,6 +7,11 @@ #include <ArchKit/ArchKit.h> #include <KernelKit/PCI/Device.h> +#define PCI_BAR_IO 0x01 +#define PCI_BAR_LOWMEM 0x02 +#define PCI_BAR_64 0x04 +#define PCI_BAR_PREFETCH 0x08 + NeOS::UInt NE_PCIReadRaw(NeOS::UInt bar, NeOS::UShort bus, NeOS::UShort dev, NeOS::UShort fun) { NeOS::UInt target = 0x80000000 | ((NeOS::UInt)bus << 16) | @@ -33,11 +38,6 @@ void NE_PCISetCfgTarget(NeOS::UInt bar, NeOS::UShort bus, NeOS::UShort dev, NeOS NeOS::HAL::rt_wait_400ns(); } -#define PCI_BAR_IO 0x01 -#define PCI_BAR_LOWMEM 0x02 -#define PCI_BAR_64 0x04 -#define PCI_BAR_PREFETCH 0x08 - namespace NeOS::PCI { Device::Device(UShort bus, UShort device, UShort func, UInt32 bar) @@ -124,34 +124,34 @@ namespace NeOS::PCI void Device::EnableMmio(UInt32 bar_in) { - UInt32 enable = Read((UShort)PciConfigKind::CommandReg, sizeof(UInt32)); + UInt32 enable = Read(bar_in, sizeof(UInt32)); enable |= (1 << 1); - Write((UShort)PciConfigKind::CommandReg, enable, sizeof(UInt32)); + Write(bar_in, enable, sizeof(UInt32)); } void Device::BecomeBusMaster(UInt32 bar_in) { - UInt32 enable = Read((UShort)PciConfigKind::CommandReg, sizeof(UInt32)); + UInt32 enable = Read(bar_in, sizeof(UInt32)); enable |= (1 << 2); - Write((UShort)PciConfigKind::CommandReg, enable, sizeof(UInt32)); + Write(bar_in, enable, sizeof(UInt32)); } UIntPtr Device::Bar(UInt32 bar_in) { - UInt32 bar = NE_PCIReadRaw(bar_in & 0xFC, fBus, fDevice, fFunction); + UInt32 bar = NE_PCIReadRaw(bar_in & ~0x03, fBus, fDevice, fFunction); if (bar & PCI_BAR_IO) - return bar & ~0x03; + return static_cast<UIntPtr>(bar & ~0x03); if (bar & PCI_BAR_64) { - UInt32 high = NE_PCIReadRaw((bar_in + 4) & 0xFC, fBus, fDevice, fFunction); - return ((UIntPtr)high << 32) | (bar & ~0x0F); + UInt32 high = NE_PCIReadRaw((bar_in + 4) & ~0x03, fBus, fDevice, fFunction); + return (static_cast<UIntPtr>(high) << 32) | (bar & ~0x0F); } - return bar & ~0x0F; + return static_cast<UIntPtr>(bar & ~0x0F); } UShort Device::Vendor() |