feat(kernel): source code improvements.

Signed-off-by: Amlal El Mahrouss <amlal@nekernel.org>

6 files changed, 64 insertions, 69 deletions

diff --git a/dev/kernel/HALKit/ARM64/HalApplicationProcessor.cc b/dev/kernel/HALKit/ARM64/HalApplicationProcessor.cc
index d37a3e54..5be41e4e 100644
--- a/dev/kernel/HALKit/ARM64/HalApplicationProcessor.cc
+++ b/dev/kernel/HALKit/ARM64/HalApplicationProcessor.cc
@@ -4,6 +4,23 @@
 

 ------------------------------------------- */

 

+#define GICD_BASE 0x08000000

+#define GICC_BASE 0x08010000

+

+#define GICD_CTLR 0x000

+#define GICD_ISENABLER 0x100

+#define GICD_ICENABLER 0x180

+#define GICD_ISPENDR 0x200

+#define GICD_ICPENDR 0x280

+#define GICD_IPRIORITYR 0x400

+#define GICD_ITARGETSR 0x800

+#define GICD_ICFGR 0xC00

+

+#define GICC_CTLR 0x000

+#define GICC_PMR 0x004

+#define GICC_IAR 0x00C

+#define GICC_EOIR 0x010

+

 #include <HALKit/ARM64/ApplicationProcessor.h>

 #include <HALKit/ARM64/Processor.h>

 #include <KernelKit/DebugOutput.h>

@@ -11,28 +28,11 @@
 #include <KernelKit/ProcessScheduler.h>

 #include <KernelKit/Timer.h>

 

-#define GICD_BASE 0x08000000  // Distributor base address

-#define GICC_BASE 0x08010000  // CPU interface base address

-

-#define GICD_CTLR 0x000        // Distributor Control Register

-#define GICD_ISENABLER 0x100   // Interrupt Set-Enable Registers

-#define GICD_ICENABLER 0x180   // Interrupt Clear-Enable Registers

-#define GICD_ISPENDR 0x200     // Interrupt Set-Pending Registers

-#define GICD_ICPENDR 0x280     // Interrupt Clear-Pending Registers

-#define GICD_IPRIORITYR 0x400  // Interrupt Priority Registers

-#define GICD_ITARGETSR 0x800   // Interrupt Processor Targets Registers

-#define GICD_ICFGR 0xC00       // Interrupt Configuration Registers

-

-#define GICC_CTLR 0x000  // CPU Interface Control Register

-#define GICC_PMR 0x004   // Interrupt Priority Mask Register

-#define GICC_IAR 0x00C   // Interrupt Acknowledge Register

-#define GICC_EOIR 0x010  // End of Interrupt Register

-

 // ================================================================= //

 

 namespace Kernel {

 struct HAL_HARDWARE_THREAD final {

-  HAL::StackFramePtr mFrame;

+  HAL::StackFramePtr mFramePtr;

   ProcessID          mThreadID{0};

 };

 

@@ -41,49 +41,37 @@ STATIC HAL_HARDWARE_THREAD kHWThread[kMaxAPInsideSched] = {{nullptr}};
 namespace Detail {

   STATIC BOOL kGICEnabled = NO;

 

-  STATIC void mp_hang_fn(void) {

-    while (YES)

-      ;

-

-    dbg_break_point();

-  }

-

-  Void mp_setup_gic_el0(Void) {

-    // enable distributor.

+  /***********************************************************************************/

+  /// @brief Enables the GIC with EL0 configuration.

+  /// @internal

+  /***********************************************************************************/

+  STATIC Void mp_setup_gic_el0(Void) {

     ke_dma_write<UInt32>(GICD_BASE, GICD_CTLR, YES);

 

     UInt32 gicc_ctlr = ke_dma_read<UInt32>(GICC_BASE, GICC_CTLR);

 

-    const auto kEnableSignalInt = YES;

+    const UInt8 kEnableSignalInt = 0x1;

 

-    gicc_ctlr |= kEnableSignalInt;         // Enable signaling of interrupts

-    gicc_ctlr |= (kEnableSignalInt << 1);  // Allow Group 1 interrupts in EL0

+    gicc_ctlr |= kEnableSignalInt;

+    gicc_ctlr |= (kEnableSignalInt << 0x1);

 

     ke_dma_write<UInt32>(GICC_BASE, GICC_CTLR, gicc_ctlr);

 

-    // Set priority mask (accept all priorities)

     ke_dma_write<UInt32>(GICC_BASE, GICC_PMR, 0xFF);

 

     UInt32 icfgr = ke_dma_read<UInt32>(GICD_BASE, GICD_ICFGR + (0x20 / 0x10) * 4);

 

-    icfgr |= (0x2 << ((32 % 16) * 2));  // Edge-triggered

-    ke_dma_write<UInt32>(GICD_BASE, GICD_ICFGR + (0x20 / 0x10) * 4, icfgr);

+    icfgr |= (0x2 << ((32 % 16) * 2));

 

-    // Target interrupt 32 to CPU 1

+    ke_dma_write<UInt32>(GICD_BASE, GICD_ICFGR + (0x20 / 0x10) * 4, icfgr);

     ke_dma_write<UInt32>(GICD_BASE, GICD_ITARGETSR + (0x20 / 0x04) * 4, 0x2 << ((32 % 4) * 8));

-

-    // Set interrupt 32 priority to lowest (0xFF)

     ke_dma_write<UInt32>(GICD_BASE, GICD_IPRIORITYR + (0x20 / 0x04) * 4, 0xFF << ((32 % 4) * 8));

-

-    // Enable interrupt 32 for AP.

     ke_dma_write<UInt32>(GICD_BASE, GICD_ISENABLER + 4, 0x01);

   }

 

-  BOOL mp_handle_gic_interrupt_el0(Void) {

-    // Read the interrupt ID

+  EXTERN_C BOOL mp_handle_gic_interrupt_el0(Void) {

     UInt32 interrupt_id = ke_dma_read<UInt32>(GICC_BASE, GICC_IAR);

 

-    // Check if it's a valid interrupt (not spurious)

     if ((interrupt_id & 0x3FF) < 1020) {

       auto interrupt = interrupt_id & 0x3FF;

 

@@ -106,15 +94,25 @@ namespace Detail {
       return YES;

     }

 

-    // spurious interrupt

     return NO;

   }

 }  // namespace Detail

 

+/***********************************************************************************/

+/// @brief Get current stack frame for a thread.

+/// @param thrdid The thread ID.

+/***********************************************************************************/

+

 EXTERN_C HAL::StackFramePtr mp_get_current_context(ProcessID thrdid) {

-  return kHWThread[thrdid].mFrame;

+  return kHWThread[thrdid].mFramePtr;

 }

 

+/***********************************************************************************/

+/// @brief Register current stack frame for a thread.

+/// @param stack_frame The current stack frame.

+/// @param thrdid The thread ID.

+/***********************************************************************************/

+

 EXTERN_C Bool mp_register_process(HAL::StackFramePtr stack_frame, ProcessID thrdid) {

   MUST_PASS(Detail::kGICEnabled);

 

@@ -123,25 +121,20 @@ EXTERN_C Bool mp_register_process(HAL::StackFramePtr stack_frame, ProcessID thrd
 

   const auto process_index = thrdid;

 

-  kHWThread[process_index].mFrame    = stack_frame;

+  kHWThread[process_index].mFramePtr = stack_frame;

   kHWThread[process_index].mThreadID = thrdid;

 

-  STATIC HardwareTimer timer{rtl_milliseconds(1000)};

-  timer.Wait();

-

-  HardwareThreadScheduler::The()[thrdid].Leak()->Busy(NO);

-

   return YES;

 }

 

-/// @internal

+/***********************************************************************************/

 /// @brief Initialize the Global Interrupt Controller.

+/// @internal

+/***********************************************************************************/

 Void mp_init_cores(Void) noexcept {

   if (!Detail::kGICEnabled) {

     Detail::kGICEnabled = YES;

     Detail::mp_setup_gic_el0();

   }

-

-  return Detail::kGICEnabled;

 }

 }  // namespace Kernel
\ No newline at end of file
diff --git a/dev/kernel/HALKit/ARM64/HalFlushTLB.S b/dev/kernel/HALKit/ARM64/HalCommonAPI.s
index e76b6e3f..e76b6e3f 100644
--- a/dev/kernel/HALKit/ARM64/HalFlushTLB.S
+++ b/dev/kernel/HALKit/ARM64/HalCommonAPI.s
diff --git a/dev/kernel/HALKit/ARM64/HalInterruptAPI.s b/dev/kernel/HALKit/ARM64/HalInterruptAPI.s
new file mode 100644
index 00000000..cafebb7d
--- /dev/null
+++ b/dev/kernel/HALKit/ARM64/HalInterruptAPI.s
@@ -0,0 +1,3 @@
+/* (c) 2024-2025 Amlal El Mahrouss */
+
+.text
diff --git a/dev/kernel/HALKit/ARM64/HalTimerARM64.cc b/dev/kernel/HALKit/ARM64/HalTimerARM64.cc
index 32f64aec..2a595f11 100644
--- a/dev/kernel/HALKit/ARM64/HalTimerARM64.cc
+++ b/dev/kernel/HALKit/ARM64/HalTimerARM64.cc
@@ -12,3 +12,4 @@
 ------------------------------------------- */
 
 #include <ArchKit/ArchKit.h>
+#include <KernelKit/Timer.h>
\ No newline at end of file
diff --git a/dev/kernel/HALKit/ARM64/Paging.h b/dev/kernel/HALKit/ARM64/Paging.h
index 2eb02bc1..88eedcd8 100644
--- a/dev/kernel/HALKit/ARM64/Paging.h
+++ b/dev/kernel/HALKit/ARM64/Paging.h
@@ -12,6 +12,8 @@
 
 ------------------------------------------------------- */
 
+#ifdef __NE_ARM64__
+
 #include <NewKit/Defines.h>
 
 #ifndef kPageMax
@@ -101,3 +103,5 @@ typedef HAL::PDE_4KB PDE;
 }  // namespace Kernel
 
 EXTERN_C void hal_flush_tlb();
+
+#endif  // __NE_ARM64__
\ No newline at end of file
diff --git a/dev/kernel/HALKit/ARM64/Processor.h b/dev/kernel/HALKit/ARM64/Processor.h
index 9f16d8f5..f52b854f 100644
--- a/dev/kernel/HALKit/ARM64/Processor.h
+++ b/dev/kernel/HALKit/ARM64/Processor.h
@@ -6,12 +6,14 @@
 
 #pragma once
 
+#ifdef __NE_ARM64__
+
 #include <FirmwareKit/Handover.h>
 #include <NewKit/Array.h>
 #include <NewKit/Defines.h>
 #include <NewKit/Utils.h>
 
-#define kCPUBackendName "ARMv8"
+#define kCPUBackendName "aarch64"
 
 namespace Kernel::HAL {
 struct PACKED Register64 final {
@@ -21,11 +23,11 @@ struct PACKED Register64 final {
 
 /// @brief Memory Manager mapping flags.
 enum {
-  kMMFlagsPresent = 1 << 0,
-  kMMFlagsWr      = 1 << 1,
-  kMMFlagsUser    = 1 << 2,
-  kMMFlagsNX      = 1 << 3,
-  kMMFlagsPCD     = 1 << 4,
+  kMMFlagsInvalid = 1 << 0,
+  kMMFlagsPresent = 1 << 1,
+  kMMFlagsWr      = 1 << 2,
+  kMMFlagsUser    = 1 << 3,
+  kMMFlagsNX      = 1 << 4,
   kMMFlagsCount   = 4,
 };
 
@@ -62,16 +64,6 @@ inline Void rt_halt() noexcept {
   }
 }
 
-template <typename DataKind>
-inline void hal_dma_write(UIntPtr address, DataKind value) {
-  *reinterpret_cast<volatile DataKind*>(address) = value;
-}
-
-template <typename DataKind>
-inline DataKind hal_dma_read(UIntPtr address) {
-  return *reinterpret_cast<volatile DataKind*>(address);
-}
-
 inline Void hal_wfi(Void) {
   asm volatile("wfi");
 }
@@ -80,6 +72,8 @@ inline Void hal_wfi(Void) {
 inline Kernel::VoidPtr kKernelBitMpStart = nullptr;
 inline Kernel::UIntPtr kKernelBitMpSize  = 0UL;
 
-inline Kernel::VoidPtr kKernelPhysicalStart = nullptr;
+inline Kernel::VoidPtr kKernelPDE = nullptr;
 
 #include <HALKit/ARM64/Paging.h>
+
+#endif  // __NE_ARM64__
\ No newline at end of file