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authorAmlal <amlal@nekernel.org>2025-04-25 13:08:33 +0200
committerAmlal <amlal@nekernel.org>2025-04-25 13:08:33 +0200
commitfb790b07aeba8e22e4190cf3e1834d11ecde6c96 (patch)
tree4cec7d1b321307b1d5935577631dae116a658a37 /dev/kernel/KernelKit/PCI/DMA.h
parent63a2d92c5dfe976175cda024ec01905d11b43738 (diff)
dev: better .clang-format, ran format command.
Signed-off-by: Amlal <amlal@nekernel.org>
Diffstat (limited to 'dev/kernel/KernelKit/PCI/DMA.h')
-rw-r--r--dev/kernel/KernelKit/PCI/DMA.h125
1 files changed, 59 insertions, 66 deletions
diff --git a/dev/kernel/KernelKit/PCI/DMA.h b/dev/kernel/KernelKit/PCI/DMA.h
index b2d3cfa8..28256389 100644
--- a/dev/kernel/KernelKit/PCI/DMA.h
+++ b/dev/kernel/KernelKit/PCI/DMA.h
@@ -1,6 +1,6 @@
/* -------------------------------------------
- Copyright (C) 2024-2025, Amlal El Mahrouss, all rights reserved.
+ Copyright (C) 2024-2025, Amlal El Mahrouss, all rights reserved.
------------------------------------------- */
@@ -12,70 +12,63 @@
#include <NewKit/OwnPtr.h>
#include <NewKit/Ref.h>
-namespace Kernel
-{
- enum class DmaKind
- {
- PCI, // Bus mastering is required to be turned on. Basiaclly a request
- // control system. 64-Bit access depends on the PAE bit and the device
- // (if Double Address Cycle is available)
- ISA, // Four DMA channels 0-3; 8 bit transfers and only a megabyte of RAM.
- Invalid,
- };
-
- class DMAWrapper final
- {
- public:
- explicit DMAWrapper() = delete;
-
- public:
- explicit DMAWrapper(nullPtr) = delete;
- explicit DMAWrapper(voidPtr Ptr, DmaKind Kind = DmaKind::PCI)
- : fAddress(Ptr), fKind(Kind)
- {
- }
-
- public:
- DMAWrapper& operator=(voidPtr Ptr);
-
- public:
- DMAWrapper& operator=(const DMAWrapper&) = default;
- DMAWrapper(const DMAWrapper&) = default;
-
- public:
- ~DMAWrapper() = default;
-
- template <class T>
- T* operator->();
-
- template <class T>
- T* Get(UIntPtr off = 0);
-
- public:
- operator bool();
- bool operator!();
-
- public:
- bool Write(UIntPtr& bit, const UInt32& offset);
- UIntPtr Read(const UInt32& offset);
- Boolean Check(UIntPtr offset) const;
-
- public:
- UIntPtr operator[](UIntPtr& offset);
-
- private:
- voidPtr fAddress{nullptr};
- DmaKind fKind{DmaKind::Invalid};
-
- private:
- friend class DMAFactory;
- };
-
- class DMAFactory final
- {
- public:
- static OwnPtr<IOBuf<Char*>> Construct(OwnPtr<DMAWrapper>& dma);
- };
-} // namespace Kernel
+namespace Kernel {
+enum class DmaKind {
+ PCI, // Bus mastering is required to be turned on. Basiaclly a request
+ // control system. 64-Bit access depends on the PAE bit and the device
+ // (if Double Address Cycle is available)
+ ISA, // Four DMA channels 0-3; 8 bit transfers and only a megabyte of RAM.
+ Invalid,
+};
+
+class DMAWrapper final {
+ public:
+ explicit DMAWrapper() = delete;
+
+ public:
+ explicit DMAWrapper(nullPtr) = delete;
+ explicit DMAWrapper(voidPtr Ptr, DmaKind Kind = DmaKind::PCI) : fAddress(Ptr), fKind(Kind) {}
+
+ public:
+ DMAWrapper& operator=(voidPtr Ptr);
+
+ public:
+ DMAWrapper& operator=(const DMAWrapper&) = default;
+ DMAWrapper(const DMAWrapper&) = default;
+
+ public:
+ ~DMAWrapper() = default;
+
+ template <class T>
+ T* operator->();
+
+ template <class T>
+ T* Get(UIntPtr off = 0);
+
+ public:
+ operator bool();
+ bool operator!();
+
+ public:
+ bool Write(UIntPtr& bit, const UInt32& offset);
+ UIntPtr Read(const UInt32& offset);
+ Boolean Check(UIntPtr offset) const;
+
+ public:
+ UIntPtr operator[](UIntPtr& offset);
+
+ private:
+ voidPtr fAddress{nullptr};
+ DmaKind fKind{DmaKind::Invalid};
+
+ private:
+ friend class DMAFactory;
+};
+
+class DMAFactory final {
+ public:
+ static OwnPtr<IOBuf<Char*>> Construct(OwnPtr<DMAWrapper>& dma);
+};
+} // namespace Kernel
#include <KernelKit/PCI/DMA.inl>