Merge pull request #81 from nekernel-org/dev

feat! breaking changes on kernel sources.

7 files changed, 276 insertions, 0 deletions

diff --git a/src/kernel/HALKit/AMD64/PCI/DMA.cc b/src/kernel/HALKit/AMD64/PCI/DMA.cc
new file mode 100644
index 00000000..809494b6
--- /dev/null
+++ b/src/kernel/HALKit/AMD64/PCI/DMA.cc
@@ -0,0 +1,72 @@
+/* ========================================
+
+  Copyright (C) 2024-2025, Amlal El Mahrouss, licensed under the Apache 2.0 license.
+
+======================================== */
+
+#include <ArchKit/ArchKit.h>
+#include <KernelKit/PCI/DMA.h>
+
+namespace Kernel {
+DMAWrapper::operator bool() {
+  return this->fAddress;
+}
+
+bool DMAWrapper::operator!() {
+  return !this->fAddress;
+}
+
+Boolean DMAWrapper::Check(UIntPtr offset) const {
+  if (!this->fAddress) return false;
+
+  if (offset == 0) return false;
+
+  kout << "[DMAWrapper::IsIn] Checking offset...\r";
+  return reinterpret_cast<UIntPtr>(this->fAddress) >= offset;
+}
+
+bool DMAWrapper::Write(UIntPtr& bit, const UInt32& offset) {
+  kout << "[DMAWrapper::Read] Checking this->fAddress...\r";
+
+  if (!this->fAddress) return false;
+
+  (Void)(kout << "[DMAWrapper::Write] Writing at address: "
+              << hex_number(reinterpret_cast<UIntPtr>(this->fAddress) + offset) << kendl);
+
+  ke_dma_write<UInt32>(reinterpret_cast<UIntPtr>(this->fAddress), offset, bit);
+
+  return true;
+}
+
+UIntPtr DMAWrapper::Read(const UInt32& offset) {
+  kout << "[DMAWrapper::Read] Checking this->fAddress...\r";
+
+  if (!this->fAddress) return ~0;
+
+  (Void)(kout << "[DMAWrapper::Write] Writing at address: "
+              << hex_number(reinterpret_cast<UIntPtr>(this->fAddress) + offset) << kendl);
+
+  return (UIntPtr) ke_dma_read<UInt32>(reinterpret_cast<UIntPtr>(this->fAddress), offset);
+}
+
+UIntPtr DMAWrapper::operator[](UIntPtr& offset) {
+  return this->Read(offset);
+}
+
+OwnPtr<IOBuf<Char*>> DMAFactory::Construct(OwnPtr<DMAWrapper>& dma) {
+  if (!dma) return {};
+
+  OwnPtr<IOBuf<Char*>> dmaOwnPtr =
+      mm_make_own_ptr<IOBuf<Char*>, char*>(reinterpret_cast<char*>(dma->fAddress));
+
+  if (!dmaOwnPtr) return {};
+
+  kout << "Returning the new OwnPtr<IOBuf<Char*>>!\r";
+  return dmaOwnPtr;
+}
+
+DMAWrapper& DMAWrapper::operator=(voidPtr Ptr) {
+  this->fAddress = Ptr;
+  return *this;
+}
+}  // namespace Kernel
diff --git a/src/kernel/HALKit/AMD64/PCI/Database.cc b/src/kernel/HALKit/AMD64/PCI/Database.cc
new file mode 100644
index 00000000..ba3e946c
--- /dev/null
+++ b/src/kernel/HALKit/AMD64/PCI/Database.cc
@@ -0,0 +1,9 @@
+/* ========================================
+
+  Copyright (C) 2024-2025, Amlal El Mahrouss, licensed under the Apache 2.0 license.
+
+======================================== */
+
+#include <KernelKit/PCI/Database.h>
+
+namespace Kernel {}
diff --git a/src/kernel/HALKit/AMD64/PCI/Device.cc b/src/kernel/HALKit/AMD64/PCI/Device.cc
new file mode 100644
index 00000000..65af2f25
--- /dev/null
+++ b/src/kernel/HALKit/AMD64/PCI/Device.cc
@@ -0,0 +1,142 @@
+/* ========================================
+
+  Copyright (C) 2024-2025, Amlal El Mahrouss, licensed under the Apache 2.0 license.
+
+======================================== */
+
+#include <ArchKit/ArchKit.h>
+#include <KernelKit/PCI/Device.h>
+
+#define PCI_BAR_IO (0x01)
+#define PCI_BAR_LOWMEM (0x02)
+#define PCI_BAR_64 (0x04)
+#define PCI_BAR_PREFETCH (0x08)
+#define PCI_ENABLE_BIT (0x80000000)
+
+static Kernel::UInt NE_PCIReadRaw(Kernel::UInt bar, Kernel::UShort bus, Kernel::UShort dev,
+                                  Kernel::UShort fun) {
+  Kernel::UInt target = PCI_ENABLE_BIT | ((Kernel::UInt) bus << 16) | ((Kernel::UInt) dev << 11) |
+                        ((Kernel::UInt) fun << 8) | (bar & 0xFC);
+
+  Kernel::HAL::rt_out32((Kernel::UShort) Kernel::PCI::PciConfigKind::ConfigAddress, target);
+
+  Kernel::HAL::rt_wait_400ns();
+
+  return Kernel::HAL::rt_in32((Kernel::UShort) Kernel::PCI::PciConfigKind::ConfigData);
+}
+
+static Kernel::Void NE_PCISetCfgTarget(Kernel::UInt bar, Kernel::UShort bus, Kernel::UShort dev,
+                                       Kernel::UShort fun) {
+  Kernel::UInt target = 0x80000000 | ((Kernel::UInt) bus << 16) | ((Kernel::UInt) dev << 11) |
+                        ((Kernel::UInt) fun << 8) | (bar & 0xFC);
+
+  Kernel::HAL::rt_out32((Kernel::UShort) Kernel::PCI::PciConfigKind::ConfigAddress, target);
+
+  Kernel::HAL::rt_wait_400ns();
+}
+
+namespace Kernel::PCI {
+Device::Device(UShort bus, UShort device, UShort func, UInt32 bar)
+    : fBus(bus), fDevice(device), fFunction(func), fBar(bar) {}
+
+Device::~Device() = default;
+
+UInt Device::Read(UInt bar, Size sz) {
+  // Ensure aligned access by masking to 4-byte boundary
+  NE_PCISetCfgTarget(bar & 0xFC, fBus, fDevice, fFunction);
+
+  // Read 4 bytes and shift out the correct value
+  UInt data = HAL::rt_in32((UShort) PciConfigKind::ConfigData);
+
+  if (sz == 4) return data;
+  if (sz == 2) return (data >> ((bar & 2) * 8)) & 0xFFFF;
+  if (sz == 1) return (data >> ((bar & 3) * 8)) & 0xFF;
+
+  return (UShort) PciConfigKind::Invalid;
+}
+
+void Device::Write(UInt bar, UIntPtr data, Size sz) {
+  NE_PCISetCfgTarget(bar & 0xFC, fBus, fDevice, fFunction);
+
+  if (sz == 4) {
+    HAL::rt_out32((UShort) PciConfigKind::ConfigAddress, (UInt) data);
+  } else if (sz == 2) {
+    UInt temp = HAL::rt_in32((UShort) PciConfigKind::ConfigData);
+
+    temp &= ~(0xFFFF << ((bar & 2) * 8));
+    temp |= (data & 0xFFFF) << ((bar & 2) * 8);
+
+    HAL::rt_out32((UShort) PciConfigKind::ConfigAddress, temp);
+  } else if (sz == 1) {
+    UInt temp = HAL::rt_in32((UShort) PciConfigKind::ConfigData);
+
+    temp &= ~(0xFF << ((bar & 3) * 8));
+    temp |= (data & 0xFF) << ((bar & 3) * 8);
+
+    HAL::rt_out32((UShort) PciConfigKind::ConfigAddress, temp);
+  }
+}
+
+UShort Device::DeviceId() {
+  return (UShort) (NE_PCIReadRaw(0x0, fBus, fDevice, fFunction) >> 16);
+}
+
+UShort Device::VendorId() {
+  return (UShort) (NE_PCIReadRaw(0x0, fBus, fDevice, fFunction) & 0xFFFF);
+}
+
+UShort Device::InterfaceId() {
+  return (UShort) (NE_PCIReadRaw(0x09, fBus, fDevice, fFunction) >> 16);
+}
+
+UChar Device::Class() {
+  return (UChar) (NE_PCIReadRaw(0x08, fBus, fDevice, fFunction) >> 24);
+}
+
+UChar Device::Subclass() {
+  return (UChar) (NE_PCIReadRaw(0x08, fBus, fDevice, fFunction) >> 16);
+}
+
+UChar Device::ProgIf() {
+  return (UChar) (NE_PCIReadRaw(0x08, fBus, fDevice, fFunction) >> 8);
+}
+
+UChar Device::HeaderType() {
+  return (UChar) (NE_PCIReadRaw(0xC, fBus, fDevice, fFunction) >> 16);
+}
+
+void Device::EnableMmio() {
+  UInt32 command = Read(0x04, sizeof(UInt32));
+  command |= (1 << 1);  // Memory Space Enable (bit 1)
+
+  Write(0x04, command, sizeof(UInt32));
+}
+
+void Device::BecomeBusMaster() {
+  UInt32 command = Read(0x04, sizeof(UInt32));
+  command |= (1 << 2);  // Bus Master Enable (bit 2)
+  Write(0x04, command, sizeof(UInt32));
+}
+
+UIntPtr Device::Bar(UInt32 bar_in) {
+  UInt32 bar = NE_PCIReadRaw(bar_in, fBus, fDevice, fFunction);
+
+  if (bar & PCI_BAR_IO) return static_cast<UIntPtr>(bar & ~0x03);
+
+  if (bar & PCI_BAR_64) {
+    UInt32 high = NE_PCIReadRaw((bar_in + 4) & ~0x03, fBus, fDevice, fFunction);
+    return (static_cast<UIntPtr>(high) << 32) | (bar & ~0x0F);
+  }
+
+  return static_cast<UIntPtr>(bar & ~0x0F);
+}
+
+UShort Device::Vendor() {
+  UShort vendor = this->VendorId();
+  return vendor;
+}
+
+Device::operator bool() {
+  return this->VendorId() != (UShort) PciConfigKind::Invalid;
+}
+}  // namespace Kernel::PCI
diff --git a/src/kernel/HALKit/AMD64/PCI/Express.cc b/src/kernel/HALKit/AMD64/PCI/Express.cc
new file mode 100644
index 00000000..2b6ba8d3
--- /dev/null
+++ b/src/kernel/HALKit/AMD64/PCI/Express.cc
@@ -0,0 +1,9 @@
+/* ========================================
+
+  Copyright (C) 2024-2025, Amlal El Mahrouss, licensed under the Apache 2.0 license.
+
+======================================== */
+
+#include <KernelKit/PCI/Express.h>
+
+namespace Kernel {}
diff --git a/src/kernel/HALKit/AMD64/PCI/IO.cc b/src/kernel/HALKit/AMD64/PCI/IO.cc
new file mode 100644
index 00000000..233c8ef2
--- /dev/null
+++ b/src/kernel/HALKit/AMD64/PCI/IO.cc
@@ -0,0 +1,7 @@
+/* ========================================
+
+  Copyright (C) 2024-2025, Amlal El Mahrouss, licensed under the Apache 2.0 license.
+
+======================================== */
+
+#include <KernelKit/PCI/IO.h>
diff --git a/src/kernel/HALKit/AMD64/PCI/Iterator.cc b/src/kernel/HALKit/AMD64/PCI/Iterator.cc
new file mode 100644
index 00000000..103ddb2c
--- /dev/null
+++ b/src/kernel/HALKit/AMD64/PCI/Iterator.cc
@@ -0,0 +1,30 @@
+/* ========================================
+
+  Copyright (C) 2024-2025, Amlal El Mahrouss, licensed under the Apache 2.0 license.
+
+======================================== */
+
+#include <KernelKit/PCI/Iterator.h>
+
+namespace Kernel::PCI {
+Iterator::Iterator(const Types::PciDeviceKind type, UInt32 bar) {
+  // probe devices.
+  for (Int32 bus = 0; bus < NE_BUS_COUNT; ++bus) {
+    for (Int32 device = 0; device < NE_DEVICE_COUNT; ++device) {
+      for (Int32 function = 0; function < NE_FUNCTION_COUNT; ++function) {
+        Device dev(bus, device, function, bar);
+
+        if (dev.Class() == type) {
+          fDevices[bus] = dev;
+        }
+      }
+    }
+  }
+}
+
+Iterator::~Iterator() {}
+
+Ref<PCI::Device> Iterator::operator[](const Size& at) {
+  return fDevices[at];
+}
+}  // namespace Kernel::PCI
diff --git a/src/kernel/HALKit/AMD64/PCI/PCI.cc b/src/kernel/HALKit/AMD64/PCI/PCI.cc
new file mode 100644
index 00000000..a8c48fb9
--- /dev/null
+++ b/src/kernel/HALKit/AMD64/PCI/PCI.cc
@@ -0,0 +1,7 @@
+/* ========================================
+
+  Copyright (C) 2024-2025, Amlal El Mahrouss, licensed under the Apache 2.0 license.
+
+======================================== */
+
+#include <KernelKit/PCI/PCI.h>