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-rw-r--r--dev/Kernel/ArchKit/ArchKit.h12
-rw-r--r--dev/Kernel/HALKit/AMD64/Storage/AHCI+Generic.cc7
-rw-r--r--dev/Kernel/HALKit/ARM64/HalApplicationProcessor.cc49
-rw-r--r--dev/Kernel/HALKit/ARM64/Processor.h4
-rw-r--r--dev/Kernel/StorageKit/AHCI.h5
5 files changed, 45 insertions, 32 deletions
diff --git a/dev/Kernel/ArchKit/ArchKit.h b/dev/Kernel/ArchKit/ArchKit.h
index dd284f5d..04fc5bf6 100644
--- a/dev/Kernel/ArchKit/ArchKit.h
+++ b/dev/Kernel/ArchKit/ArchKit.h
@@ -47,20 +47,20 @@ namespace NeOS
/// @param base the base address.
/// @param reg the register.
/// @param value the write to write on it.
- template <typename WordLength>
- inline Void ke_dma_write(WordLength base, WordLength reg, WordLength value) noexcept
+ template <typename DataKind>
+ inline Void ke_dma_write(UIntPtr base, DataKind reg, DataKind value) noexcept
{
- *(volatile WordLength*)(base + reg) = value;
+ *(volatile DataKind*)(base + reg) = value;
}
/// @brief read from mapped memory register.
/// @param base base address
/// @param reg the register.
/// @return the value inside the register.
- template <typename WordLength>
- inline UInt32 ke_dma_read(WordLength base, WordLength reg) noexcept
+ template <typename DataKind>
+ inline UInt32 ke_dma_read(UIntPtr base, DataKind reg) noexcept
{
- return *(volatile WordLength*)((UInt64)base + reg);
+ return *(volatile DataKind*)(base + reg);
}
namespace HAL
diff --git a/dev/Kernel/HALKit/AMD64/Storage/AHCI+Generic.cc b/dev/Kernel/HALKit/AMD64/Storage/AHCI+Generic.cc
index cfbeeeb2..51db8054 100644
--- a/dev/Kernel/HALKit/AMD64/Storage/AHCI+Generic.cc
+++ b/dev/Kernel/HALKit/AMD64/Storage/AHCI+Generic.cc
@@ -244,8 +244,7 @@ STATIC Bool drv_std_init_ahci(UInt16& pi, BOOL atapi)
UInt32 ports_implemented = mem_ahci->Pi;
UInt16 ahci_index = 0;
- kSATAPortsImplemented = ports_implemented;
- pi = kSATAPortsImplemented;
+ pi = ports_implemented;
const UInt16 kMaxPortsImplemented = kSATAPortCnt;
const UInt32 kSATASignature = kSATASig;
@@ -309,6 +308,8 @@ namespace NeOS
UInt16 pi = 0;
return drv_std_init_ahci(pi, atapi);
+ kSATAPortsImplemented = pi;
+
return pi;
}
@@ -330,7 +331,7 @@ namespace NeOS
},
nullptr);
- device.SetPi(kSATAPortsImplemented);
+ device.SetPortsImplemented(kSATAPortsImplemented);
device.SetIndex(drv_index);
return ErrorOr<AHCIDeviceInterface>(device);
diff --git a/dev/Kernel/HALKit/ARM64/HalApplicationProcessor.cc b/dev/Kernel/HALKit/ARM64/HalApplicationProcessor.cc
index 5ef13a3b..660af502 100644
--- a/dev/Kernel/HALKit/ARM64/HalApplicationProcessor.cc
+++ b/dev/Kernel/HALKit/ARM64/HalApplicationProcessor.cc
@@ -45,57 +45,68 @@ namespace NeOS
{
while (YES)
;
+
+ dbg_break_point();
}
Void mp_setup_gic_el0(Void)
{
// enable distributor.
- HAL::hal_mmio_write(GICD_BASE + GICD_CTLR, YES);
+ ke_dma_write<UInt32>(GICD_BASE, GICD_CTLR, YES);
- UInt32 gicc_ctlr = HAL::hal_mmio_read<UInt32>(GICC_BASE + GICC_CTLR);
+ UInt32 gicc_ctlr = ke_dma_read<UInt32>(GICC_BASE, GICC_CTLR);
const auto kEnableSignalInt = YES;
gicc_ctlr |= kEnableSignalInt; // Enable signaling of interrupts
gicc_ctlr |= (kEnableSignalInt << 1); // Allow Group 1 interrupts in EL0
- HAL::hal_mmio_write(GICC_BASE + GICC_CTLR, gicc_ctlr);
+ ke_dma_write<UInt32>(GICC_BASE, GICC_CTLR, gicc_ctlr);
// Set priority mask (accept all priorities)
- HAL::hal_mmio_write(GICC_BASE + GICC_PMR, 0xFF);
+ ke_dma_write<UInt32>(GICC_BASE, GICC_PMR, 0xFF);
- UInt32 icfgr = HAL::hal_mmio_read<UInt32>(GICD_BASE + GICD_ICFGR + (32 / 16) * 4);
+ UInt32 icfgr = ke_dma_read<UInt32>(GICD_BASE, GICD_ICFGR + (0x20 / 0x10) * 4);
icfgr |= (0x2 << ((32 % 16) * 2)); // Edge-triggered
- HAL::hal_mmio_write(GICD_BASE + GICD_ICFGR + (32 / 16) * 4, icfgr);
+ ke_dma_write<UInt32>(GICD_BASE, GICD_ICFGR + (0x20 / 0x10) * 4, icfgr);
// Target interrupt 32 to CPU 1
- HAL::hal_mmio_write(GICD_BASE + GICD_ITARGETSR + (32 / 4) * 4, 0x2 << ((32 % 4) * 8));
+ ke_dma_write<UInt32>(GICD_BASE, GICD_ITARGETSR + (0x20 / 0x04) * 4, 0x2 << ((32 % 4) * 8));
// Set interrupt 32 priority to lowest (0xFF)
- HAL::hal_mmio_write(GICD_BASE + GICD_IPRIORITYR + (32 / 4) * 4, 0xFF << ((32 % 4) * 8));
+ ke_dma_write<UInt32>(GICD_BASE, GICD_IPRIORITYR + (0x20 / 0x04) * 4, 0xFF << ((32 % 4) * 8));
// Enable interrupt 32 for AP.
- HAL::hal_mmio_write(GICD_BASE + GICD_ISENABLER + (32 / 32) * 4, 0x01 << (32 % 32));
-
- kout << "AP's GIC configured in ISR 32." << kendl;
+ ke_dma_write<UInt32>(GICD_BASE, GICD_ISENABLER + 4, 0x01);
}
BOOL mp_handle_gic_interrupt_el0(Void)
{
// Read the interrupt ID
- UInt32 interrupt_id = HAL::hal_mmio_read<UInt32>(GICC_BASE + GICC_IAR);
+ UInt32 interrupt_id = ke_dma_read<UInt32>(GICC_BASE, GICC_IAR);
// Check if it's a valid interrupt (not spurious)
if ((interrupt_id & 0x3FF) < 1020)
{
- kout << "Handling interrupt for AP: " << (interrupt_id & 0x3FF) << kendl;
-
- // TODO: Handle code here.
-
- // End the interrupt
-
- HAL::hal_mmio_write(GICC_BASE + GICC_EOIR, interrupt_id);
+ auto interrupt = interrupt_id & 0x3FF;
+
+ const UInt16 kInterruptScheduler = 0x20;
+
+ kout << "Handling interrupt for AP: " << interrupt << kendl;
+
+ switch (interrupt)
+ {
+ case kInterruptScheduler: {
+ ke_dma_write<UInt32>(GICC_BASE, GICC_EOIR, interrupt_id);
+ UserProcessHelper::StartScheduling();
+ break;
+ }
+ default: {
+ ke_dma_write<UInt32>(GICC_BASE, GICC_EOIR, interrupt_id);
+ break;
+ }
+ }
return YES;
}
diff --git a/dev/Kernel/HALKit/ARM64/Processor.h b/dev/Kernel/HALKit/ARM64/Processor.h
index e79a99c7..940cfbe9 100644
--- a/dev/Kernel/HALKit/ARM64/Processor.h
+++ b/dev/Kernel/HALKit/ARM64/Processor.h
@@ -66,13 +66,13 @@ namespace NeOS::HAL
}
template <typename DataKind>
- inline void hal_mmio_write(UIntPtr address, DataKind value)
+ inline void hal_dma_write(UIntPtr address, DataKind value)
{
*reinterpret_cast<volatile DataKind*>(address) = value;
}
template <typename DataKind>
- inline DataKind hal_mmio_read(UIntPtr address)
+ inline DataKind hal_dma_read(UIntPtr address)
{
return *reinterpret_cast<volatile DataKind*>(address);
}
diff --git a/dev/Kernel/StorageKit/AHCI.h b/dev/Kernel/StorageKit/AHCI.h
index 2eb0912b..43e81ba0 100644
--- a/dev/Kernel/StorageKit/AHCI.h
+++ b/dev/Kernel/StorageKit/AHCI.h
@@ -27,12 +27,12 @@ namespace NeOS
const Char* Name() const override;
- const UInt16& GetPi()
+ const UInt16& GetPortsImplemented()
{
return this->fPortsImplemented;
}
- Void SetPi(const UInt16& pi)
+ Void SetPortsImplemented(const UInt16& pi)
{
MUST_PASS(pi > 0);
this->fPortsImplemented = pi;
@@ -45,6 +45,7 @@ namespace NeOS
Void SetIndex(const UInt32& drv)
{
+ MUST_PASS(MountpointInterface::kDriveIndexInvalid != drv);
this->fDriveIndex = drv;
}
generated by cgit v1.2.3 (git 2.39.1) at 2026-03-13 04:55:11 +0000