diff options
Diffstat (limited to 'dev/kernel/HALKit')
| -rw-r--r-- | dev/kernel/HALKit/AMD64/PCI/Device.cc | 27 | ||||
| -rw-r--r-- | dev/kernel/HALKit/AMD64/Storage/AHCI+Generic.cc | 41 |
2 files changed, 19 insertions, 49 deletions
diff --git a/dev/kernel/HALKit/AMD64/PCI/Device.cc b/dev/kernel/HALKit/AMD64/PCI/Device.cc index 9c27cb10..7ad19360 100644 --- a/dev/kernel/HALKit/AMD64/PCI/Device.cc +++ b/dev/kernel/HALKit/AMD64/PCI/Device.cc @@ -7,14 +7,15 @@ #include <ArchKit/ArchKit.h> #include <KernelKit/PCI/Device.h> -#define PCI_BAR_IO 0x01 -#define PCI_BAR_LOWMEM 0x02 -#define PCI_BAR_64 0x04 -#define PCI_BAR_PREFETCH 0x08 +#define PCI_BAR_IO (0x01) +#define PCI_BAR_LOWMEM (0x02) +#define PCI_BAR_64 (0x04) +#define PCI_BAR_PREFETCH (0x08) +#define PCI_ENABLE_BIT (0x80000000) -Kernel::UInt NE_PCIReadRaw(Kernel::UInt bar, Kernel::UShort bus, Kernel::UShort dev, Kernel::UShort fun) +static Kernel::UInt NE_PCIReadRaw(Kernel::UInt bar, Kernel::UShort bus, Kernel::UShort dev, Kernel::UShort fun) { - Kernel::UInt target = 0x80000000 | ((Kernel::UInt)bus << 16) | + Kernel::UInt target = PCI_ENABLE_BIT | ((Kernel::UInt)bus << 16) | ((Kernel::UInt)dev << 11) | ((Kernel::UInt)fun << 8) | (bar & 0xFC); @@ -26,7 +27,7 @@ Kernel::UInt NE_PCIReadRaw(Kernel::UInt bar, Kernel::UShort bus, Kernel::UShort return Kernel::HAL::rt_in32((Kernel::UShort)Kernel::PCI::PciConfigKind::ConfigData); } -void NE_PCISetCfgTarget(Kernel::UInt bar, Kernel::UShort bus, Kernel::UShort dev, Kernel::UShort fun) +static Kernel::Void NE_PCISetCfgTarget(Kernel::UInt bar, Kernel::UShort bus, Kernel::UShort dev, Kernel::UShort fun) { Kernel::UInt target = 0x80000000 | ((Kernel::UInt)bus << 16) | ((Kernel::UInt)dev << 11) | ((Kernel::UInt)fun << 8) | @@ -70,20 +71,26 @@ namespace Kernel::PCI NE_PCISetCfgTarget(bar & 0xFC, fBus, fDevice, fFunction); if (sz == 4) - HAL::rt_out32((UShort)PciConfigKind::ConfigData, (UInt)data); + { + HAL::rt_out32((UShort)PciConfigKind::ConfigAddress, (UInt)data); + } else if (sz == 2) { UInt temp = HAL::rt_in32((UShort)PciConfigKind::ConfigData); + temp &= ~(0xFFFF << ((bar & 2) * 8)); temp |= (data & 0xFFFF) << ((bar & 2) * 8); - HAL::rt_out32((UShort)PciConfigKind::ConfigData, temp); + + HAL::rt_out32((UShort)PciConfigKind::ConfigAddress, temp); } else if (sz == 1) { UInt temp = HAL::rt_in32((UShort)PciConfigKind::ConfigData); + temp &= ~(0xFF << ((bar & 3) * 8)); temp |= (data & 0xFF) << ((bar & 3) * 8); - HAL::rt_out32((UShort)PciConfigKind::ConfigData, temp); + + HAL::rt_out32((UShort)PciConfigKind::ConfigAddress, temp); } } diff --git a/dev/kernel/HALKit/AMD64/Storage/AHCI+Generic.cc b/dev/kernel/HALKit/AMD64/Storage/AHCI+Generic.cc index e9c967dc..68a5b051 100644 --- a/dev/kernel/HALKit/AMD64/Storage/AHCI+Generic.cc +++ b/dev/kernel/HALKit/AMD64/Storage/AHCI+Generic.cc @@ -15,7 +15,6 @@ * */ -#include "NewKit/Defines.h" #include <KernelKit/DeviceMgr.h> #include <KernelKit/DriveMgr.h> #include <KernelKit/ProcessScheduler.h> @@ -70,7 +69,7 @@ STATIC Void drv_compute_disk_ahci() noexcept; namespace AHCI::Detail { template <typename RetType> - RetType* ahci_align_address(RetType* address, Int32 alignement) + STATIC RetType* ahci_align_address(RetType* address, Int32 alignement) { if (!address) return nullptr; @@ -91,7 +90,7 @@ STATIC Void drv_compute_disk_ahci() noexcept const UInt16 kSzIdent = 256; /// Push it to the stack - UInt16* identify_data ATTRIBUTE(aligned(kib_cast(1))) = AHCI::Detail::ahci_align_address<UInt16>(new UInt16[kSzIdent], kib_cast(1)); + UInt16* identify_data = AHCI::Detail::ahci_align_address<UInt16>(new UInt16[kSzIdent], kib_cast(1)); /// Send AHCI command for identification. drv_std_input_output_ahci<NO, YES, YES>(0, (UInt8*)identify_data, kAHCISectorSize, kSzIdent); @@ -198,8 +197,6 @@ STATIC Void drv_std_input_output_ahci(UInt64 lba, UInt8* buffer, SizeT sector_sz volatile FisRegH2D* h2d_fis = (volatile FisRegH2D*)(&command_table->Cfis[0]); - rt_set_memory((FisRegH2D*)h2d_fis, 0, sizeof(FisRegH2D)); - h2d_fis->FisType = kFISTypeRegH2D; h2d_fis->CmdOrCtrl = CommandOrCTRL; h2d_fis->Command = (Identify ? (kAHCICmdIdentify) : (Write ? kAHCICmdWriteDmaEx : kAHCICmdReadDmaEx)); @@ -287,40 +284,6 @@ STATIC BOOL ahci_enable_and_probe() break; } - // Command engine stopped, remap the AHCI port. - - auto port = &kSATAHba->Ports[kSATAIndex]; - - // Relocate Command List Base. - - VoidPtr const kAHCIBasePtr = AHCI::Detail::ahci_align_address<Void>(mm_new_heap(kib_cast(64), YES, NO, 0), kib_cast(1)); - UIntPtr const kAHCIBaseAddress = reinterpret_cast<UIntPtr>(kAHCIBasePtr); - - port->Clb = kAHCIBaseAddress + (kSATAIndex << 10); - port->Clbu = 0; - - // clean it. - rt_set_memory(reinterpret_cast<VoidPtr>(port->Clb), 0, 1024); - - // Relocate Frame Info Structure now. - - port->Fb = (UInt32)(UIntPtr)(UIntPtr*)AHCI::Detail::ahci_align_address<UInt32>((UInt32*)(kAHCIBaseAddress + (kSATAPortCnt << 10) + (kSATAIndex << 10)), kib_cast(1)); - port->Fbu = 0; - - // clean it. - rt_set_memory(reinterpret_cast<VoidPtr>(port->Fb), 0, 256); - - volatile HbaCmdHeader* cmd_hdr = reinterpret_cast<volatile HbaCmdHeader*>(port->Clb); - - for (Int32 i = 0; i < kSATAPortCnt; i++) - { - cmd_hdr[i].Prdtl = 8; - cmd_hdr[i].Ctba = (UInt32)(UIntPtr)(UIntPtr*)AHCI::Detail::ahci_align_address<UInt32>((UInt32*)(kAHCIBaseAddress + (40 << 10) + (kSATAPortCnt << 10) + (kSATAIndex << 10)), kib_cast(1)); - cmd_hdr[i].Ctbau = 0; - - rt_set_memory(reinterpret_cast<VoidPtr>(cmd_hdr[i].Ctba), 0, 256); - } - // Now we are ready. kSATAHba->Ports[kSATAIndex].Cmd |= kHBAPxCmdFre; |