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-rw-r--r--dev/kernel/HALKit/AMD64/HalApplicationProcessor.cc16
-rw-r--r--dev/kernel/HALKit/AMD64/HalDebugProtocol.cc (renamed from dev/kernel/HALKit/AMD64/HalDebugPort.cc)6
-rw-r--r--dev/kernel/HALKit/AMD64/HalKernelMain.cc20
3 files changed, 21 insertions, 21 deletions
diff --git a/dev/kernel/HALKit/AMD64/HalApplicationProcessor.cc b/dev/kernel/HALKit/AMD64/HalApplicationProcessor.cc
index cb1ec59b..3e10d577 100644
--- a/dev/kernel/HALKit/AMD64/HalApplicationProcessor.cc
+++ b/dev/kernel/HALKit/AMD64/HalApplicationProcessor.cc
@@ -117,7 +117,6 @@ EXTERN_C BOOL mp_register_task(HAL::StackFramePtr stack_frame, ThreadID thrdid)
if (!stack_frame) return NO;
kHWThread[thrdid].mFramePtr = stack_frame;
- kHWThread[thrdid].mThreadID = thrdid;
HardwareThreadScheduler::The()[thrdid].Leak()->Busy(NO);
@@ -165,17 +164,18 @@ Void mp_init_cores(VoidPtr vendor_ptr) noexcept {
kSMPInterrupt = 0;
kSMPCount = 0;
- UInt32 lo = 0, hi = 0;
+ UInt32 lo = 0U, hi = 0U;
+
+ hal_get_msr(APIC_BASE_MSR, &lo, &hi);
- hal_get_msr(0x1B, &lo, &hi);
UInt64 apic_base = ((UInt64) hi << 32) | lo;
- apic_base |= 0x800; // enable bit
+ apic_base |= APIC_BASE_MSR_ENABLE; // Enable APIC.
lo = apic_base & 0xFFFFFFFF;
hi = apic_base >> 32;
- hal_set_msr(0x1B, lo, hi);
+ hal_set_msr(APIC_BASE_MSR, lo, hi);
kApicBaseAddress = apic_base & 0xFFFFF000;
@@ -184,7 +184,7 @@ Void mp_init_cores(VoidPtr vendor_ptr) noexcept {
controller.Write(LAPIC_REG_ENABLE, 0);
controller.Write(LAPIC_REG_SPURIOUS, 0x1FF); // Enable bit, spurious interrupt vector register.
controller.Write(LAPIC_REG_TIMER_DIV, 0b0011);
- controller.Write(LAPIC_REG_TIMER_LVT, 32 | (1 << 17));
+ controller.Write(LAPIC_REG_TIMER_LVT, 0x20 | (1 << 17));
controller.Write(LAPIC_REG_TIMER_INITCNT, 1000000);
volatile UInt8* entry_ptr = reinterpret_cast<volatile UInt8*>(kMADTBlock->List);
@@ -202,6 +202,8 @@ Void mp_init_cores(VoidPtr vendor_ptr) noexcept {
if (entry_struct->Flags & 0x1) {
kAPICLocales[kSMPCount] = entry_struct->ProcessorID;
+ kHWThread[kSMPCount].mThreadID = kAPICLocales[kSMPCount];
+
++kSMPCount;
kout << "Kind: LAPIC: ON\r";
@@ -212,7 +214,7 @@ Void mp_init_cores(VoidPtr vendor_ptr) noexcept {
kout << "Kind: LAPIC: OFF\r";
}
} else {
- kout << "Kind: UNKNOWN: ?\r";
+ kout << "Kind: UNKNOWN\r";
}
entry_ptr += length;
diff --git a/dev/kernel/HALKit/AMD64/HalDebugPort.cc b/dev/kernel/HALKit/AMD64/HalDebugProtocol.cc
index 4e0e2b7f..8a1249ea 100644
--- a/dev/kernel/HALKit/AMD64/HalDebugPort.cc
+++ b/dev/kernel/HALKit/AMD64/HalDebugProtocol.cc
@@ -13,8 +13,4 @@
// after that we have start of additional data.
-namespace Kernel {
-Void rt_debug_listen(KernelDebugHeader* the_hdr) noexcept {
- NE_UNUSED(the_hdr);
-}
-} // namespace Kernel
+namespace Kernel {} // namespace Kernel
diff --git a/dev/kernel/HALKit/AMD64/HalKernelMain.cc b/dev/kernel/HALKit/AMD64/HalKernelMain.cc
index 97043227..e7337e62 100644
--- a/dev/kernel/HALKit/AMD64/HalKernelMain.cc
+++ b/dev/kernel/HALKit/AMD64/HalKernelMain.cc
@@ -23,11 +23,13 @@ EXTERN_C Kernel::VoidPtr kInterruptVectorTable[];
/// @brief Kernel init function.
/// @param handover_hdr Handover boot header.
EXTERN_C Int32 hal_init_platform(Kernel::HEL::BootInfoHeader* handover_hdr) {
+ using namespace Kernel;
+
if (handover_hdr->f_Magic != kHandoverMagic && handover_hdr->f_Version != kHandoverVersion) {
return kEfiFail;
}
- Kernel::HAL::rt_sti();
+ HAL::rt_sti();
kHandoverHeader = handover_hdr;
@@ -46,9 +48,9 @@ EXTERN_C Int32 hal_init_platform(Kernel::HEL::BootInfoHeader* handover_hdr) {
/* INITIALIZE BIT MAP. */
/************************************** */
- kKernelBitMpSize = kHandoverHeader->f_BitMapSize;
- kKernelBitMpStart = reinterpret_cast<Kernel::VoidPtr>(
- reinterpret_cast<Kernel::UIntPtr>(kHandoverHeader->f_BitMapStart));
+ kKernelBitMpSize = kHandoverHeader->f_BitMapSize;
+ kKernelBitMpStart =
+ reinterpret_cast<VoidPtr>(reinterpret_cast<UIntPtr>(kHandoverHeader->f_BitMapStart));
/************************************** */
/* INITIALIZE GDT AND SEGMENTS. */
@@ -62,7 +64,7 @@ EXTERN_C Int32 hal_init_platform(Kernel::HEL::BootInfoHeader* handover_hdr) {
kKernelTSS.fIopb = sizeof(HAL::Detail::NE_TSS);
/* The GDT, mostly descriptors for user and kernel segments. */
- STATIC Kernel::HAL::Detail::NE_GDT_ENTRY ALIGN(0x08) kGDTArray[kGDTEntriesCount] = {
+ STATIC HAL::Detail::NE_GDT_ENTRY ALIGN(0x08) kGDTArray[kGDTEntriesCount] = {
{.fLimitLow = 0,
.fBaseLow = 0,
.fBaseMid = 0,
@@ -112,13 +114,13 @@ EXTERN_C Int32 hal_init_platform(Kernel::HEL::BootInfoHeader* handover_hdr) {
kGDTArray[4].fBaseHigh = 0;
// Load memory descriptors.
- Kernel::HAL::Register64 gdt_reg;
+ HAL::Register64 gdt_reg;
- gdt_reg.Base = reinterpret_cast<Kernel::UIntPtr>(kGDTArray);
- gdt_reg.Limit = (sizeof(Kernel::HAL::Detail::NE_GDT_ENTRY) * kGDTEntriesCount) - 1;
+ gdt_reg.Base = reinterpret_cast<UIntPtr>(kGDTArray);
+ gdt_reg.Limit = (sizeof(HAL::Detail::NE_GDT_ENTRY) * kGDTEntriesCount) - 1;
//! GDT will load hal_read_init after it successfully loads the segments.
- Kernel::HAL::GDTLoader gdt_loader;
+ HAL::GDTLoader gdt_loader;
gdt_loader.Load(gdt_reg);
return kEfiFail;