1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
|
/* -------------------------------------------
Copyright (C) 2024-2025, Amlal El Mahrouss, all rights reserved.
File: HalCPU.cc
Purpose: Platform processor routines.
------------------------------------------- */
#include <HALKit/AMD64/Paging.h>
#include <HALKit/AMD64/Processor.h>
/**
* @file HalCPU.cc
* @brief Common CPU API.
*/
namespace Kernel::HAL
{
Void hal_set_msr(UInt32 msr, UInt32 lo, UInt32 hi) noexcept
{
asm volatile("wrmsr"
:
: "a"(lo), "d"(hi), "c"(msr));
}
Void lrt_hal_out8(UInt16 port, UInt8 value)
{
asm volatile("outb %%al, %1"
:
: "a"(value), "Nd"(port)
: "memory");
}
Void lrt_hal_out16(UInt16 port, UInt16 value)
{
asm volatile("outw %%ax, %1"
:
: "a"(value), "Nd"(port)
: "memory");
}
Void lrt_hal_out32(UInt16 port, UInt32 value)
{
asm volatile("outl %%eax, %1"
:
: "a"(value), "Nd"(port)
: "memory");
}
UInt8 lrt_hal_in8(UInt16 port)
{
UInt8 value = 0UL;
asm volatile("inb %1, %%al"
: "=a"(value)
: "Nd"(port)
: "memory");
return value;
}
UInt16 lrt_hal_in16(UInt16 port)
{
UInt16 value = 0UL;
asm volatile("inw %1, %%ax"
: "=a"(value)
: "Nd"(port)
: "memory");
return value;
}
UInt32 lrt_hal_in32(UInt16 port)
{
UInt32 value = 0UL;
asm volatile("inl %1, %%eax"
: "=a"(value)
: "Nd"(port)
: "memory");
return value;
}
Void rt_halt()
{
asm volatile("hlt");
}
Void rt_cli()
{
asm volatile("cli");
}
Void rt_sti()
{
asm volatile("sti");
}
Void rt_cld()
{
asm volatile("cld");
}
Void rt_std()
{
asm volatile("std");
}
} // namespace Kernel::HAL
|