blob: b2d3cfa822583f1dd21699521b3d3158006cda03 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
|
/* -------------------------------------------
Copyright (C) 2024-2025, Amlal El Mahrouss, all rights reserved.
------------------------------------------- */
#pragma once
#include <KernelKit/DeviceMgr.h>
#include <KernelKit/PCI/Device.h>
#include <NewKit/Array.h>
#include <NewKit/OwnPtr.h>
#include <NewKit/Ref.h>
namespace Kernel
{
enum class DmaKind
{
PCI, // Bus mastering is required to be turned on. Basiaclly a request
// control system. 64-Bit access depends on the PAE bit and the device
// (if Double Address Cycle is available)
ISA, // Four DMA channels 0-3; 8 bit transfers and only a megabyte of RAM.
Invalid,
};
class DMAWrapper final
{
public:
explicit DMAWrapper() = delete;
public:
explicit DMAWrapper(nullPtr) = delete;
explicit DMAWrapper(voidPtr Ptr, DmaKind Kind = DmaKind::PCI)
: fAddress(Ptr), fKind(Kind)
{
}
public:
DMAWrapper& operator=(voidPtr Ptr);
public:
DMAWrapper& operator=(const DMAWrapper&) = default;
DMAWrapper(const DMAWrapper&) = default;
public:
~DMAWrapper() = default;
template <class T>
T* operator->();
template <class T>
T* Get(UIntPtr off = 0);
public:
operator bool();
bool operator!();
public:
bool Write(UIntPtr& bit, const UInt32& offset);
UIntPtr Read(const UInt32& offset);
Boolean Check(UIntPtr offset) const;
public:
UIntPtr operator[](UIntPtr& offset);
private:
voidPtr fAddress{nullptr};
DmaKind fKind{DmaKind::Invalid};
private:
friend class DMAFactory;
};
class DMAFactory final
{
public:
static OwnPtr<IOBuf<Char*>> Construct(OwnPtr<DMAWrapper>& dma);
};
} // namespace Kernel
#include <KernelKit/PCI/DMA.inl>
|
