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authorAmlal El Mahrouss <amlal.elmahrouss@icloud.com>2024-01-13 13:00:40 +0100
committerAmlal El Mahrouss <amlal.elmahrouss@icloud.com>2024-01-13 13:00:40 +0100
commitb11aa11199cfe873946bc032e031f139348eafd6 (patch)
tree9360a92d9d670d3b51ab7ff4337f7ab624689e10
parentddaa28767b85743c6231a9a59a75c1bdc19f7d94 (diff)
PDF: Worked on DSP/CPU specs.
Signed-off-by: Amlal El Mahrouss <amlal.elmahrouss@icloud.com>
-rw-r--r--PDF/HAVP17
-rw-r--r--PDF/VNRP24
2 files changed, 41 insertions, 0 deletions
diff --git a/PDF/HAVP b/PDF/HAVP
new file mode 100644
index 0000000..438ac7c
--- /dev/null
+++ b/PDF/HAVP
@@ -0,0 +1,17 @@
+HAVP - Harvard Audio/Video Processor
+
+- Encoding: IBAD
+
+- Data path = 24
+ - 16: sound data
+ - 8: information data
+
+- Register size: 32
+- Store strategy: shift registers.
+- Standard registers: [ r0, r9 ]
+- Floating point registers: [ f0, f2 ]
+- Builtin SRAM: 512kb
+
+Objective:
+ - Not pricey
+ - And usable/prorammable. \ No newline at end of file
diff --git a/PDF/VNRP b/PDF/VNRP
new file mode 100644
index 0000000..c1b42a2
--- /dev/null
+++ b/PDF/VNRP
@@ -0,0 +1,24 @@
+VNRP - Von Neumann, RISC Processor
+
+- Encoding = RegToReg, Imm, Syscall, Jump, NoArgs
+
+- Data path = 128-bit (register data)
+- Addressing = 58-bit physical address size.
+
+- Registers (128-bit) = r0, r19
+- Float/Vector registers (128-bit) = f0, f9
+
+- Out of order (superscalar also added to the equation) = Yes
+- Superscalar = Yes
+
+- L1 cache: 16kb (8 instr, 8 data)
+- L2 cache: 1024kb (512 instr, 512 data)
+
+- Clock speed: 1 Ghz
+
+Objective:
+ - Not pricey
+ - And usable/prorammable.
+
+Problems:
+ - RAM \ No newline at end of file