diff options
| author | Amlal El Mahrouss <amlal@nekernel.org> | 2025-07-31 08:57:14 +0100 |
|---|---|---|
| committer | Amlal El Mahrouss <amlal@nekernel.org> | 2025-07-31 08:57:14 +0100 |
| commit | 1891d7343a9ac25ab157c4495581a0fcbd7fbcbf (patch) | |
| tree | c6da72fdf5db30c67c28e968883f869ee57600d0 /lib/ppc64/processor.h | |
| parent | 18d33e155d2f56e59eb49dadbb30ab2f7ac3e852 (diff) | |
feat! refactor NeBoot for NeKernel.org v1.0.0
Signed-off-by: Amlal El Mahrouss <amlal@nekernel.org>
Diffstat (limited to 'lib/ppc64/processor.h')
| -rw-r--r-- | lib/ppc64/processor.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/lib/ppc64/processor.h b/lib/ppc64/processor.h index bbeb0c9..3e6e04d 100644 --- a/lib/ppc64/processor.h +++ b/lib/ppc64/processor.h @@ -1023,29 +1023,29 @@ struct pt_regs { /* * 405EX/EXr CHIP_21 Errata */ -#ifdef CONFIG_CB_4xx_CHIP_21_405EX_SECURITY -#define CONFIG_CB_4xx_CHIP_21_ERRATA +#ifdef CONFIG_NB_4xx_CHIP_21_405EX_SECURITY +#define CONFIG_NB_4xx_CHIP_21_ERRATA #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX1_RC #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX1_RD #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x0 #endif -#ifdef CONFIG_CB_4xx_CHIP_21_405EX_NO_SECURITY -#define CONFIG_CB_4xx_CHIP_21_ERRATA +#ifdef CONFIG_NB_4xx_CHIP_21_405EX_NO_SECURITY +#define CONFIG_NB_4xx_CHIP_21_ERRATA #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX2_RC #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX2_RD #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x1 #endif -#ifdef CONFIG_CB_4xx_CHIP_21_405EXr_SECURITY -#define CONFIG_CB_4xx_CHIP_21_ERRATA +#ifdef CONFIG_NB_4xx_CHIP_21_405EXr_SECURITY +#define CONFIG_NB_4xx_CHIP_21_ERRATA #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR1_RC #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR1_RD #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x2 #endif -#ifdef CONFIG_CB_4xx_CHIP_21_405EXr_NO_SECURITY -#define CONFIG_CB_4xx_CHIP_21_ERRATA +#ifdef CONFIG_NB_4xx_CHIP_21_405EXr_NO_SECURITY +#define CONFIG_NB_4xx_CHIP_21_ERRATA #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR2_RC #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR2_RD #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x3 |