xcoff: import xcoff changes from nekernel to fw.

meta: alongside other important changes (such as indexing boot offset as
volatile)

Signed-off-by: Amlal El Mahrouss <amlal@nekernel.org>

6 files changed, 140 insertions, 118 deletions

diff --git a/lib/30pin.h b/lib/30pin.h
index f194b66..71d998d 100644
--- a/lib/30pin.h
+++ b/lib/30pin.h
@@ -6,12 +6,21 @@
 
 #pragma once
 
+#include <lib/boot.h>
+
 /// @note This version is for the 30-pin recovery system.
 
-struct TRB_PACKET
+/// @brief 30pin recovery header.
+/// @param mag magic number.
+/// @param kind kind of packet we deal with.
+/// @param buffer the data of the packet.
+/// @param eop end of packet data.
+struct _cb_tpin_recovery_packet
 {
-	char mag[2];
-	char kind;
-	char buffer[498];
-	char eop[11];
-};
\ No newline at end of file
+	uint8_t mag[2];
+	uint8_t kind;
+	uint8_t buffer[498];
+	uint8_t eop[11];
+};
+
+typedef struct _cb_tpin_recovery_packet cb_tpin_recovery_packet_t;
\ No newline at end of file
diff --git a/lib/boot.h b/lib/boot.h
index a88f1cd..86efdc5 100644
--- a/lib/boot.h
+++ b/lib/boot.h
@@ -61,39 +61,39 @@ typedef ptrtype_t		 size_t;
 #define yes __yes
 
 #ifndef __cplusplus
-#define bool  boolean
+#define bool boolean
 #define false no
-#define true  yes
+#define true yes
 #endif //!_cplusplus
 
-#define SYS_RESTART	 0
-#define SYS_SHUTDOWN 1
+#define CB_RESTART	0
+#define CB_SHUTDOWN 1
 
 #define __COPYRIGHT(s) /* unused */
 
 #ifdef __COMPILE_RISCV__
-#define SYS_BOOT_ADDR		 (0x80020000)
-#define SYS_BOOT_ADDR_STR	 "0x80020000"
-#define SYS_FRAMEBUFFER_ADDR 0x40000000L
-#define SYS_UART_BASE		 0x10000000
-#define SYS_FLASH_BASE_ADDR	 0x08000000
+#define CB_BOOT_ADDR		(0x80020000)
+#define CB_BOOT_ADDR_STR	"0x80020000"
+#define CB_FRAMEBUFFER_ADDR 0x40000000L
+#define CB_UART_BASE		0x10000000
+#define CB_FLASH_BASE_ADDR	0x08000000
 
 #define cb_sync_synchronize() __sync_synchronize()
 #elif defined(__COMPILE_POWERPC__)
-#define SYS_UART_BASE		 0x10000000
-#define SYS_BOOT_ADDR		 0x1030000
-#define SYS_BOOT_ADDR_STR	 "0x1030000"
-#define SYS_FRAMEBUFFER_ADDR 0x40000000L
-#define SYS_FLASH_BASE_ADDR	 0x08000000
+#define CB_UART_BASE		0x10000000
+#define CB_BOOT_ADDR		0x1030000
+#define CB_BOOT_ADDR_STR	"0x1030000"
+#define CB_FRAMEBUFFER_ADDR 0x40000000L
+#define CB_FLASH_BASE_ADDR	0x08000000
 
 #define cb_sync_synchronize() __sync_synchronize()
 #elif defined(__COMPILE_ARM64__)
 
-#define SYS_UART_BASE		 0x09000000
-#define SYS_BOOT_ADDR		 0x1030000
-#define SYS_BOOT_ADDR_STR	 "0x1030000"
-#define SYS_FRAMEBUFFER_ADDR 0x40000000L
-#define SYS_FLASH_BASE_ADDR	 0x08000000
+#define CB_UART_BASE		0x09000000
+#define CB_BOOT_ADDR		0x1030000
+#define CB_BOOT_ADDR_STR	"0x1030000"
+#define CB_FRAMEBUFFER_ADDR 0x40000000L
+#define CB_FLASH_BASE_ADDR	0x08000000
 
 static inline void __sync_synchronize(void)
 {
@@ -103,20 +103,20 @@ static inline void __sync_synchronize(void)
 #define cb_sync_synchronize() __sync_synchronize()
 #endif // ifndef __COMPILE_POWERPC__
 
-#define SYS_BAUDRATE_TABLE                                            \
+#define CB_BAUDRATE_TABLE                                             \
 	{                                                                 \
 		300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 \
 	}
 
-#define SYS_STRING(s) #s
+#define CB_STRING(s) #s
 
-#define SYS_BOOT_MAG_0 'C'
-#define SYS_BOOT_MAG_1 'B'
+#define CB_BOOT_MAG_0 'C'
+#define CB_BOOT_MAG_1 'B'
 
-#define SYS_BOOT_VER 0x101
+#define CB_BOOT_VER 0x101
 
-#define SYS_BOOT_CALL(struct, offset)                      \
-	cb_proc_t proc_##offset = (cb_proc_t)(struct->offset); \
+#define CB_BOOT_CALL(struct, offset)                                         \
+	volatile cb_proc_t proc_##offset = (volatile cb_proc_t)(struct->offset); \
 	proc_##offset();
 
 /// @brief floating point representation (IEE 7554) in a C structure
diff --git a/lib/pci-tree.h b/lib/pci-tree.h
index 3bd64d5..9b83da0 100644
--- a/lib/pci-tree.h
+++ b/lib/pci-tree.h
@@ -16,8 +16,8 @@
 #define PCI_INVALID_DATA_U16 ((uint16_t)~0)
 #define PCI_INVALID_DATA_U32 ((uint32_t)~0)
 
-#define SYS_BASE_ADDRESS  (0x20008000) /* PCI base mapped in virtual memory. */
-#define SYS_PCI_TREE_BASE (0x802000)   /* The PCI tree base address. */
+#define CB_BASE_ADDRESS	 (0x20008000) /* PCI base mapped in virtual memory. */
+#define CB_PCI_TREE_BASE (0x802000)	  /* The PCI tree base address. */
 
 #define PCI_CONFIG_SPACE (4096U)
 
@@ -26,12 +26,12 @@
 #define PCI_FN_MAX	(8U)
 
 /* version 1.0 */
-#define SYS_PCI_VERSION (0x0100)
+#define CB_PCI_VERSION (0x0100)
 
-#define SYS_PCI_DEV_MAGIC (0xfeedd00d)
-#define SYS_PCI_INT_SZ	  sizeof(cb_pci_num_t)
+#define CB_PCI_DEV_MAGIC (0xfeedd00d)
+#define CB_PCI_INT_SZ	 sizeof(cb_pci_num_t)
 
-#define SYS_PCI_NAME_LEN (255U)
+#define CB_PCI_NAME_LEN (255U)
 
 typedef char	  cb_pci_char_t;
 typedef uintptr_t cb_pci_num_t;
@@ -54,7 +54,7 @@ struct hw_cb_pci_tree
 	cb_pci_num_t d_first_node;
 	cb_pci_num_t d_next_sibling;
 
-	cb_pci_char_t d_name[SYS_PCI_NAME_LEN];
+	cb_pci_char_t d_name[CB_PCI_NAME_LEN];
 };
 
 /// @brief Init PCI tree.
diff --git a/lib/ppc64/mmu.h b/lib/ppc64/mmu.h
index 206876e..d68fcf5 100644
--- a/lib/ppc64/mmu.h
+++ b/lib/ppc64/mmu.h
@@ -413,7 +413,7 @@ extern void print_bats(void);
 #define MAS0_TLBSEL(x)	(((x) << 28) & MAS0_TLBSEL_MSK)
 #define MAS0_ESEL_MSK	0x0FFF0000
 #define MAS0_ESEL(x)	(((x) << 16) & MAS0_ESEL_MSK)
-#define MAS0_NV(x)		((x) & 0x00000FFF)
+#define MAS0_NV(x)		((x)&0x00000FFF)
 
 #define MAS1_VALID		  0x80000000
 #define MAS1_IPROT		  0x40000000
@@ -470,9 +470,9 @@ extern void print_bats(void);
 	 (((ts) << 12) & MAS1_TS) |                  \
 	 (MAS1_TSIZE(tsize)))
 #define FSL_BOOKE_MAS2(epn, wimge) \
-	(((epn) & MAS3_RPN) | (wimge))
+	(((epn)&MAS3_RPN) | (wimge))
 #define FSL_BOOKE_MAS3(rpn, user, perms) \
-	(((rpn) & MAS3_RPN) | (user) | (perms))
+	(((rpn)&MAS3_RPN) | (user) | (perms))
 #define FSL_BOOKE_MAS7(rpn) \
 	(((uint64_t)(rpn)) >> 32)
 
@@ -640,10 +640,10 @@ extern int					  num_tlb_entries;
 
 /* Some handy macros */
 
-#define EPN(e)			((e) & 0xfffffc00)
+#define EPN(e)			((e)&0xfffffc00)
 #define TLB0(epn, sz)	((EPN((epn)) | (sz) | TLB_VALID))
-#define TLB1(rpn, erpn) (((rpn) & 0xfffffc00) | (erpn))
-#define TLB2(a)			((a) & 0x00000fbf)
+#define TLB1(rpn, erpn) (((rpn)&0xfffffc00) | (erpn))
+#define TLB2(a)			((a)&0x00000fbf)
 
 #define tlbtab_start \
 	mflr r1;         \
diff --git a/lib/ppc64/processor.h b/lib/ppc64/processor.h
index 02a6d8a..602ff08 100644
--- a/lib/ppc64/processor.h
+++ b/lib/ppc64/processor.h
@@ -141,36 +141,36 @@ struct pt_regs
 #define SPRN_DBCR		0x3F2 /* Debug Control Regsiter */
 #define DBCR_EDM		0x80000000
 #define DBCR_IDM		0x40000000
-#define DBCR_RST(x)		(((x) & 0x3) << 28)
+#define DBCR_RST(x)		(((x)&0x3) << 28)
 #define DBCR_RST_NONE	0
 #define DBCR_RST_CORE	1
 #define DBCR_RST_CHIP	2
 #define DBCR_RST_SYSTEM 3
-#define DBCR_IC			0x08000000			/* Instruction Completion Debug Evnt */
-#define DBCR_BT			0x04000000			/* Branch Taken Debug Event */
-#define DBCR_EDE		0x02000000			/* Exception Debug Event */
-#define DBCR_TDE		0x01000000			/* TRAP Debug Event */
-#define DBCR_FER		0x00F80000			/* First Events Remaining Mask */
-#define DBCR_FT			0x00040000			/* Freeze Timers on Debug Event */
-#define DBCR_IA1		0x00020000			/* Instr. Addr. Compare 1 Enable */
-#define DBCR_IA2		0x00010000			/* Instr. Addr. Compare 2 Enable */
-#define DBCR_D1R		0x00008000			/* Data Addr. Compare 1 Read Enable */
-#define DBCR_D1W		0x00004000			/* Data Addr. Compare 1 Write Enable */
-#define DBCR_D1S(x)		(((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
+#define DBCR_IC			0x08000000		  /* Instruction Completion Debug Evnt */
+#define DBCR_BT			0x04000000		  /* Branch Taken Debug Event */
+#define DBCR_EDE		0x02000000		  /* Exception Debug Event */
+#define DBCR_TDE		0x01000000		  /* TRAP Debug Event */
+#define DBCR_FER		0x00F80000		  /* First Events Remaining Mask */
+#define DBCR_FT			0x00040000		  /* Freeze Timers on Debug Event */
+#define DBCR_IA1		0x00020000		  /* Instr. Addr. Compare 1 Enable */
+#define DBCR_IA2		0x00010000		  /* Instr. Addr. Compare 2 Enable */
+#define DBCR_D1R		0x00008000		  /* Data Addr. Compare 1 Read Enable */
+#define DBCR_D1W		0x00004000		  /* Data Addr. Compare 1 Write Enable */
+#define DBCR_D1S(x)		(((x)&0x3) << 12) /* Data Adrr. Compare 1 Size */
 #define DAC_BYTE		0
 #define DAC_HALF		1
 #define DAC_WORD		2
 #define DAC_QUAD		3
-#define DBCR_D2R		0x00000800		   /* Data Addr. Compare 2 Read Enable */
-#define DBCR_D2W		0x00000400		   /* Data Addr. Compare 2 Write Enable */
-#define DBCR_D2S(x)		(((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
-#define DBCR_SBT		0x00000040		   /* Second Branch Taken Debug Event */
-#define DBCR_SED		0x00000020		   /* Second Exception Debug Event */
-#define DBCR_STD		0x00000010		   /* Second Trap Debug Event */
-#define DBCR_SIA		0x00000008		   /* Second IAC Enable */
-#define DBCR_SDA		0x00000004		   /* Second DAC Enable */
-#define DBCR_JOI		0x00000002		   /* JTAG Serial Outbound Int. Enable */
-#define DBCR_JII		0x00000001		   /* JTAG Serial Inbound Int. Enable */
+#define DBCR_D2R		0x00000800		 /* Data Addr. Compare 2 Read Enable */
+#define DBCR_D2W		0x00000400		 /* Data Addr. Compare 2 Write Enable */
+#define DBCR_D2S(x)		(((x)&0x3) << 8) /* Data Addr. Compare 2 Size */
+#define DBCR_SBT		0x00000040		 /* Second Branch Taken Debug Event */
+#define DBCR_SED		0x00000020		 /* Second Exception Debug Event */
+#define DBCR_STD		0x00000010		 /* Second Trap Debug Event */
+#define DBCR_SIA		0x00000008		 /* Second IAC Enable */
+#define DBCR_SDA		0x00000004		 /* Second DAC Enable */
+#define DBCR_JOI		0x00000002		 /* JTAG Serial Outbound Int. Enable */
+#define DBCR_JII		0x00000001		 /* JTAG Serial Inbound Int. Enable */
 #ifndef CONFIG_BOOKE
 #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
 #else
@@ -395,27 +395,27 @@ struct pt_regs
 #define TCR_WP(x) (((64 - x) & 0x3) << 30) | \
 					  (((64 - x) & 0x3c) << 15) /* WDT Period 2^x clocks*/
 #else
-#define TCR_WP(x) (((x) & 0x3) << 30)	 /* WDT Period */
-#define WP_2_17	  0						 /* 2^17 clocks */
-#define WP_2_21	  1						 /* 2^21 clocks */
-#define WP_2_25	  2						 /* 2^25 clocks */
-#define WP_2_29	  3						 /* 2^29 clocks */
-#endif									 /* CONFIG_E500 */
-#define TCR_WRC(x)	 (((x) & 0x3) << 28) /* WDT Reset Control */
-#define WRC_NONE	 0					 /* No reset will occur */
-#define WRC_CORE	 1					 /* Core reset will occur */
-#define WRC_CHIP	 2					 /* Chip reset will occur */
-#define WRC_SYSTEM	 3					 /* System reset will occur */
-#define TCR_WIE		 0x08000000			 /* WDT Interrupt Enable */
-#define TCR_PIE		 0x04000000			 /* PIT Interrupt Enable */
-#define TCR_FP(x)	 (((x) & 0x3) << 24) /* FIT Period */
-#define FP_2_9		 0					 /* 2^9 clocks */
-#define FP_2_13		 1					 /* 2^13 clocks */
-#define FP_2_17		 2					 /* 2^17 clocks */
-#define FP_2_21		 3					 /* 2^21 clocks */
-#define TCR_FIE		 0x00800000			 /* FIT Interrupt Enable */
-#define TCR_ARE		 0x00400000			 /* Auto Reload Enable */
-#define SPRN_THRM1	 0x3FC				 /* Thermal Management Register 1 */
+#define TCR_WP(x) (((x)&0x3) << 30)	   /* WDT Period */
+#define WP_2_17	  0					   /* 2^17 clocks */
+#define WP_2_21	  1					   /* 2^21 clocks */
+#define WP_2_25	  2					   /* 2^25 clocks */
+#define WP_2_29	  3					   /* 2^29 clocks */
+#endif								   /* CONFIG_E500 */
+#define TCR_WRC(x)	 (((x)&0x3) << 28) /* WDT Reset Control */
+#define WRC_NONE	 0				   /* No reset will occur */
+#define WRC_CORE	 1				   /* Core reset will occur */
+#define WRC_CHIP	 2				   /* Chip reset will occur */
+#define WRC_SYSTEM	 3				   /* System reset will occur */
+#define TCR_WIE		 0x08000000		   /* WDT Interrupt Enable */
+#define TCR_PIE		 0x04000000		   /* PIT Interrupt Enable */
+#define TCR_FP(x)	 (((x)&0x3) << 24) /* FIT Period */
+#define FP_2_9		 0				   /* 2^9 clocks */
+#define FP_2_13		 1				   /* 2^13 clocks */
+#define FP_2_17		 2				   /* 2^17 clocks */
+#define FP_2_21		 3				   /* 2^21 clocks */
+#define TCR_FIE		 0x00800000		   /* FIT Interrupt Enable */
+#define TCR_ARE		 0x00400000		   /* Auto Reload Enable */
+#define SPRN_THRM1	 0x3FC			   /* Thermal Management Register 1 */
 #define THRM1_TIN	 (1 << 0)
 #define THRM1_TIV	 (1 << 1)
 #define THRM1_THRES	 (0x7f << 2)
@@ -429,26 +429,26 @@ struct pt_regs
 #ifndef CONFIG_BOOKE
 #define SPRN_TSR 0x3D8 /* Timer Status Register */
 #else
-#define SPRN_TSR 0x150					/* Book E Timer Status Register */
-#endif									/* CONFIG_BOOKE */
-#define TSR_ENW		0x80000000			/* Enable Next Watchdog */
-#define TSR_WIS		0x40000000			/* WDT Interrupt Status */
-#define TSR_WRS(x)	(((x) & 0x3) << 28) /* WDT Reset Status */
-#define WRS_NONE	0					/* No WDT reset occurred */
-#define WRS_CORE	1					/* WDT forced core reset */
-#define WRS_CHIP	2					/* WDT forced chip reset */
-#define WRS_SYSTEM	3					/* WDT forced system reset */
-#define TSR_PIS		0x08000000			/* PIT Interrupt Status */
-#define TSR_FIS		0x04000000			/* FIT Interrupt Status */
-#define SPRN_UMMCR0 0x3A8				/* User Monitor Mode Control Register 0 */
-#define SPRN_UMMCR1 0x3AC				/* User Monitor Mode Control Register 0 */
-#define SPRN_UPMC1	0x3A9				/* User Performance Counter Register 1 */
-#define SPRN_UPMC2	0x3AA				/* User Performance Counter Register 2 */
-#define SPRN_UPMC3	0x3AD				/* User Performance Counter Register 3 */
-#define SPRN_UPMC4	0x3AE				/* User Performance Counter Register 4 */
-#define SPRN_USIA	0x3AB				/* User Sampled Instruction Address Register */
-#define SPRN_XER	0x001				/* Fixed Point Exception Register */
-#define SPRN_ZPR	0x3B0				/* Zone Protection Register */
+#define SPRN_TSR 0x150				  /* Book E Timer Status Register */
+#endif								  /* CONFIG_BOOKE */
+#define TSR_ENW		0x80000000		  /* Enable Next Watchdog */
+#define TSR_WIS		0x40000000		  /* WDT Interrupt Status */
+#define TSR_WRS(x)	(((x)&0x3) << 28) /* WDT Reset Status */
+#define WRS_NONE	0				  /* No WDT reset occurred */
+#define WRS_CORE	1				  /* WDT forced core reset */
+#define WRS_CHIP	2				  /* WDT forced chip reset */
+#define WRS_SYSTEM	3				  /* WDT forced system reset */
+#define TSR_PIS		0x08000000		  /* PIT Interrupt Status */
+#define TSR_FIS		0x04000000		  /* FIT Interrupt Status */
+#define SPRN_UMMCR0 0x3A8			  /* User Monitor Mode Control Register 0 */
+#define SPRN_UMMCR1 0x3AC			  /* User Monitor Mode Control Register 0 */
+#define SPRN_UPMC1	0x3A9			  /* User Performance Counter Register 1 */
+#define SPRN_UPMC2	0x3AA			  /* User Performance Counter Register 2 */
+#define SPRN_UPMC3	0x3AD			  /* User Performance Counter Register 3 */
+#define SPRN_UPMC4	0x3AE			  /* User Performance Counter Register 4 */
+#define SPRN_USIA	0x3AB			  /* User Sampled Instruction Address Register */
+#define SPRN_XER	0x001			  /* Fixed Point Exception Register */
+#define SPRN_ZPR	0x3B0			  /* Zone Protection Register */
 
 /* Book E definitions */
 #define SPRN_DECAR	 0x036 /* Decrementer Auto Reload Register */
@@ -853,7 +853,7 @@ struct pt_regs
 #define IOCR_PTD	0x00000400
 #define IOCR_ARE	0x00000080
 #define IOCR_DRC	0x00000020
-#define IOCR_RDM(x) (((x) & 0x3) << 3)
+#define IOCR_RDM(x) (((x)&0x3) << 3)
 #define IOCR_TCS	0x00000004
 #define IOCR_SCS	0x00000002
 #define IOCR_SPC	0x00000001
@@ -1022,29 +1022,29 @@ struct pt_regs
 /*
  * 405EX/EXr CHIP_21 Errata
  */
-#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
-#define CONFIG_SYS_4xx_CHIP_21_ERRATA
+#ifdef CONFIG_CB_4xx_CHIP_21_405EX_SECURITY
+#define CONFIG_CB_4xx_CHIP_21_ERRATA
 #define CONFIG_405EX_CHIP21_PVR_REV_C	PVR_405EX1_RC
 #define CONFIG_405EX_CHIP21_PVR_REV_D	PVR_405EX1_RD
 #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x0
 #endif
 
-#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY
-#define CONFIG_SYS_4xx_CHIP_21_ERRATA
+#ifdef CONFIG_CB_4xx_CHIP_21_405EX_NO_SECURITY
+#define CONFIG_CB_4xx_CHIP_21_ERRATA
 #define CONFIG_405EX_CHIP21_PVR_REV_C	PVR_405EX2_RC
 #define CONFIG_405EX_CHIP21_PVR_REV_D	PVR_405EX2_RD
 #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x1
 #endif
 
-#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY
-#define CONFIG_SYS_4xx_CHIP_21_ERRATA
+#ifdef CONFIG_CB_4xx_CHIP_21_405EXr_SECURITY
+#define CONFIG_CB_4xx_CHIP_21_ERRATA
 #define CONFIG_405EX_CHIP21_PVR_REV_C	PVR_405EXR1_RC
 #define CONFIG_405EX_CHIP21_PVR_REV_D	PVR_405EXR1_RD
 #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x2
 #endif
 
-#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY
-#define CONFIG_SYS_4xx_CHIP_21_ERRATA
+#ifdef CONFIG_CB_4xx_CHIP_21_405EXr_NO_SECURITY
+#define CONFIG_CB_4xx_CHIP_21_ERRATA
 #define CONFIG_405EX_CHIP21_PVR_REV_C	PVR_405EXR2_RC
 #define CONFIG_405EX_CHIP21_PVR_REV_D	PVR_405EXR2_RD
 #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x3
@@ -1252,7 +1252,7 @@ int fsl_qoriq_dsp_core_to_cluster(unsigned int core);
 #if defined(CONFIG_MPC83xx)
 #define CPU_TYPE_ENTRY(x) \
 	{                     \
-		#x, SPR_##x       \
+#x, SPR_##x       \
 	}
 #endif
 #endif
diff --git a/lib/xcoff.h b/lib/xcoff.h
index 03223ef..ed19029 100644
--- a/lib/xcoff.h
+++ b/lib/xcoff.h
@@ -18,6 +18,8 @@
 
 #define XCOFF_MAG 0x01F7
 
+#define XCOFF_NAME_LEN 256U
+
 #define XCOFF_REL_FLG	0x0001
 #define XCOFF_EXEC_FLG	0x0002
 #define XCOFF_LNNO_FLG	0x0004
@@ -35,6 +37,17 @@ typedef struct _xcoff_header
 	uint16_t opthdr; // ?: Number of bytes in optional header
 } xcoff_header_t;
 
+/// @brief This the executable's manifest fork, designed for NeFS.
+/// @param prop_xml_fork The XML fork of the executable.
+/// @param dyld_fork The DYLD fork metadata.
+/// @param code_sign_fork Executable's certificate contained in a fork.
+typedef struct _xcoff_fork_header
+{
+	char prop_xml_fork[XCOFF_NAME_LEN];
+	char dyld_fork[XCOFF_NAME_LEN];
+	char code_sign_fork[XCOFF_NAME_LEN];
+} xcoff_fork_header_t;
+
 typedef xcoff_header_t xcoff_header64_t;
 typedef xcoff_header_t xcoff_header32_t;