diff options
| author | Amlal El Mahrouss <amlal@nekernel.org> | 2025-03-29 05:08:35 +0100 |
|---|---|---|
| committer | Amlal El Mahrouss <amlal@nekernel.org> | 2025-03-29 05:08:35 +0100 |
| commit | 51cd421030c52aa16e76811d3497d9a7ab2b1bec (patch) | |
| tree | c6f01df11faf8fc37993e0f342e4c82cab724555 /src/ppc64 | |
| parent | fcc66b0fa04b25b206e702110ed652fd4c113823 (diff) | |
xcoff: import xcoff changes from nekernel to fw.
meta: alongside other important changes (such as indexing boot offset as
volatile)
Signed-off-by: Amlal El Mahrouss <amlal@nekernel.org>
Diffstat (limited to 'src/ppc64')
| -rw-r--r-- | src/ppc64/ppc64-boot.S | 6 | ||||
| -rw-r--r-- | src/ppc64/ppc64-hal.c | 39 | ||||
| -rw-r--r-- | src/ppc64/ppc64-uart.c | 6 |
3 files changed, 26 insertions, 25 deletions
diff --git a/src/ppc64/ppc64-boot.S b/src/ppc64/ppc64-boot.S index 17d6fa5..28d1865 100644 --- a/src/ppc64/ppc64-boot.S +++ b/src/ppc64/ppc64-boot.S @@ -29,11 +29,11 @@ cb_reset_vector: .global cb_start_context
.global cb_boot_processor_ready
-.equ SYS_BOOT_ADDR, 0x1030000
+.equ CB_BOOT_ADDR, 0x1030000
cb_start_rom:
- lis 3, SYS_BOOT_ADDR@h
- addi 3, 3, SYS_BOOT_ADDR@l
+ lis 3, CB_BOOT_ADDR@h
+ addi 3, 3, CB_BOOT_ADDR@l
blr
diff --git a/src/ppc64/ppc64-hal.c b/src/ppc64/ppc64-hal.c index 53e16d2..f47f0b3 100644 --- a/src/ppc64/ppc64-hal.c +++ b/src/ppc64/ppc64-hal.c @@ -36,6 +36,7 @@ void cb_set_tlb(uint8_t tlb, // this mmu-version does not allow odd tsize values
return;
}
+
uint32_t mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
uint32_t mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
uint32_t mas2 = FSL_BOOKE_MAS2(epn, wimge);
@@ -52,18 +53,18 @@ void cb_init_hw(void) /// amlal:
/// map VGA framebuffer
- cb_set_tlb(0, SYS_FRAMEBUFFER_ADDR, /* v_addr, 0x0000A0000 */
- 0x0000A000, /* p_addr. 0x0000A0000 */
- MAS3_SW | MAS3_SR, /* perm type=TLB_MAP_IO */
- MAS2_I | MAS2_G, /* wimge type=TLB_MAP_IO */
- 0, /* ts i.e AS=0 */
- 1, /* esel (a.k.a tlb_index*/
- BOOKE_PAGESZ_64K, /* tsize ie 2^10kB ie 1MB */
+ cb_set_tlb(0, CB_FRAMEBUFFER_ADDR, /* v_addr, 0x0000A0000 */
+ 0x0000A000, /* p_addr. 0x0000A0000 */
+ MAS3_SW | MAS3_SR, /* perm type=TLB_MAP_IO */
+ MAS2_I | MAS2_G, /* wimge type=TLB_MAP_IO */
+ 0, /* ts i.e AS=0 */
+ 1, /* esel (a.k.a tlb_index*/
+ BOOKE_PAGESZ_64K, /* tsize ie 2^10kB ie 1MB */
1);
// map ccsrbar and uart.
// at start we execute from esel = 0, so chose something else..
- cb_set_tlb(1, SYS_UART_BASE, /* v_addr 0xe0000000 see qemu-ppce500.h */
+ cb_set_tlb(1, CB_UART_BASE, /* v_addr 0xe0000000 see qemu-ppce500.h */
0xfe0000000, /* p_addr. 0xfe0000000 */
MAS3_SW | MAS3_SR, /* perm type=TLB_MAP_IO */
MAS2_I | MAS2_G, /* wimge type=TLB_MAP_IO */
@@ -74,21 +75,21 @@ void cb_init_hw(void) /// amlal:
/// map pci base for kernel
- cb_set_tlb(0, SYS_BASE_ADDRESS, /* v_addr, 0xFE008000 */
- 0xFE0008000, /* p_addr. 0xfe0000000 */
- MAS3_SW | MAS3_SR, /* perm type=TLB_MAP_IO */
- MAS2_I | MAS2_G, /* wimge type=TLB_MAP_IO */
- 0, /* ts i.e AS=0 */
- 3, /* esel (a.k.a tlb_index*/
- BOOKE_PAGESZ_1M, /* tsize ie 2^10kB ie 1MB */
+ cb_set_tlb(0, CB_BASE_ADDRESS, /* v_addr, 0xFE008000 */
+ 0xFE0008000, /* p_addr. 0xfe0000000 */
+ MAS3_SW | MAS3_SR, /* perm type=TLB_MAP_IO */
+ MAS2_I | MAS2_G, /* wimge type=TLB_MAP_IO */
+ 0, /* ts i.e AS=0 */
+ 3, /* esel (a.k.a tlb_index*/
+ BOOKE_PAGESZ_1M, /* tsize ie 2^10kB ie 1MB */
1);
cb_pci_init_tree();
- cb_pci_append_tree("@fb", SYS_FRAMEBUFFER_ADDR, 0x0);
- cb_pci_append_tree("@mbci", 0x0, 0x0);
- cb_pci_append_tree("@serial", SYS_UART_BASE, 0);
- cb_pci_append_tree("@pci", SYS_BASE_ADDRESS, 0x0);
+ cb_pci_append_tree("@fb", CB_FRAMEBUFFER_ADDR, 0x0);
+ cb_pci_append_tree("@mbci", 0x0, 0x0); // did not found a MBCI base for now...
+ cb_pci_append_tree("@serial", CB_UART_BASE, 0);
+ cb_pci_append_tree("@pci", CB_BASE_ADDRESS, 0x0);
cb_flush_tlb();
}
diff --git a/src/ppc64/ppc64-uart.c b/src/ppc64/ppc64-uart.c index 0a01857..c908eae 100644 --- a/src/ppc64/ppc64-uart.c +++ b/src/ppc64/ppc64-uart.c @@ -9,10 +9,10 @@ /// BUGS: 0
-#define SYS_NS16550_COM1 (SYS_UART_BASE + 0x4500)
-#define SYS_NS16550_COM2 (SYS_UART_BASE + 0x4600)
+#define CB_NS16550_COM1 (CB_UART_BASE + 0x4500)
+#define CB_NS16550_COM2 (CB_UART_BASE + 0x4600)
-volatile ascii_char_t* const UART0DR = (ascii_char_t*)SYS_NS16550_COM1;
+volatile ascii_char_t* const UART0DR = (ascii_char_t*)CB_NS16550_COM1;
/* this file handles the UART */
|