diff options
| author | Amlal <amlal.elmahrouss@icloud.com> | 2025-02-20 11:58:55 +0100 |
|---|---|---|
| committer | Amlal <amlal.elmahrouss@icloud.com> | 2025-02-20 11:58:55 +0100 |
| commit | aa8a096ad429640e752d69a89c572da35493d4c0 (patch) | |
| tree | 4616c7cf8f8baedfa91e46eba9a6c76ab10de7a2 /dev/Kernel/HALKit/AMD64/HalPagingMgrAMD64.cc | |
| parent | 807dbca22a151713ff7b7527cbf66b6c350ed938 (diff) | |
FS, DriveMgr, AHCI: Actively working on it.
PagingMgr: Define get_phys_address in C++ source directly.
Signed-off-by: Amlal <amlal.elmahrouss@icloud.com>
Diffstat (limited to 'dev/Kernel/HALKit/AMD64/HalPagingMgrAMD64.cc')
| -rw-r--r-- | dev/Kernel/HALKit/AMD64/HalPagingMgrAMD64.cc | 82 |
1 files changed, 61 insertions, 21 deletions
diff --git a/dev/Kernel/HALKit/AMD64/HalPagingMgrAMD64.cc b/dev/Kernel/HALKit/AMD64/HalPagingMgrAMD64.cc index ab8c5b97..442e9b83 100644 --- a/dev/Kernel/HALKit/AMD64/HalPagingMgrAMD64.cc +++ b/dev/Kernel/HALKit/AMD64/HalPagingMgrAMD64.cc @@ -3,7 +3,7 @@ Copyright (C) 2024-2025, Amlal EL Mahrouss, all rights reserved. File: HalPagingMgr.cc - Purpose: Platform Paging Manager.. + Purpose: Platform Paging Manager. ------------------------------------------- */ @@ -50,6 +50,50 @@ namespace Kernel::HAL } }; + /// @brief Go over the Page structure and find the address of *virtual_address* + + UInt64 hal_get_phys_address(VoidPtr virtual_address) + { + // Constants for table index bits + const UInt64 kPmlIndexMask = 0x1FFULL; // Mask for PML4, PDPT, PD, PT index (9 bits) + const UInt64 kPtIndexMask = 0xFFFULL; // Mask for page table index (12 bits) + + UInt64 cr3 = (UInt64)hal_read_cr3(); + + NE_PAGE_STORE& page_store = NE_PAGE_STORE::The(); + + // Extract the indices from the virtual address + UInt64 pml4_index = ((UIntPtr)virtual_address >> 39) & kPmlIndexMask; + UInt64 pdpt_index = ((UIntPtr)virtual_address >> 30) & kPmlIndexMask; + UInt64 pd_index = ((UIntPtr)virtual_address >> 21) & kPmlIndexMask; + UInt64 pt_index = ((UIntPtr)virtual_address >> 12) & kPmlIndexMask; + + page_store.fStoreOp = Yes; + + const auto kPmlEntrySize = 8; + + // Read the PML4 entry from memory + UInt64 pml4_base = cr3 & ~kPtIndexMask; // CR3 points to the PML4 table base, mask off lower bits + UInt64 pml4_entry = (pml4_base + pml4_index * kPmlEntrySize); // Each entry is 8 bytes + + // Read the PDPT entry + UInt64 pdpt_base = pml4_entry & ~kPtIndexMask; // Get the PDPT base physical address + UInt64 pdpt_entry = (pdpt_base + pdpt_index * kPmlEntrySize); + + // Read the PD entry + UInt64 pd_base = pdpt_entry & ~kPtIndexMask; // Get the Page Directory base physical address + UInt64 pd_entry = (pd_base + pd_index * kPmlEntrySize); + + // Read the PT entry + UInt64 pt_base = pd_entry & ~kPtIndexMask; // Get the Page Table base physical address + UInt64 pt_entry = (pt_base + pt_index * kPmlEntrySize); + + // Lastly, grab the pte entry. + NE_PDE* pde_struct = reinterpret_cast<NE_PDE*>(pt_base); + + return pde_struct->fEntries[pt_entry]->PhysicalAddress; + } + /***********************************************************************************/ /// \brief Retrieve the page status of a PTE. /// \param pte Page Table Entry pointer. @@ -62,7 +106,7 @@ namespace Kernel::HAL kout << (pte->User ? "User" : "Not User") << endl; } - STATIC Int32 mmi_map_page_table_entry(UInt32 virtual_address, UInt32 flags, NE_PTE* pt_entry, NE_PDE* pd_entry); + STATIC Int32 mmi_map_page_table_entry(UInt32 physical_address, UInt32 flags, NE_PTE* pt_entry, NE_PDE* pd_entry); /***********************************************************************************/ /// @brief Maps or allocates a page from virtual_address. @@ -73,43 +117,39 @@ namespace Kernel::HAL /***********************************************************************************/ EXTERN_C Int32 mm_map_page(VoidPtr virtual_address, VoidPtr physical_address, UInt32 flags) { - if (!virtual_address || - !flags) - return 0; - // Constants for table index bits - const UInt64 cPmlIndexMask = 0x1FFULL; // Mask for PML4, PDPT, PD, PT index (9 bits) - const UInt64 cPtIndexMask = 0xFFFULL; // Mask for page table index (12 bits) + const UInt64 kPmlIndexMask = 0x1FFULL; // Mask for PML4, PDPT, PD, PT index (9 bits) + const UInt64 kPtIndexMask = 0xFFFULL; // Mask for page table index (12 bits) UInt64 cr3 = (UInt64)hal_read_cr3(); NE_PAGE_STORE& page_store = NE_PAGE_STORE::The(); // Extract the indices from the virtual address - UInt64 pml4_index = ((UIntPtr)virtual_address >> 39) & cPmlIndexMask; - UInt64 pdpt_index = ((UIntPtr)virtual_address >> 30) & cPmlIndexMask; - UInt64 pd_index = ((UIntPtr)virtual_address >> 21) & cPmlIndexMask; - UInt64 pt_index = ((UIntPtr)virtual_address >> 12) & cPmlIndexMask; + UInt64 pml4_index = ((UIntPtr)virtual_address >> 39) & kPmlIndexMask; + UInt64 pdpt_index = ((UIntPtr)virtual_address >> 30) & kPmlIndexMask; + UInt64 pd_index = ((UIntPtr)virtual_address >> 21) & kPmlIndexMask; + UInt64 pt_index = ((UIntPtr)virtual_address >> 12) & kPmlIndexMask; page_store.fStoreOp = Yes; - const auto cPmlEntrySize = 8; + const auto kPmlEntrySize = 8; // Read the PML4 entry from memory - UInt64 pml4_base = cr3 & ~cPtIndexMask; // CR3 points to the PML4 table base, mask off lower bits - UInt64 pml4_entry = (pml4_base + pml4_index * cPmlEntrySize); // Each entry is 8 bytes + UInt64 pml4_base = cr3 & ~kPtIndexMask; // CR3 points to the PML4 table base, mask off lower bits + UInt64 pml4_entry = (pml4_base + pml4_index * kPmlEntrySize); // Each entry is 8 bytes // Read the PDPT entry - UInt64 pdpt_base = pml4_entry & ~cPtIndexMask; // Get the PDPT base physical address - UInt64 pdpt_entry = (pdpt_base + pdpt_index * cPmlEntrySize); + UInt64 pdpt_base = pml4_entry & ~kPtIndexMask; // Get the PDPT base physical address + UInt64 pdpt_entry = (pdpt_base + pdpt_index * kPmlEntrySize); // Read the PD entry - UInt64 pd_base = pdpt_entry & ~cPtIndexMask; // Get the Page Directory base physical address - UInt64 pd_entry = (pd_base + pd_index * cPmlEntrySize); + UInt64 pd_base = pdpt_entry & ~kPtIndexMask; // Get the Page Directory base physical address + UInt64 pd_entry = (pd_base + pd_index * kPmlEntrySize); // Read the PT entry - UInt64 pt_base = pd_entry & ~cPtIndexMask; // Get the Page Table base physical address - UInt64 pt_entry = (pt_base + pt_index * cPmlEntrySize); + UInt64 pt_base = pd_entry & ~kPtIndexMask; // Get the Page Table base physical address + UInt64 pt_entry = (pt_base + pt_index * kPmlEntrySize); // Lastly, grab the pte entry. NE_PDE* pde_struct = reinterpret_cast<NE_PDE*>(pt_base); |
